RT8125H RICHTEK | Alldatasheet
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Technical content
Features
Richtek Mach ResponseTM Technology 1% High Accuracy 0.8V Reference VCC Input Range : 4.5V to 13.2V VOUT Operating Range : 0.3V to 3.3V Power Stage Input Range : 1.5V to 24V Fixed Operating Frequency : 300kHz LG_OCSET for Current Limit Embedded Bootstrap Switch High Side Gate Driver Pull Low Resistor (10kΩΩΩΩΩ) Current Limit with Low Side Current Sense Scheme Enable Function with Mode Selection OVP/UVP/OTP/Pre-OVP/Current Limit Shutdown Current <100μμμμμA RoHS Compliant and Halogen Free High Efficiency Single Synchronous Buck PWM Controller Simplified Application Circuit
Applications
Generic DC-DC Power Regulator Mother Boards and Desktop Servers VCC UGATE FB RT8125H LGATE/ OCSET BOOT PHASE VINVCC VOUT REFIN GND REFOUT EN_MODE PGOODPGOOD 0V to 5V
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 BOOT Bootstrap supply for high-side gate driver. Connect a capacitor between this pin and the PHASE pin. 2 UGATE Gate drive output for the external high-side MOSFET. 3 PHASE Switch node. It behaves as the current sense comparator input for low side MOSFET RDS(ON) sensing and reference voltage for on-time generation.
4 LGATE/OCSET
Gate drive output for the low-side external MOSFET. Connect a resistor (ROCSET) between this pin and GND to set the output current limit level. If ROCSET is not present , or the setting threshold greater than 400mV, the OC threshold is internally present to 315mV (typ.)
5 VCC
Supply voltage input. It provides the power for the Buck controller, the low side driver and the bootstrap circuit for high side driver. Bypass to GND with a 4.7F ceramic capacitor. 6 FB VOUT feedback voltage input. Connect the FB to a resistive voltage divider from VOUT to GND to set the output voltage from 0.3V to 3.3V
7 EN_MODE
Enable and mode selection control input. When the voltage of EN_MODE pin is pulled lower than 0.4V, controller remains in shutdown. When the pin voltage is between 2.1V to 2.7V, controller operates into DEM. When the pin voltage is between 4.3V to 5V, controller operates into FCCM. 8 PGOOD Open-drain power good indicator. High impedance indicates that power is good.
9 REFIN
Reference input. Connect a current console to REFIN pin, and connect a resistor between REFIN and REFOUT to tune up/down FB reference voltage.
10 REFOUT
Reference voltage output. It provides an 1% high accuracy reference 0.8V with 2mA source/sink ability. Bypass to GND with a maximum 6.8nF ceramic capacitor. (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Marking Information
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Pin Configuration (TOP VIEW) WDFN-10L 3x3 RT8125H Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) BOOT UGATE VCC LGATE/OCSET REFOUT REFIN PGOOD FB EN_MODE PHASE GND QZ=YM DNN QZ= : Product Code YMDNN : Date Code
DS8125H-00 October 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Operation The RT8125H is suitable for low external component count configuration with appropriate amount of Equivalent Series Resistance (ESR) capacitor(s) at the output. The output ripple valley voltage is monitored at a feedback point voltage. The synchronous high side MOSFET is turned on at the beginning of each cycle. After the internal one- shot timer expires, the MOSFET is turned off. The pulse width of this one-shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the entire input voltage range. Another one- shot sets a minimum off-time (400ns typ.). The on-time comparator has two inputs, one is from the output voltage, the other is from the input voltage. The on- time of the high side switch is designed to be directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. R QS Minimum TOFF Comp VREF OVP Latch UVP Hiccup 125% VREF 50% VREF 90% VREF SS Thermal Shutdown On-time One Shot FB PHASE VCC VCC PHASE PGOOD GND LGATE/OCSET EN_MODE BOOT LDO & POR REF Gm Sample and Hold UGATE REFOUT REFIN VDET VIN Detection
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) PHASE to GND UGATE to PHASE LGATE to GND Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3)
DS8125H-00 October 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller VCC POR Threshold Rising edge 3.75 4.1 4.5 V Falling edge -- 3.8 4 VCC Quiescent Supply Current IQ FB forced above the regulation Point, EN_MODE = 5V, REFOUT Current = 0 -- 500 1250 A VCC Shutdown Current I SHDN V CC current, EN_MODE = 0V -- -- 100 A REFOUT (Note 5) V REFOUT VCC = 4.5V to 13.2V, sink/ source current = 2mA 786 794 802 mV REFOUT Source / Sink Current IREFOUT -- -- 2 mA FB Input Bias Current FB = 0.8V 1 0 1 A REFIN Input Voltage Range 0.3 -- 3.3 V Switching Frequency f SW (Note 6) 270 300 330 kHz Minimum Off-Time t OFF_MIN 250 -- -- ns Current Sensing IOCSET 9 10 11 A Soft-Start Time t SS REFIN = 0.8V, no load -- 0.7 -- ms Protection Function Current Limit Setting Range LGATE 50 -- 400 mV Current Limit Threshold R OCSET NC -- 315 -- mV UV Threshold UVP Detect, FB Lower than REFIN Voltage 225 300 375 mV OVP Threshold OVP Detect, FB Higher than REFIN Voltage 225 300 375 mV Threshold 3.35 3.5 -- V Thermal Shutdown Latch -- 140 -- C VIN Detection Threshold VDET 0.5 -- -- V Driver On-Resistance UGATE Driver Source RUGATEsr VBOOT VPHASE = 12V, source current = 100mA -- 1.5 3 UGATE Driver Sink RUGATEsk BOOT PHASE = 12V, ISINK = 10mA -- 2.25 4 LGATE Driver Source RLGATEsr VCC = 12V, source current = 100mA -- 1.5 3 LGATE Driver Sink RLGATEsk VCC = 12V, ISINK = 10mA -- 1 2 Dead Time LGATE rising (PHASE = 1.5V) -- 30 -- ns UGATE rising -- 30 -- Internal Boost Charging Switch On-Resistance VCC to BOOT, 10mA -- -- 80 (VCC = 5V, VIN = 15V, EN_MODE = 5V, TA = 25°C, unless otherwise specified)
Electrical Characteristics
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit EN_MODE Threshold EN_MODE Input Voltage VIH FCCM, V CC = 4.5V to 13.2V 4.3 -- 5 V VIH DEM, V CC = 5V to 13.2V 2.1 -- 2.7 VIH DEM, VCC = 4.5 to 5V 2.1 2.5 VIL Shutdown, V CC = 4.5V to 13.2V -- -- 0.4 EN_MODE Internal Pull Low Current V EN_MODE = 5V -- 0.7 -- A PGOOD (PGOOD High w/o OVP or UVP) PGOOD Blanking Time PGOOD rising edge after soft-start 1 3 5 ms Output Low Voltage I SINK = 4mA -- -- 0.3 V Leakage Current High state, forced to 5V -- -- 1 A Note 1. Stresses beyond those listed uner “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The reference voltage shift -6mV from 0.8V for offset canceling under feedback valley control. Note 6. No production tested. Test condition V IN = 8V, VOUT = 1.1V, IOUT = 10A using application circuit.
DS8125H-00 October 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit VCC UGATE FB RT8125H LGATE/ OCSET 1BOOT PHASE VINVCC VOUT REFIN9 GND 11 (Exposed Pad) REFOUT10 100k 4.7µF 0.1µF ROCSET 0V to 5V
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics TON vs. Temperature 360 380 400 420 440 460 480 500 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) TON (ns) VIN = VCC = 12V, VOUT = 1.5V, No Load Output Voltage vs. Temperature 1.45 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = VCC = 12V, No Load Efficiency vs. Load Current 100 0.01 0.1 1 10 100 Load Current (A) Efficiency (%) VIN = VCC = 12V, VOUT = 1.5V Output Voltage vs. Load Current 1.45 1.46 1.47 1.48 1.49 1.50 1.51 1.52 1.53 1.54 1.55 0 2 4 6 8 1 01 21 41 61 82 0 Load Current (A) Output Voltage (V) VIN = VCC = 12V Frequency vs. Load Current 100 150 200 250 300 350 400 450 0 2 4 6 8 1 01 21 41 61 82 0 Load Current (A) Frequency (kHz) 1 VIN = VCC = 12V, VOUT = 1.5V Load Transient Response Time (200 μs/Div) VIN = V CC = 12V, VOUT = 1.5V IOUT (10A/Div) VOUT (100mV/Div)
DS8125H-00 October 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. OVP Time (100 μs/Div) VOUT (1V/Div) VFB (1V/Div) VIN = VCC = 12V LGATE (20V/Div) PGOOD (5V/Div) Dynamic Output Voltage Control Time (200 μs/Div) VIN = V CC = 12V, IREFIN = -10μA x 5steps, IOUT = 10A VREFIN (200mV/Div) VOUT (100mV/Div) Dynamic Output Voltage Control Time (20 μs/Div) VIN = VCC = 12V, IREFIN = 50μA x 1steps, IOUT = 10A VREFIN (200mV/Div) VOUT (100mV/Div) Power On from EN_MODE Time (1ms/Div) PGOOD (10V/Div) VIN = VCC = 12V, IOUT = 50mA UGATE (20V/Div) VOUT (1V/Div) EN_MODE (5V/Div) Power Off from EN_MODE Time (100 μs/Div) PGOOD (10V/Div) VIN = VCC = 12V, IOUT = 10A UGATE (20V/Div) VOUT (1V/Div) EN_MODE (5V/Div)
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The RT8125H PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for CPU core, I/O, and chipset RAM supplies in notebook computers. Richtek Mach Response TM technology is specifically designed for providing 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology solves the poor load transient response timing problems of fixed frequency current mode PWMs and avoids the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes. Supply Voltage and Power On Reset (POR) The input voltage range for VCC is from 4.5 V to 13.2 V with respect to GND. An internal linear regulator regulates the supply voltage for internal control logic circuit. A minimum 0.1μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor near the IC. VCC also supplies the integrated MOSFET drivers. A bootstrap diode is embedded to facilitate PCB design and reduce the total BOM cost. No external Schottky diode is required in real applications. The Power On Reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage (4.2V typ.), the controller resets and prepares the PWM for operation. If VCC falls below the POR falling threshold during normal operation, all MOSFETs stop switching. The POR rising and falling threshold has a hysteresis (0.12V typ.) to prevent unintentional noise based reset. VIN Detection Once VCC exceeds its power on reset (POR) rising threshold voltage and the EN_MODE pin is set free, UGATE will output continuous pulses (~40kHz, 100ns), and LGATE will be forced low for converter input voltage VIN detection. If the voltage pulses at the PHASE pin are less than VIN detection threshold (V DET) when UGATE is turned off more than 3 cycles, VIN is recognized as ready. Then, the controller will initiate soft-start operation. For ensuring the VIN can be defected, the Phase to GND can't place schottky diode to avoid the phase voltage will be clamped to around -0.3V. Enable and Mode Selection The EN_MODE pin is a multi-function pin for integrated enable and mode selection. The controller will operate in different mode according to different EN_MODE input voltage level. When the voltage of EN_MODE pin is pulled lower than 0.4V, controller remains in shutdown. When the pin voltage is between 2.1V to 2.7V, controller operates into DEM. When the pin voltage is between 4.3V to 5V, controller operates into FCCM. Figure 1 shows a recommend circuit for EN_MODE control. Complete function requires a resistor divider that connected from 5V source to EN_MODE pin and two N-channel MOSFETs switch. The Q1 switch is used to determine the pin voltage for different operation mode, DEM or FCCM. The Q2 switch is used to enable or disable the RT8125H. Except to confirm that the resistor divider value can pull up the voltage of EN_MODE pin, also need to ensure the 5V source will not be pulled down by divider. Refer to Table 1 for control input level and mode state mapping results. Figure 1. EN_MODE Pin Recommend Circuit Table 1. States of EN_MODE Control Circuit
©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 2. Soft-Start Timing Chart
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. where VBOOT represents the voltage across the bootstrap capacitor and fSW is the switching frequency. It is important to ensure the package can dissipate the switching loss and have enough room for safe operation. Inductor Selection The inductor plays an important role in step-down converters because it stores the energy from the input power rail and then releases the energy to the load. From the viewpoint of efficiency, the DC Resistance (DCR) of the inductor should be as small as possible to minimize the conduction loss. In addition, the inductor covers a significant proportion of the board space, so its size is also important. Low profile inductors can save board space especially when the height has a limitation. However, low DCR and low profile inductors are usually not cost effective. Additionally, larger inductance results in lower ripple current, which translates into the lower power loss. The inductor current rising time increases with inductance value. This means the transient response will be slower. Therefore, the inductor design is a trade-off among performance, size and cost. In general, inductance is chosen such that the ripple current ranges between 20% to 40% of the full load current. The inductance can be calculated using the following equation : IN OUT OUT(MIN) SW OUT_Full Load IN VV VL = fk I V where k is the ratio between inductor ripple current and rated output current. Input Capacitor Selection Voltage rating and current rating are the key parameters when selecting an input capacitor. Conservatively speaking, an input capacitor should have a voltage rating 1.5 times greater than the maximum input voltage to be considered a safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : OUT OUTRMS OUT IN IN VVI = I 1 VV OUT_ESR LV = I E S R OUT_C L OUT SW The next step is to select a proper capacitor for the RMS current rating. Using more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank is a good design. Placing a ceramic capacitor close to the drain of the high side MOSFET can also be helpful in reducing the input voltage ripple at heavy load. Output Capacitor Selection The output capacitor and the inductor form a low-pass filter in the Buck topology. In steady state condition, the ripple current flowing into/out of the capacitor results in voltage ripple. The output voltage ripples contains two components, ΔV OUT_ESR and ΔVOUT_C. When load transient occurs, the output capacitor supplies the load current before controller can respond. Therefore, the ESR will dominate the output voltage sag during load transient. The output voltage sag can be calculated using the following equation : OUT_SAG OUTV = E S R I For a given output voltage sag specification, the ESR value can be determined. Another parameter that has influence on the output voltage sag is the equivalent series inductance (ESL). The rapid change in load current results in di/dt during transient. Therefore ESL contributes to part of the voltage sag. Using a capacitor with low ESL will obtain better transient performance. Generally, using several capacitors connected in parallel will also have better transient performance than just one single capacitor with the same total ESR. Unlike electrolytic capacitors, the ceramic capacitor has relatively low ESR and can reduce the voltage deviation during load transient. However, the ceramic capacitor can only provide low capacitance value. Therefore, it is suggested to use a mixed combination of electrolytic capacitor and ceramic capacitor for achieving better transient performance.
©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. have its own individual ceramic capacitor. Figure 7. Derating Curve of Maximum Power Dissipation MOSFET driver capability and the budget. on the maximum power dissipation.
DS8125H-00 October 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Make MOSFET gate driver path as short as possible. Since the gate driver uses narrow-width high current pulses to switch on/off power MOSFET, the driver path must be short to reduce the trace inductance. This is especially important for low side MOSFET, because this can reduce the possibility of shoot-through. Providing enough copper area around power MOSFETs to help heat dissipation. Using thick copper also reduces the trace resistance and inductance to have better performance. The output capacitors should be placed physically close to the load. This can minimize the trace parasitic components and improve transient response. All small signal components should be located close to the controller. The small signal components include the feedback voltage divider resistors, function setting components and high frequency bypass capacitors. The feedback voltage divider resistor must be placed close to FB pin, because the FB pin is inherently noise- sensitive. Voltage feedback path must be away from switching nodes. The noisy switching node is, for example, the interconnection between high side MOSFET, low side MOSFET and inductor. Feedback path must be away from this kind of noisy node to avoid noise pick-up. A multi-layer PCB design is recommended. Make use of one single layer as the ground and have separate layers for power rail, or signal is suitable for PCB design.
DS8125H-00 October 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A
DS8125H-00 October 2020www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Footprint Information PABCD S x S y M Package Tolerance Footprint Dimension (mm)Number of Pin