RT8113 RICHTEK | Alldatasheet

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Technical content

Features

zzzzz Single-Phase Power Conversion zzzzz One Embedded MOSFET Driver with Internal Bootstrap Diode zzzzz VID Table for Intel VR11.1 zzzzz Continuous Differential Inductor DCR Current Sense zzzzz Droop Enable/Disable Capability zzzzz Adjustable Soft-Start zzzzz Adjustable Frequency Typically at 200kHz zzzzz Power Good Indication zzzzz Adjustable Over Current Protection zzzzz Over Voltage Protection zzzzz Over Temperature Protection zzzzz Small 24-Lead WQFN Package zzzzz RoHS Compliant and Halogen Free Marking Information VID1 OCSET FBRTN SS COMP FB ISN ADJ OFS RT/EN ISP VCC5 PGOOD BOOT PHASE VCC12 LGATE UGATE VID5 VID7 VID2 VID3 VID4 VID6 GND 789 1 0 1 2 11 21 20 1924 2223 DZ= : Product Code YMDNN : Date Code DZ=YM DNN Package Type QW : WQFN-24L 4x4 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) RT8113

DS8113-02 April 2011www.richtek.com Function Block Diagram Typical Application Circuit VOUT ADJ RT/EN UGATE ISN RT8113 LGATE 17BOOT OFS PHASE FB ISP 11 12V R4 C3 12V SS 4 C14 COMP 5 FBRTN 3 GNDExposed Pad (25) Load EN Option for Disable Drop VCC1214 VCC510 C11 C10 C7 C8 C12 C13 R20 R19 R13 R9 R10 R12 NTC

18 PGOOD

VCC_SNS VSS_SNS RRTQ3 OCSETR16R15 R18 R14 Option for Negative OFS Option for Positive OFS PGOOD R17 VTT Option VID [7:1] -CMP OC Current Sense /10 OV 150mV+ Transient Response Enhancement Offset VR11 VID Table Soft Start and Fault Logic VID Off EAP OC OV Control MOSFET Driver Power On Reset Regulator Modulation Waveform Generator POR VCC12 FB COMP FBRTN SS UGATE PHASE OCSET VCC12 OFS RT/EN ISP BOOT ADJ LGATE ISN VCC5 PGOOD EA GND MOSFET Driver Driver Logic Fault Logic PWM Thermal ProtectionOT

DS8113-02 April 2011 www.richtek.com Pin No. Pin Name Pin Function 2 OCSET Over Current Protection Threshold Set Pin. 3 FBRTN Return Ground. This pin is Negative Node of the differential Remote Voltage sending. 4 SS Soft-Start Ramp Slope Set Pin. Connect this pin to FBRTN by a Capacitor to Adjust soft-start slew rate. 5 COMP Compensation Pin. Output of Error Amplifier and Input of PWM comparator. 6 FB Inverting Input of Error Amplifier. 7 ADJ Droop Set Pin. Connect a resistor from this pin to GND sets the load line slope.

8 OFS

Voltage Offset Pin. This pin sets No-Load Output Voltage Offset. Connect a resistor from this Pin to VCC5 or GND to bidirection set the output voltage no-load offset.

9 RT/EN

Switching Frequency Set Pin. Connect this pin to GND via a resistor to adjust switching frequency and operate with droop function. Connect this pin to VCC5 via a resistor to adjust switching frequency and operate without droop function. 10 VCC5 Internal 5V Regulator Output. 11 ISP Non-Invertering Input of Current Sense Amplifier. 12 ISN Invertering Input of Current Sense Amplifier. 13 LGATE Lower Gate Driver. This pin drives the gate of low side MOSFETs. 14 VCC12 12V Power Supply Input Pin. 15 PHASE Switch Node of High side Driver. Connect this pin to high-side MOSFETs sources together with the low side MOSFETs drains and inductor. 16 UGATE Upper Gate Driver. This pin drives the gate of the high-side MOSFETs.

17 BOOT

Bootstrap Power Pin. This pin powers the high-side MOSFETs drivers. Connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. 18 PGOOD Power Good Indicator. 19 to 24,1 VID7 to VID1 DAC Voltage Identification Inputs. (Exposed Pad) GND Ground Pin. The exposed pad must be soldered to a large PCB and connected to AGND for maximum power dissipation. Functional Pin Description

Table 1. Output Voltage Program

DS8113-02 April 2011 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit VCC12 Supply Input VCC12 Supply Current I CC -- 6 -- mA VCC5 Power VCC5 Output Voltage V CC5 I LOAD = 10mA 4.9 5 5.1 V VCC5 Output Sourcing I VCC5 10 -- -- mA Power-On Reset VCC12 Rising Threshold V CC12_TH VCC12 Rising 9.2 9.7 10.2 V VCC12 Hysteresis V CC12_HY VCC12 Falling -- 0.9 -- V VCC5 Rising Threshold V CC5_TH VCC5 Rising 4.4 4.6 4.8 V VCC5 Hysteresis V CC5_HY VCC5 Falling -- 0.4 -- V (TA = 25°C, unless otherwise specified)

Electrical Characteristics

Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) z BOOTx to GND z PHASEx to GND z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3) To be continued To be continued

DS8113-02 April 2011www.richtek.com To be continued Parameter Symbol Test Conditions Min Typ Max Unit RT/EN Chip Disable Threshold V DIS -- -- 0.4 V Running Frequency f OSC R RT = 60kΩ 180 200 220 kHz RT Pin Voltage V RT , GND RRT = 60kΩ, connected between RT/EN and GND 1.52 1.6 1.68 V RT Pin Voltage V RT , VDD RRT = 60kΩ, connected between RT/EN and VCC5 VCC5− 1.68 VCC5− 1.6 VCC5− 1.52 V Modulation Gain A RAMP RRT = 60kΩ -- 22 -- %/V Reference Voltage Accuracy 0.8V to 1V −5 -- 5 mV DAC Accuracy 0.5V to 0.8V −8 -- 8 mV Logic-Low V IL VID [7:1] -- -- 0.4 V VID Threshold Voltage Logic-High V IH VID [7:1] 0.8 -- -- V Error Amplifier DC Gain A DC No Load -- 80 -- dB Gain-Bandwidth GBW C LOAD = 10pF -- 10 -- MHz Slew Rate SR C LOAD = 10pF 10 -- -- V/ μs Output Voltage Range V COMP 0.5 -- 3.6 V Maximum Current I EA_SLEW Slew 300 -- -- μA Power Sequence PGOOD Low Voltage V PGOOD I PGOOD = 4mA -- -- 0.4 V Soft-Start Delay t D1 After POR, from EN = High to V OUT Rising 0 -- 5 ms VBOOT Duration t D3 0.05 -- 3 ms PGOOD Delay t D5 Measured from final VOUT value to PGOOD = High 0.05 -- 3 ms Current Sense Amplifier Maximum Current I GMMAX V CSP = 1.3V, sink current from CSN 100 -- -- μA Input Offset Voltage V OSCS −1.5 0 1.5 mV Soft Start Soft Start Current I SS1 Slew 12 16 20 μA VID Change Current I SS2 Slew 120 160 200 μA Gate Driver UGA TE Drive Source I UGATEsr BOOT – PHASE = 12V , UGATE – PHASE = 6V 0.6 1 -- A UGA TE Drive Sink R UGATEsk BOOT – PHASE = 8V, 250mA Source Current -- 1 -- Ω LGATE Drive Source I LGATEsr V CC12 = 12V, VLGATE = 6V 0.6 1 -- A LGATE Drive Sink R LGATEsk 250mA Sink Current -- 0.8 -- Ω Protection Over-Voltage Threshold V OVP Sweep FB Voltage, V FB − VEAP 125 150 175 mV OCP Input Offset Voltage V OCOFS −10 -- 10 mV

DS8113-02 April 2011 www.richtek.com Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in natural convection at T A = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Over Temperature Shutdown Setpoint TSD -- 160 -- °C Dynamic Characteristic UGATE Rise Time t rUGA TE - 15 - ns UGATE Fall Time t fUGATE - 10 - ns LGATE Rise Time t rLGA TE - 15 - ns LGATE Rise Time t fLGATE Ciss = 3000pF - 10 - ns

DS8113-02 April 2011www.richtek.com Typical Operating Characteristics VID = 0.9V, ILOAD = 1A Power Off from RT/EN Time (400 μs/Div) PGOOD (2V/Div) VOUT (1V/Div) RT/EN (2V/Div) UGATE (20V/Div) VID = 0.9V, ILOAD = 1A Start Up from RT/EN Time (1ms/Div) PGOOD (2V/Div) VOUT (1V/Div) RT/EN (2V/Div) UGATE (20V/Div) VID from 0.675V up to 1.3V, ILOAD = 16A Dynamic VID Up Time (40 μs/Div) VOUT (500mV/Div) VID1 (1V/Div) VID from 1.3V down to 0.675V, ILOAD = 16A Dynamic VID Down Time (40 μs/Div) VOUT (500mV/Div) VID1 (1V/Div) Load Transient Response Time (10 μs/Div) ILOAD VOUT (20mV/Div) VID = 1.3V, fLOAD = 1kHz, ILOAD = 7A to 20A ->1.2V 20A Load Transient Response Time (10 μs/Div) ILOAD VOUT (20mV/Div) VID = 1.3V, fLOAD = 1kHz, ILOAD = 20A to 7A ->1.2V 20A

DS8113-02 April 2011 www.richtek.com Over Current Protection Time (200 μs/Div) PGOOD (5V/Div) VOUT (1V/Div) UGATE (50V/Div) ILOAD (50A/Div) Over Voltage Protection Time (20 μs/Div) PGOOD (5V/Div) VFB (1V/Div) UGATE (20V/Div) LGATE (10V/Div)

DS8113-02 April 2011www.richtek.com Dynamic VID The RT8113 can accept VID input changing while the controller is running. This allows the output voltage (VOUT) to change while the DC/DC converter is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under either light or heavy load conditions. The CPU changes the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. Theoretically, V OUT should follow V DAC, which is a staircase waveform, but in real application, the bandwidth of the converter is finite while the staircase waveform needs infinite bandwidth to follow. Thus, undesired V OUT overshoot (when V DAC changes up) or undershoot (when V DAC changes down) is often observed in these type of designs. However, for the RT8113, as mentioned before in the Soft-Start section, V DAC slew rate is limited by I SS2/CSS when PGOOD = high. This slew rate limiter works as a low-pass filter of V DAC and makes the bandwidth of VDAC waveform finite. By smoothening VDAC staircase waveform, VOUT will no longer overshoot or undershoot. On the other hand, CSS will increase the settling time of V OUT during VID OTF. In most cases, a 1nF to 30nF ceramic capacitor will be suitable for C SS. FB OFSN OFSN FB OFS 0.8 x RV = I x R = R Connect a resistor from the OFS pin to VCC5 to activate IOFSP. IOFSP flows through R FB from the V CCP to the FB pin. In this case, a positive no-load offset voltage (VOFSP) is generated. FB OFSP OFSP FB OFS 6.4 x RV = I x R = R D1 OUT SS D2 OUT OUT BOOT BOOT SS t is the delay time from power on reset state to the beginning of V rising. 0.7V x Ct = 1600 μs + 16μA t is the soft-start time from V = 0 to V = V . V x Ct = 16μA t is the OUT BOOT D4 OUT BOOT OUT DAC DAC BOOT dwelling time for V = V . t 8 0 0 μs. t is the soft-start time from V = V to V = V . V - V x C s st 16μA t is the power good delay time. t1 6 0 0 μs. Output Voltage Differential Sensing The RT8113 uses a high-gain low-offset error amplifier for differential sensing. The CPU voltage is sensed between the FB and FBRTN pins. A resistor (R FB) connects the FB pin with the positive remote sense pin of the CPU (VCCP), while the FBRTN pin connects directly to the negative remote sense pin of the CPU (V CCN). The error amplifier compares VEAP (= VDAC − VADJ) with the VFB to regulate the output voltage. No-Load Offset In Figure 5, IOFSN and IOFSP are used to generate no-load offset. Either I OFSN or I OFSP is active during normal operation. Connect a resistor from OFS pin to GND to activate I OFSN. IOFSN flows through RFB from the FB pin to VCCP. In this case, a negative no-load offset voltage (VOFSN) is generated.

Figure 7. Circuit for Current Sensing 700nA is a typical value of the CSA input offset current.

compensates the temperature effect of the load line. be the same whether connecting RT/EN to VCC5 or GND. Figure 8. Over Current Protection MOSFET and turn off high side MOSFET to protect CPU. MOSFETs and low side MOSFETs. zero and mid-frequency to high-frequency gain boost.

frequency to cancel high frequency noise. ambient temperature on the maximum power dissipation. circuits as short as possible. driving current (at least 40mm). Figure 11. Derating Curves for RT8113 Package

DS8113-02 April 2011www.richtek.com \ The voltage feedback loop contains two traces, VCC and VSS, which are Kelvin sensed from CPU socket or output capacitors. These two traces should have 10mm width and be placed away from high (di/dt) switching elements such as high-side MOSFETs, low-side MOSFETs, phase plane etc. The circuit elements of voltage feedback loop, such as feedback loop short resistors and voltage loop compensation RCs, have to be kept near the RT8113 and also away from switching elements. \ The current-sense mechanism of the RT8113 is fully differential Kelvin sense. Therefore, the current-sense loop of the RT8113 contain two traces : the positive trace(ISP) comes from the positive node the of output inductor (the node connecting phase plane) and the negative trace (ISN) comes from the negative node of the output inductor (the node connecting output plane). DO NOT connect the current-sense traces from the phase plane or output plane. Only connect these traces from both sides of the output inductor to achieve the goal of precise Kelvin sense. The current-sense feedback loops have to be routed away from switching elements, and the current-sense RC elements have to be put near their respective ISN or ISP pins of the RT8113 and also away from noise switching elements. At lease 10 mm width is suggested for current sense feedback loops.

DS8113-02 April 2011 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Outline Dimension A D E L be SEE DETAIL A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2