RT8023GQW

RT8023GQW RICHTEK | Alldatasheet

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Technical content

Features

zzzzz Converter Input Voltage Range : 2.6V to 5.5V, LDO Input Voltage Range : 2.4V to 5.5V zzzzz Low-Noise LDO for RF Application zzzzz Ultra-Fast Response in Line/Load Transient zzzzz LDO Turn-On Time Less Than 40us zzzzz Only 1 μμμμμF LDO Output Capacitor Required for Stability zzzzz Current Limiting Protection zzzzz 1.5A, High Efficiency Step-Down Converter zzzzz 1.2MHZ Constant Switching Frequency zzzzz Low RDS(ON) Internal Switches zzzzz No Schottky Diode Required zzzzz 0.8V Reference Allows Low Output Voltage zzzzz Low Dropout Operation : 100% Duty Cycle Internally Compensated zzzzz < 2μμμμμA Shutdown Current zzzzz Power Good Output Voltage Monitor zzzzz Internal Soft-Start for PWM Converter zzzzz Easy Power Sequence Control zzzzz Over Temperature Protection zzzzz Short Circuit Protection zzzzz Thermally Enhanced 24-Lead WQFN Package zzzzz RoHS Compliant and 100% Lead (Pb)-Free Note : Richtek products are : \ RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Package Type QW : WQFN-24L 4x4 (W-Type) RT8023 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free)

Figure 1. 1.2V Output Step-Down Converter and Dual 2.5V Output Regulators Note : Must to use ceramic X5R/X7R capacitors.

DS8023-03 March 2011 www.richtek.com Functional Pin Description Pin No. Pin Name Pin Function 1 PGOOD1 Power Good Indicator of step-down converter. Open-drain lo gic output that is opened when the output voltage exceeds 90% of the regulation point.

2 VDD1

Signal Input Supply . Decouple this pin to GND with a capacitor. Normally VIN1 is equal to VDD1. Keep the volta ge difference between VDD1 and VIN1 less than 0.5V. 3, 4, 5 VIN1 Power Input Supply of step-down converter. Decouple this pin to GND with a capacitor. 25 (Exposed Pad) PGND Power Ground. Must be soldered to PCB ground for electrical contact and optimum thermal performance. The exposed pad must be soldered to a lar ge PCB and connected to PGND for maximum power dissipation. 8, 9 PHASE1 Internal Power MOSFET Switches Output of step-down converter. Connect this pin to the inductor. 11 VIN2 Power Input Supply of LDO1. Decouple this pin to GND with a 1Uf or greater capacitor. 12 VOUT2 Output of LDO1. A 1Uf or greater output low-ESR ceramic capacitor is required for stability .. 13 FB2 Feedback Pin of LDO1. Receives the feedback volta ge from a resistive divider connected across the output. 14 PGOOD2 Power Good Indicator of LDO1. Open-drain lo gic output that is opened when the output voltage exceeds 90% of the regulation point. 15 EN2 LDO1 Enable. A logical high level at this pin enables LDO1, while a lo gical low level causes LDO1 to shut down. 16 EN3 LDO2 Enable. A logic high level at this pin enables LDO2, while a lo gic low level causes LDO2 to shut down. 17 PGOOD3 Power Good Indicator of LDO2. Open-drain lo gic output that is opened when the output voltage exceed 90% of regulation point. 18 FB3 Feedback Pin of LDO2. Receives the feedback volta ge from a resistive divider connected across the output. 19 AGND Analog Grand. All small-signal of the IC should connect to this ground, which connects to PGND at one point for away exposed pad. 20 VOUT3 Output of LDO2. A 1uF or greater output low-ESR ceramic capacitor is required for stability . 21 VIN3 Power Input Supply of LDO2. Decouple this pin to GND with a 1uF or greater capacitor. 7, 10, 22 NC No Internal Connection. 23 FB1 Feedback Pin of step-down converter. Receives the feedback volta ge from a resistive divider connected across the output. 24 EN1 Step-down converter Enable. A logic high level at this pin enables step-down converter, while a logic low level causes step-down converter to shut down.

DS8023-03 March 2011www.richtek.com Function Block Diagram Driver Control Logic 0.72V 0.4V OC Limit ISEN Slope Compensation OSC Output ClampEA0.8V Internal- Soft Start POR FB1 VIN1 VDD1 PGOOD1 GND PHASE1 OTP VREF2 VREF3 VIN2 Current Limit FB3 EA VOUT3 0.8V 0.72V VIN3 Current Limit FB2 EA VOUT2 0.8V 0.72V PGOOD3 OT POR PGOOD2 EN1 EN2 EN3

DS8023-03 March 2011 www.richtek.com Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

Electrical Characteristics

(TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Step-down converter Input Voltage Range V IN1 2.6 -- 5.5 V Feedback Voltage V FB1 0.784 -- 0.816 V VDD1 Rising 2.24 2.36 2.48 V Under Voltage Lockout Threshold V UVLO VDD1 Hysteresis -- 150 -- mV DC Bias Current Active, VFB = 0.75V, Not Switching -- 300 -- μA Shutdown Current I SHDN EN2 = 0 -- -- 2 μA Switch On Resistance, High R FET_H I PHASE = 0.5A -- 150 270 m Ω Switch On Resistance, Low R FET_L I PHASE = 0.5A -- 90 150 m Ω Peak Current Limit I LIM 1.7 2.3 3.2 A Switching Frequency 1 1.2 1.4 MHz Output Voltage Line Regulation V IN1 = 2.6V to 5.5V -- 0.01 1 %/V To be continued Recommended Operating Conditions (Note 4)

DS8023-03 March 2011www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Load Regulation Measured by sever loop, EA output from 0.253V to 0.853V -- 0.01 1 % FB Threshold for PGOOD Transition 0.68 0.72 0.76 V PGOOD1 Pull-Down Resistance -- -- 100 Ω EN1 Input High 1.4 -- -- V EN1 Input Low -- -- 0.4 V Thermal Shutdown Temperature T SD (Note 5) -- 145 -- Thermal Shutdown Hysteresis ΔTSD -- 25 -- LDO1 (VIN = VOUT + 0.5V, VEN = VIIN, CIN = COUT = 1uF (Ceramic)) Input Voltage Range V IN2 2.4 -- 5.5 V Feed Back Voltage V FB2 0.784 -- 0.816 V Output Noise Voltage e NO V OUT2 = 1.5V, IOUT2 = 1mA -- 30 -- μVRMS Quiescent Current I Q V EN2 = 5V, IOUT2 = 0mA -- 35 60 μA Shutdown Current I SHDN EN2 = 0 -- -- 2 μA EN2 Pin Current I EN2 Measured EN leakage current. EN2 = 5.5V -- 0.1 1 μA Current Limit I LIM R LOAD = 0Ω 0.7 0.9 1.2 A Dropout Voltage V DROP I OUT2 = 500mA, VIN2 > 2.7V -- 250 400 mV Load Regulation ΔVLOAD 1mA < IOUT2 < 500mA, Line Regulation ΔVLINE VIN2 = (VOUT2 + 0.5) to 5.5V IOUT2 = 1mA -- 0.01 0.2 %/V Power Supply Rejection Ratio, f = 100kHz PSRR I OUT2 = 300mA -- 40 -- dB FB Threshold for PGOOD Transition -- 0.72 0.76 V PGOOD2 Pull-Down Resistance -- -- 120 Ω EN2 Input High 1.4 -- -- V EN2 Input Low -- -- 0.4 V LDO2 (VIN = VOUT + 0.5V, VEN = VIN, CIN = COUT = 1uF (Ceramic)) Input Voltage Range V IN3 2.4 -- 5.5 V Feed Back Voltage V FB3 0.784 -- 0.816 V Output Noise Voltage e NO V OUT3 = 1.5V, IOUT3 = 1mA -- 30 -- μVRMS Quiescent Current I Q V EN3 = 5V, IOUT3 = 0mA -- 35 60 μA Shutdown Current I SHDN EN1 = 0 -- -- 2 μA EN3 Pin Current I EN3 Measured EN leakage current. EN3 = 5.5V -- 0.1 1 μA To be continued

DS8023-03 March 2011 www.richtek.com Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The power source for thermal shutdown circuit must be provided by V IN1. There must be a power input into LDO1 and then the LDO2 can provide the thermal shutdown function. Parameter Symbol Test Conditions Min Typ Max Unit Current Limit I LIM R LOAD = 0Ω 0.35 0.48 0.6 A Dropout Voltage V DROP I OUT3 = 250mA, VIN3 > 2.7V -- 250 400 mV Load Regulation ΔVLOAD 1mA < IOUT3 < 250mA, Line Regulation ΔVLINE VIN3 = (VOUT3 + 0.5) to 5.5V IOUT3 = 1mA -- 0.01 0.2 %/V EN3 Pin Current I EN3 Measured EN leakage current. EN3 = 5.5V -- 0.1 1 μA Current Limit I LIM R LOAD = 0Ω 0.35 0.48 0.6 A Dropout Voltage V DROP I OUT3 = 250mA, VIN3 > 2.7V -- 250 400 mV Load Regulation ΔVLOAD 1mA < IOUT3 < 250mA, Line Regulation ΔVLINE VIN3 = (VOUT3 + 0.5) to 5.5V IOUT3 = 1mA -- 0.01 0.2 %/V Power Supply Rejection Ratio, f = 100kHz PSRR I OUT3 = 150mA -- 40 -- dB FB3 Threshold for PGOOD Transition -- 0.72 0.76 V PGOOD3 Pull-Down Resistance -- -- 120 Ω EN3 Input High 1.4 -- -- V EN3 Input Low -- -- 0.4 V

DS8023-03 March 2011www.richtek.com Typical Operating Characteristics Buck Output Voltage vs. Load Current 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 Load Current (A) Output Voltage (V) VOUT1 = 1.2V VIN1 = 3.3V VIN1 = 5.5V Buck Efficiency vs. Output Current 100 Output Current (A) Efficiency (%) VOUT1 = 1.2V VIN1 = 3.3V VIN1 = 5V Buck Output Voltage vs. Temperature 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 -50 -25 0 25 50 75 100 125 Temperature Output Voltage (V) (°C) VOUT1 = 1.2V VIN1 = 3.3V VIN1 = 5.5V (°C) Buck Current Limit vs. Temperature 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 -50 -25 0 25 50 75 100 125 Temperature Current Limit (A) VOUT1 = 1.2V VIN1 = 3.3V VIN1 = 5.5V Buck Frequency vs. Input Voltage 1.00 1.05 1.10 1.15 1.20 1.25 1.30 -50 -25 0 25 50 75 100 125 Input Voltage (V) Frequency (MHz ) VOUT1 = 1.2V, IOUT1 = 0.1A VIN1 = 3.3V VIN1 = 5.5V Buck Frequency vs. Input Voltage 1.00 1.05 1.10 1.15 1.20 1.25 1.30 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Frequency (MHz) VOUT1 = 1.2V, IOUT1 = 0.1A

DS8023-03 March 2011 www.richtek.com VIN1 = 5V, VOUT1 = 1.2V IOUT1 = 0A to 1.5A Buck Load Transient Response Time (50 μs/Div) IOUT1 (1A/Div) VOUT1 (50mV/Div) VIN1 = 3.3V, VOUT1 = 1.2V, IOUT1 = 1.5A Buck PGOOD Response Time (100 μs/Div) IOUT1 (0.5A/Div) VOUT1 (500mV/Div) VEN1 (2V/Div) VPGOOD1 (2V/Div) LDO1 Dropout Voltage vs. Load Current 100 200 300 400 500 600 0 100 200 300 400 500 600 700 Load Current (mA) Dropout Voltage (mV) TA = -40°C TA = 25°C TA = 125°C VOUT2 = 2.5V LDO2 Dropout Voltage vs. Load Current 100 200 300 400 500 600 0 50 100 150 200 250 300 350 Load Current (mA) Dropout Voltage (mV) TA = -40°C TA = 25°C TA = 125°C VOUT3 = 2.5V VIN1 = 3.3V, VOUT1 = 1.2V, IOUT1 = 1.5A Buck Power On from EN Time (100 μs/Div) IIN1 (0.5A/Div) VOUT1 (500mV/Div) VEN1 (2V/Div) VIN1 = 3.3V, VOUT1 = 1.2V IOUT1 = 1.5A Buck Switching Waveforms Time (1 μs/Div) IPHASE1 (500mA/Div) VOUT1 (5mV/Div) VPHASE1 (5V/Div) IPHASE1

DS8023-03 March 2011www.richtek.com LDO1 Current Limit vs. Input Voltage 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 2 . 533 . 544 . 555 . 5 Input Voltage (V) Current Limit (A) VOUT2 = 2.5V LDO2 Current Limit vs. Input Voltage 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 2 . 533 . 544 . 555 . 5 Input Voltage (V) Current Limit (A) VOUT3 = 2.5V LDO1 Current Limit vs. Temperature 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 Temperature Current Limit (A) VOUT2 = 2.5V VIN2 = 3.3V VIN2 = 5.5V (°C) LDO2 Current Limit vs. Temperature 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 -50 -25 0 25 50 75 100 125 Temperature Current Limit (A) VOUT3 = 2.5V VIN3 = 3.3V VIN3 = 5.5V (°C) LDO1 Output Voltage vs. Load Current 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 0 100 200 300 400 500 600 700 Load Current (mA) Output Voltage (V) VOUT2 = 2.5V VIN2 = 3.3V VIN2 = 5.5V LDO2 Output Voltage vs. Load Current 2.490 2.495 2.500 2.505 2.510 2.515 2.520 2.525 2.530 0 50 100 150 200 250 300 350 Load Current (mA) Output Voltage (V) VOUT3 = 2.5V VIN3 = 3.3V VIN3 = 5.5V

DS8023-03 March 2011 www.richtek.com VIN3 = 2.5V to 3.5V, VOUT3 = 1.2V, IOUT3 = 100mA LDO2 Line Transient Response Time (50 μs/Div) VOUT3 (50mV/Div) VIN3 (1V/Div) VIN2 = 2.5V to 3.5V, VOUT2 = 1.2V, IOUT2 = 100mA LDO1 Line Transient Response Time (50 μs/Div) VOUT2 (50mV/Div) VIN2 (1V/Div) VIN3 = 5V, VOUT3 = 1.2V IOUT3 = 0A to 0.35A LDO2 Load Transient Response Time (50 μs/Div) IOUT3 (0.2A/Div) VOUT3 (20mV/Div) VIN2 = 5V, VOUT2 = 1.2V IOUT2 = 0A to 0.7A LDO1 Load Transient Response Time (50 μs/Div) IOUT2 (0.5A/Div) VOUT2 (20mV/Div) LDO2 Output Voltage vs. Temperature 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -50 -25 0 25 50 75 100 125 Temperature Output Voltage (V) VIN3 = 3.3V, VOUT3 = 2.5V (°C)(°C) LDO1 Output Voltage vs. Temperature 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -50 -25 0 25 50 75 100 125 Temperature Output Voltage (V) VIN2 = 3.3V, VOUT2 = 2.5V

DS8023-03 March 2011www.richtek.com VIN2 = 4.5V, VOUT2 = 1.5V, IOUT2 = 300mA LDO1 Noise Time (10ms/Div) VOUT2 (50uV/Div) VIN3 = 4.5V, VOUT3 = 1.5V, IOUT3 = 300mA LDO2 Noise Time (10ms/Div) VOUT3 (50uV/Div) LDO1 PSRR -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 100000 1000000 Frequency (Hz) PSRR (dB) VIN2 = 2.5V to 2.6V, V OUT2 = 1.5V IOUT = 10mA IOUT = 300mA 0.01 0.1 1 10 100 1000 (kHz) Crosstalk -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 100000 1000000 Frequency (Hz) Crosstalk (dB) VIN2 to VOUT3, IOUT3 = 10mA 0.01 0.1 1 10 100 1000 (kHz) LDO1 VIN2 = 2.5V to 2.6V LDO2 VOUT3 = 1.5V VIN3 = 5V, VOUT3 = 1.2V, IOUT3 = 0.3A LDO2 Power On from EN3 Time (10 μs/Div) IIN3 (0.5A/Div) VOUT3 (500mV/Div) VEN3 (5V/Div) VIN2 = 5V, VOUT2 = 1.2V, IOUT2 = 0.3A LDO1 Power On from EN2 Time (10 μs/Div) IIN2 (0.5A/Div) VOUT2 (500mV/Div) VEN2 (5V/Div)

DS8023-03 March 2011 www.richtek.com VIN3 = 5V, VOUT3 = 1.2V, IOUT3 = 0.3A LDO2 PGOOD Response Time (25 μs/Div) IOUT3 (0.5A/Div) VOUT3 (500mV/Div) VEN3 (5V/Div) VPGOOD (2V/Div) VIN2 = 5V, VOUT2 = 1.2V, IOUT2 = 0.3A LDO1 PGOOD Response Time (25 μs/Div) IOUT2 (0.5A/Div) VOUT2 (500mV/Div) VEN2 (5V/Div) VPGOOD (2V/Div)

DS8023-03 March 2011www.richtek.com

Application Information

The Typical Application Circuit shows the basic RT8023 application circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by C IN and COUT. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔI L increases with higher VIN and decreases with higher inductance. OUT OUTL IN VVI = 1 fL V Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value o f ΔIL = 0.4(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest V IN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : OUT OUT L(MAX) IN(MAX) VVL = 1fI V Inductor Core Selection The inductor type must be selected once the value for L is known. Generally speaking, high efficiency converters can not afford the core loss found in low cost powdered iron cores. So, the more expensive ferrite or mollypermalloy cores will be a better choice. The selected inductance rather than the core size for a fixed inductor value is the key for actual core loss. As the inductance increases, core losses decrease. Unfortunately, increase of the inductance requires more turns of wire and therefore the copper losses will increase. Ferrite designs are preferred at high switching frequency due to the characteristics of very low core losses. So, design goals can focus on the reduction of copper loss and the saturation prevention. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. The previous situation results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate energy. However, they are usually more expensive than the similar powdered iron inductors. The rule for inductor choice mainly depends on the price vs. size requirement and any radiated field/ EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : OUT INRMS OUT(MAX) IN OUT V VI = I 1 VV − This formula has a maximum at V IN = 2V OUT, where IRMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of C OUT is determined by the required effective series resistance (ESR) to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔV OUT , is determined by : OUT L OUT 1VI E S R 8fC

inductance can also lead to significant ringing. of the output voltage as shown in Figure2. Figure 2. Setting the Output Voltage Where VREF is the internal reference voltage (0.8V typ.). power lost is of no consequence. significant at higher supply voltages.

DS8023-03 March 2011www.richtek.com 2. I2R losses are calculated from the resistance of the internal switches R SW and external inductor R L. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFETs R DS(ON) and the duty cycle (DC) as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristic curves. Thus, to obtain I 2R loss, simply add R SW to RL and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of total losses. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔILOAD (ESR) also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For LDO Part The external capacitors used with the RT8023 must be carefully selected for regulator stability and performance just like any low-dropout regulator. Using a capacitor whose value is >1 μF on the RT8023 input and the amount of capacitance can be increased without limit. The input capacitor must be located at a distance of not more than 1cm from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDO applications. The RT8023 is designed specifically to work with low ESR ceramic output capacitor for space-saving and performance consideration. Enable The RT8023 goes into sleep mode when the EN pin is in the logic low condition. The RT8023 has an EN pin to turn on or turn off the regulator during this condition. When the EN pin is in the logic high condition, the regulator will be turned on. The typical supply current for the EN pin is 0.1μA. The EN pin may be directly tied to V IN to keep the part on. The enable input is CMOS logic and can not be left floating. Current Limit The RT8023 contains an independent current limiter to monitor and control the pass transistor's gate voltage. The part limits the two LDOs' current respectively as follows : LDO1 : 700mA and LDO2 : 350mA (min.). The output can be shorted to ground indefinitely without damaging the part. PGOOD The power good output is an open-drain output. It is designed essentially to work as a power-on reset generator once the regulated voltage was up or a fault condition occurs. The output of the power good drives to low when a fault condition occurs. The power good output will be driven back to up once the output reaches 90% of its nominal value. The output voltage level will be drooped at the fault condition including current limit, thermal shutdown or shutdown and triggers the PGOOD detector to alarm a fault condition. Due to the shutdown mode condition, a fault condition occurs by pulling up the PGOOD output low. And it will sink a current from the open drain and the external power. It is recommended to select a suitable pulling resistance to achieve the goal of ideal power dissipation control. PSRR The power supply rejection ratio (PSRR) is defined as the ability of a regulator to maintain its output voltage as its power supply voltage is varied. The PSRR is found to be: PSRR = 20 x log[ ΔV OUT/ΔVIN]

DS8023-03 March 2011 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com A D E L be SEE DETAIL A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2 Outline Dimension