RT8015BGQW

RT8015B RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz High Efficiency : Up to 95% zzzzz Low RDS(ON) Internal Switches : 110mΩΩΩΩΩ zzzzz Programmable Frequency : 300kHz to 2MHz zzzzz No Schottky Diode Required zzzzz 0.8V Reference Allows for Low Output Voltage zzzzz Forced Continuous Mode Operation zzzzz Low Dropout Operation : 100% Duty Cycle zzzzz Power Good Output Voltage Indicator zzzzz RoHS Compliant and Halogen Free

Applications

z Battery-Powered Equipment z Notebook Computers z Distributed Power Systems z IP Phones z Digital Cameras General Description The RT8015B is a high efficiency synchronous, step down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal synchronous low on resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is set by an external resistor. The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The RT8015B is operated in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. The 100% duty cycle in Low Dropout Operation further maximize battery life. The RT8015B is available in the WDFN-10L 3x3 and SOP- 8 (Exposed Pad) packages.

Ordering Information

(TOP VIEW) WDFN-10L 3x3 3A, 2MHz, Synchronous Step-Down Converter Note : Richtek products are : \ RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes. SHDN/RT GND PGND LX COMP FB PGOOD PVDD VDD LX SHDN/RT GND LX PGND COMP FB PVDD VDD 4 5 GND SOP-8 (Exposed Pad) Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. RT8015B Package Type QW : WDFN-10L 3x3 SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free)

6 5 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor. 7 6 VDD Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD. resistive divider connected across the output. compensation elements to this pin to stabilize the control loop. large PCB and connected to GND for maximum power dissipation. GND for maximum power dissipation. Table 1. Recommended Component Selection

7 VDD

8 PGOOD

DS8015B-04 March 2011 www.richtek.com Function Block Diagram Layout Guide Driver NISEN Control Logic NMOS I Limit 0.9V 0.7V 0.2V OC Limit ISEN Slope ComOSC Output ClampEA0.8V Int-SS POR OTPVREF COMP SHDN/RT GND FB PVDD VDD PGND SD LX PGOOD VIN GND VOUT GND CIN COUT VOUT CCOMP R2R1CF ROSC Place the input and output capacitors as close to the IC as possible. LX should be connected to Inductor by wide and short trace, keep sensitive components away from this trace Place the feedback and compensation components as close to the IC as possible. RT8015B SHDN/RT GND PGND LX COMP FB PGOOD VDD PVDD LX RCOMP GND Bottom Layer

DS8015B-04 March 2011www.richtek.com Operation Main Control Loop The RT8015B is a monolithic, constant-frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-Channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the voltage on the COMP pin. The error amplifier adjusts the voltage on the COMP pin by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the COMP voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The operating frequency is set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 2MHz. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-Channel MOSFET and the inductor. Low Supply Operation The RT8015B is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the R DS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8015B is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8015B, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.

DS8015B-04 March 2011 www.richtek.com Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

Electrical Characteristics

(VDD = 3.3V, T A = 25°C, unless otherwise specified) To be continued Recommended Operating Conditions (Note 4) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range V DD 2.6 -- 5.5 V Feedback Reference Voltage V REF 0.784 0.8 0.816 V Feedback Leakage Current I FB -- 0.1 0.4 μA Active , V FB = 0.78V, Not Switching -- 460 -- μA DC Bias Current Shutdown -- -- 1 μA Output Voltage Line Regulation V IN = 2.7V to 5.5V -- 0.03 -- %/V Output Voltage Load Regulation Measured in Servo Loop, Error Amplifier Transconductance gm -- 800 -- μs Current Sense Transresistance R T -- 0.4 -- Ω Switching Leakage Current SHDN/RT = VIN = 5.5V -- -- 1 μA

DS8015B-04 March 2011www.richtek.com Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in natural convection at T A = 25 °C on a high-effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the packages. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization and correlation with statistical process controls. Parameter Symbol Test Conditions Min Typ Max Unit ROSC = 332k 0.8 1 1.2 MHz Switching Frequency Switching Frequency 0.3 -- 2 MHz Switch On Resistance, High R PMOS I SW = 0.5A -- 110 160 m Ω Switch On Resistance, Low RNMOS I SW = 0.5A -- 110 170 m Ω Power Good Range -- ±12.5 ±15 % Power Good Pull-Down Resistance -- -- 120 Ω Peak Current Limit I LIM 3.2 3.8 -- A V DD Rising -- 2.4 -- V Under Voltage Lockout Threshold V DD Falling -- 2.3 -- V Shutdown Threshold -- V IN − 0.7 V IN − 0.4 V

DS8015B-04 March 2011 www.richtek.com Typical Operating Characteristics Quiescent Current vs. Input Voltage 360 370 380 390 400 410 420 430 440 450 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Quiescent Current (uA) Output Voltage vs. Load Current 2.456 2.460 2.464 2.468 2.472 2.476 2.480 2.484 2.488 2.492 Load Current (A) Output Voltage (V) VIN = 5V Peak Current Limit vs. Input Voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Input Voltage (V) Current Limit (A) VOUT = 2.5V Frequency vs. Temperature 0.98 1.00 1.02 1.04 1.06 1.08 -50 -25 0 25 50 75 100 125 Temperature Frequency (MHz) VIN = 5V, VOUT = 2.5V, IOUT = 0A (°C) Quiescent Current vs. Temperature 380 390 400 410 420 430 440 450 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature Quiescent Current (uA) VIN = 5V (°C) Efficiency vs. Load Current 100 0.01 0.1 1 10 Load Current (A) Efficiency (%) VIN = 5V VIN = 5.5V VOUT = 2.5V VIN = 4.5V

DS8015B-04 March 2011www.richtek.com Output Voltage vs. Temperature 3.22 3.24 3.26 3.28 3.30 3.32 3.34 -50 -25 0 25 50 75 100 125 Temperature Output Voltage (V) VIN = 5V (°C) UVP Time (4 μs/Div) ILX (5A/Div) VLX (5V/Div) VIN = 5V, VOUT = 1.05V VOUT (1V/Div) PGOOD (5V/Div) Load Transient Response Time (100 μs/Div) ILOAD (1A/Div) VOUT_ac (100mV/Div) VIN = 5V, VOUT = 2.5V IOUT = 0A to 3A Output Ripple Time (400ns/Div) ILX (2A/Div) VLX (5V/Div) VIN = 5V, VOUT = 2.5V IOUT = 3A VOUT_ac (10mV/Div) Start up with No Load Time (400 μs/Div) VLX (5V/Div) VIN = 5V, VOUT = 10.5V, IOUT = 0A VOUT (1V/Div) VIN (5V/Div) PGOOD (5V/Div) Start up with Heavy Load Time (400 μs/Div) VIN = 5V, VOUT = 1.05V, IOUT = 3A VLX (5V/Div) VOUT (1V/Div) VIN (5V/Div) PGOOD (5V/Div)

DS8015B-04 March 2011www.richtek.com The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost sensitive V V VII OUT IN IN OUTOUT(MAX)RMS −= ⎡ +Δ≤Δ OUT LOUT 8fC 1ESRIV Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This result in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are ⎡ −⎥⎦ Δ×= IN(MAX) OUT L(MAX) OUT V V1If VL Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔI = 0.4(I MAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔI L increases with higher VIN and decreases with higher inductance. ⎡ −⎥⎦ ×=Δ IN OUTOUTL V V1Lf VI small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs. size requirements and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : This formula has a maximum at V IN = 2V OUT, where IRMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of C OUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔV OUT, is determined by :

DS8015B-04 March 2011 www.richtek.com applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, V IN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of C OUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem. The COMP pin external components and output capacitor shown in Typical Application Circuit will provide adequate compensation for most applications. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: V DD quiescent current and I2R losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I 2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The V DD quiescent current is due to two components : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from V DD to ground. The resulting ΔQ/Δt is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to V DD and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (D) as follows : RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I 2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss.

\` Flood all unused areas on all layers with copper. other DC rail in your system). off high side MOSFET and turn on low side MOSFET. blanked until soft-start finish. Figure 4. Derating Curves for RT8015B Package

Table 1. Inductors Table 2. Capacitors for CIN and COUT

DS8015B-04 March 2011 www.richtek.com Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.1 16 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.1 16 0.120 E2 1.500 1.750 0.059 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A

DS8015B-04 March 2011www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com A BJ F H M C D I Y X EXPOSED THERMAL PAD (Bottom of Package) 8-Lead SOP (Exposed Pad) Plastic Package Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Option 1 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Option 2 Y 3.000 3.500 0.118 0.138