RT8004

RT8004 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz High Efficiency : Up to 95% zzzzz Low Quiescent Current : 100μμμμμA zzzzz Low RDS(ON) Internal Switches : 75mΩΩΩΩΩ zzzzz Programmable Frequency : 300kHz to 4MHz zzzzz No Schottky Diode Required zzzzz 0.8V Reference Allows Low Output Voltage zzzzz Low Dropout Operation : 100% Duty Cycle zzzzz Synchronizable Switching Frequency zzzzz Power Good Output Voltage Monitor zzzzz Over Temperature Protection zzzzz Thermally Enhanced SOP-16, TSSOP-16 (Exposed Pad) and 16-Lead VQFN 4x4 Packages zzzzz RoHS Compliant and 100% Lead (Pb)-Free Pin Configurations

Applications

z Battery-Powered Equipment z Notebook Computers z Distributed Power Systems z IP Phones z Digital Cameras 3A, 4MHz, Synchronous Step-Down Regulator

Ordering Information

The RT8004 is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.65V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal power switch with 75m Ω on-resistance increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. External compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The RT8004 operates in Forced Continuous Mode which reduces noise and RF interference. 100% duty cycle in Low Dropout Operation further maximize battery life. (TOP VIEW) Note : z Richtek Pb-free and Green products are : \RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \Suitable for use in SnPb or Pb-free soldering processes. \`100% matte tin (Sn) plating. VQFN-16L 4x4 RT8004 Package Type S : SOP-16 CP : TSSOP-16 (Exposed Pad) QV : VQFN-16L 4x4 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commer- cial Standard) Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area, otherwise visit our website for detail. COMP LX SYNC RT FB LX PGND PGND LX EN/SS GND PVDD LX PGOOD VDD PVDD 13141516 8765 GND

DS8004-03 September 2007www.richtek.com Typical Application Circuit TSSOP-16 (Exposed Pad) (TOP VIEW) SOP-16 VDD PGOOD COMP FB RT SYNC EN/SS GND PVDD LX LX PGND PGND LX LX PVDD VDD LX GND RT8004 PGOOD PVDD COMP RPG 100k RTH 10k CTH 1000pF 240k ROCS 309k RSS 4.7M CSS 470pF PGND COUT 47uF VOUT 2.5V/3A FB RT SYNC EN/SS PVDD CIN1 10uF CIN2 10uF VIN 2.65V to 5.5V PGOOD 22pFR1 510k 1uH 47uF External Clock VDD PGOOD COMP FB RT SYNC EN/SS GND PVDD LX LX PGND PGND LX LX PVDD GND

DS8004-03 September 2007 www.richtek.com Functional Pin Description Pin No. Pin Name Pin Function RT8004PS RT8004PCP RT8004PQP 1 1 15 VDD Signal Input Supply. Decouple this pin to GND with a capacitor. Normally VDD is equal to PVDD. 2 2 16 PGOOD Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within ±12.5% of regulation point. 3 3 1 COMP Error Amplifier Compensation Pin. The current comparator threshold increases with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. 4 4 2 FB Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. 5 5 3 RT Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. 6 6 4 SYNC External Clock Synchronization Input. The internal oscillator can be synchronized to an external clock applied to this pin. If not use, please connect this pin to VDD or GND. 7 7 5 EN/SS Enable Control and Soft-Start Input. Forcing this pin below 0.5V shuts down the RT8004. In shutdown all functions are disabled drawing < 1uA of supply current. A capacitor to ground from this pin sets the ramp time to full output current. 8 8, Exposed Pad (17) 6, Exposed Pad (17) GND Signal Ground. All small-signal components, compensation components and the exposed pad on the bottom side of the IC should connect to this ground, which in turn connects to PGND at one point. 9, 16 9, 16 7, 14 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor. 10,11, 14, 15 10,11, 14, 15 8, 9, 12, 13 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor. 12, 13 12, 13 10, 11 PGND Power Ground. Connect this pin close to the terminal of C IN and COUT.

DS8004-03 September 2007www.richtek.com Operation Main Control Loop The RT8004 is a monolithic, constant-frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-Channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the voltage on the COMP pin. The error amplifier adjusts the voltage on the COMP pin by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the COMP voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-Channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at −2A. The operating frequency is set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 4MHz. Power Good comparators will pull the PGOOD output low if the output voltage comes out of regulation by 12.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET’ s current limit is reached. Frequency Synchronization The internal oscillator of the RT8004 can be synchronized to an external clock connected to the SYNC pin. The frequency of the external clock can be in the range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is about 20% lower than the synchronization frequency. Function Block Diagram Oscillator VREF Control Logic Output Clamp Ext_SS Driver NISEN BG Slope Com ISEN Int_SS OTP POR NMOS I Limit 0.9V 0.7V 0.4V SD OC Limit ExtSyn EA POR 0.8V PVDD LX PGND PGOOD0.8V VDD EN/SS FB COMP SYNC RT GND

DS8004-03 September 2007 www.richtek.com Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on- time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-Channel MOSFET and the inductor. Low Supply Operation The RT8004 is designed to operate down to an input supply voltage of 2.65V. One important c onsideration at low input supply voltages is that the RDS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8004 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8004, however, separated inductor current signals are used to monitor over current condition and minimum peak current. This keeps the maximum output current and minimum peak current relatively constant regardless of duty cycle. Short-Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.

DS8004-03 September 2007www.richtek.com

Electrical Characteristics

(VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units Input Voltage Range V DD 2.65 -- 5.5 V Feedback Voltage V FB (Note 5) 0.784 0.8 0.816 V Feedback Leakage Current I FB -- -- 0.4 μA Active, VFB = 0.78V, Not switching 180 400 520 μA Input DC Bias Current Shutdown, VEN < 0.1V (Note 5) -- -- 1 μA Reference Voltage Line Regulation V IN = 2.7V to 5.5V (Note 5) -- 0.04 0.2 %/V Output Voltage Load Regulation Measured in Servo Loop, VCOMP = 1.2V to 1.6V (Note 5) -- 0.05 +/-0.2 % Power Good Power Good Range -- +/-12.5 +/-15 % Power Good Pull-Down Resistance -- -- 120 Ω Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 4) z ESD Susceptibility (Note 2) Recommended Operating Conditions (Note 3) To be continued

DS8004-03 September 2007 www.richtek.com Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25 °C on 4-layers high effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the QFN package. Note 5. The specifications over the -40°C to 85°C operation ambient temperature range are assured by design, characterization and correlation with statistical process controls. Note 6. The external synchronous frequency must be equal to 1 to 1.3 times of the internal setting frequency. The switching frequency reange is guaranteed by design but not production tested. Parameter Symbol Test Conditions Min Typ Max Units ROSC = 309k 0.8 1 1.2 MHz Switching Frequency f OSC Switching Frequency Range 0.3 -- 4 MHz Sync Frequency Range (Note 6) 0.3 -- 4 MHz Switch On Resistance, High R PFET ISW = 1A 45 75 110 mΩ Switch On Resistance, Low R NFET ISW = 1A 45 69 100 mΩ Peak Current Limit I LIM 4 5.2 7 A VDD Rising 2.25 2.52 2.7 V Undervoltage Lockout Threshold Hysteresis -- 0.15 -- V SW Leakage Current VEN = 0V, VIN = 5.5V -- -- 1 μA EN/SS Leakage Current -- -- 1 μA Enable Threshold VEN 0.65 -- 0.95 V

DS8004-03 September 2007www.richtek.com Typical Operating Characteristics Soft-Star Power On VOUT (1V/Div) Time (2.5ms/Div) IL (1A/Div) RLOAD = 0.83Ω VIN = 3.3V, VOUT = 2.5V VSS (1V/Div) Ripple Voltage VOUT (10mV/Div) Time (500ns/Div) IL (2A/Div) VIN = 3.3V, VOUT = 2.5V, IOUT = 3A VLX (2V/Div) Load Transien Response VOUT (50mV/Div) Time (25 μs/Div) IL (1A/Div) ILOAD = No Load to 3A VIN = 3.3V, VOUT = 2.5V Power Off VOUT (2V/Div) Time (25ms/Div) IL (2A/Div) VIN = 3.3V, VOUT = 2.5V, IOUT = 0A VLX (5V/Div) VIN (2V/Div) Efficiency vs. Output Current 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 500 1000 1500 2000 2500 3000 Output Current (mA) Efficiency (%) 100 VOUT = 2.5V, 1M Continuous Mode Operation VIN = 3.3V VIN = 5V Load Regulation -0.20% -0.10% 0.00% 0.10% 0.20% 0.30% 50 550 1050 1550 2050 2550 3050 Output Current (mA) VOUT Devation (%) VIN = 3.3V, VOUT = 2.5V 0.30 0.20 0.10 -0.10 -0.20

DS8004-03 September 2007 www.richtek.com Frequency vs. RRT 500 1000 1500 2000 2500 3000 3500 4000 4500 0 200 400 600 800 1000 1200 1400 RRT (kٛ) Frequency (kHz) VIN = 3.3V (kΩ) VREF Deviation vs. Temperature -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% 1.50% -50 -25 0 25 50 75 100 125 Temperature VREF Deviation (%) VIN = 3.3V (°C) Frequency vs. Temperature -50 -25 0 25 50 75 100 125 Temperature Frequency Deviation (%) VIN = 3.3V (°C) Frequency vs. Input Voltage 0.992 1.008 1.016 1.024 1.032 1.04 3 3.5 4 4.5 5 5.5 Input Voltage (V) Frequency (MHz) R = 309k Peak Current Limited vs. Input Voltage 4.5 4.7 4.9 5.1 5.3 5.5 33 . 544 . 555 . 5 Input Voltage (V) Peak Current Limited (A) VOUT = 2.5V Quiescent Current vs. Input Voltage 100 150 200 250 300 350 400 450 500 3 3.5 4 4.5 5 5.5 Input Voltage (V) Quiescent Current (uA)

DS8004-03 September 2007www.richtek.com V V VII OUT IN IN OUT OUT(MAX)RMS −=

Application Information

The basic RT8004 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by C IN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge and switching losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the RT8004 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RRT curve. Although frequencies as high as 4MHz are possible, the minimum on-time of the RT8004 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f(Hz). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔIL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “ hard” , which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don ’ t radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : ⎡ −⎥⎦ IN OUTOUT L V V1Lf VΔI −⎥⎦ Δ×= IN(MAX) OUT L(MAX) OUT V V1If VL

of the output voltage as shown in Figure 1. the load transient response as described in a later section. high voltage coefficient and audible piezoelectric effects. can also lead to significant ringing. Figure 1. Setting the Output Voltage

DS8004-03 September 2007www.richtek.com The RT8004 contains an internal soft-start clamp that gradually raises the clamp on COMP after the EN/SS pin is pulled above 0.8V. The full current range becomes available on COMP after 1024 switching cycles. If a longer soft-start period is desired, the clamp on COMP can be set externally with a resistor and capacitor on the EN/SS pin as shown in Typical Application Circuit. The soft-start duration can be calculated by using the following formula: Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VDD quiescent current and I losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VDD quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from V DD to ground. The resulting ΔQ/Δt is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VDD and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor R L. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (DC) as follows : RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I 2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations In most applications, the RT8004 does not dissipate much heat due to its high efficiency. But, in applications where the RT8004 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the RT8004 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by : T R = PD x θJA Where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by : TJ = TA + TR Where TA is the ambient temperature. (s) )1.8VV Vln( x C x RT IN IN SSSSSS

DS8004-03 September 2007 www.richtek.com As an example, consider the RT8004 in dropout at an input voltage of 3.3V, a load current of 3A and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the R DS(ON) of the P-Channel switch at 70 °C is approximately 97m Ω. Therefore, power dissipated by the part is : PD = (ILOAD)2 (RDS(ON)) = (3A)2 (97mΩ) = 0.873W For the TSSOP package, the θJA is 47 °C/W. Thus the junction temperature of the regulator is : Which is below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance DS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of C OUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem. The COMP pin external components and output capacitor shown in Typical Application Circuit will provide adequate compensation for most applications. Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8004. z A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the GND pin at one point that is then connected to the PGND pin close to the IC. The exposed pad should be connected to GND. z Connect the terminal of the input capacitor(s), CIN, as close as possible to the PVDD pin. This capacitor provides the AC current into the internal power MOSFETs. z LX node is with high frequency voltage swing and should be kept small area. Keep all sensitive small-signal nodes away from LX node to prevent stray capacitive noise pick-up. z Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, SVIN, V OUT, PGND, SGND, or any other DC rail in your system). z Connect the FB pin directly to the feedback resistors. The resistor divider must be connected between V OUT and GND.

DS8004-03 September 2007www.richtek.com Outline Dimension F B C I H D A J M Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 9.804 10.008 0.386 0.394 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 16–Lead SOP Plastic Package

DS8004-03 September 2007 www.richtek.com Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.850 1.200 0.033 0.047 A1 0.000 0.150 0.000 0.006 A2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 D 4.900 5.100 0.193 0.201 e 0.65 0.026 E 6.200 6.600 0.244 0.260 E1 4.300 4.500 0.169 0.177 L 0.450 0.750 0.018 0.030 U 2.000 3.000 0.079 0.118 V 2.000 3.000 0.079 0.118 16-Lead TSSOP (Exposed Pad) Plastic Package L e E A A2 b D (Bottom of Package) EXPOSED THERMAL PAD U V

DS8004-03 September 2007www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Richtek Technology Corporation Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com A D E L be SEE DETAIL A Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.250 0.380 0.010 0.015 D 3.950 4.050 0.156 0.159 D2 2.000 2.450 0.079 0.096 E 3.950 4.050 0.156 0.159 E2 2.000 2.450 0.079 0.096 e 0.650 0.026 L 0.500 0.600 0.020 0.024 V-Type 16L VQFN 4x4 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2