RT6908

RT6908 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

zzzzz 9V to 16V Input Supply Voltage zzzzz 4.4A Boost Regulator for AVDD with 12.7V to 19V Programmable Output zzzzz 1-CH Sync. Buck Converter for VI/O zzzzz 1-CH Sync. Buck Controller for VCORE zzzzz Negative Charge Pump Regulator for VGL with zzzzz Positive Charge Pump Regulator for VGH with 24.5V to 40V Programmable Output zzzzz Programmable Sequencing zzzzz Voltage Detection Output zzzzz Over Temperature Protection zzzzz I2C Compatible Interface for Register Control zzzzz Thin 40-Lead WQFN Package zzzzz RoHS Compliant and Halogen Free RT6908 Package Type QW : WQFN-40L 5x5 (W-Type) Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free) Marking Information PGND RSTB COMP1 LXI GD AVDD VDET SDA SCL FBB1 BOOT2 NC DHB2 DRVN CRST COMP2 FBB2 DLB2 ILIMIT2 LXB2 COMP PGND LX LX LX PGND VGL VGH DRVP LXB1 LXB1 BOOT1 NC VINB1 AVIN AGND VL EN EN_I2C 20191817161514131211 31323334353637383940 PGND RT6908ZQW : Product Number YMDNN : Date CodeRT6908 ZQW YMDNN

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Typical Application Circuit RT6908 LX LXI AVIN 14, 15, 16 120µF 6.8µH 1µF VL BOOT1

36 VINB1

1µF 0.1µF 10µF 22µF VIN 12V 39, 40 LXB1 10µH FBB12 VI/O 3.3V A0 12 RSTB 4 AVDD 100k 47nF 0.22µF 6.8 35.5V VGH DRVP VGH LXB1 AGND 34 1, 13, 17, 41 (Exposed Pad) PGND 2.2nF 4.7nF GD AVDD 10µF 22µF x 2 100pF 47k 15k 0.1µF 6.8 0.22µF 6.8 LX6.8 10µF AVDD 15.6V SDA VI/O SCL SCL SDA 4.7k 4.7k 4.7k RSTB 100k DRVN 21 0.22µF 6.8 LXB16.8 47nF -6V VGL 10µF VGL 18 22CRST 22nF VCORE 1.1V 10µF 4.7µH VIN 0.22µF 1nF 1.5

30 BOOT2

28 DHB2

26 DLB2

29 LXB2

24 FBB2

23 COMP2

1.2k 470pF 22µF x 3 20k EN32VL EN_I2C31VL VDET7VI/O 47k 15k 470pF

3 COMP1

25 ILIMIT2

1µFQ2 C10 C14 C15 C16 R10 C17 C18 R16 R17 R18 C27 R19 C28 R20 R21 C29 11 220k 330pF COMP R22 C30

connected to PGND for maximum thermal dissipation. 2 FBB1 Feedback Input for Buck1 Converter. 4 RSTB Voltage Detector Open-Drain Output. 5 SDA I2C Compatible Serial Data Input/Output. 6 SCL I2C Compatible Serial Clock Input. 7 VDET Voltage Detector Input. 8 AVDD Output Sense Pin for Boost Converter AVDD. 10 LXI Isolation Switch Input. 12 A0 I2C Compatible Device Address Bit 0. 18 VGL Output Sensing Pin of VGL Negative Charge Pump. 19 VGH Output Sensing Pin of VGH Positive Charge Pump. 20 DRVP Base Drive of External PNP Transistor for VGH Positive Charge Pump. 21 DRVN Base Drive of External NPN Transistor for VGL Negative Charge Pump. 23 COMP2 Compensation Pin for Buck2 Converter. 24 FBB2 Feedback Input for Buck2 Converter. ILIMIT2 to AGND to adjust the current limit threshold below 300mV. 26 DLB2 Low Side Gate Driver Output for Buck2 Converter. Figure 3. I2C Interface Timing Diagram

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Pin No. Pin Name Pin Function 28 DHB2 High Side Gate Driver Output for Buck2 Converter.

29 LXB2 Buck2 Converter Switch node Between High Side MOSFET and Low Side

MOSFET . 30 BOOT2 N-MOSFET Gate Drive Voltage for Buck2 Converter. Connect a capacitor from the switch node LXB2 to this pin. 31 EN_I2C Enable for I 2C Control. AVDD, VGL, VGH enabled by I2C Control. 32 EN Chip Enable (Active High). Tie to VL to enable the device. 33 VL Internal Logic Regulator Output. Connect this pin with a decoupling capacitor. 34 AGND Analog Ground. 35 AVIN Analog Input Voltage of the Device. This is the input for the analog circuits. Connect this pin with a decoupling capacitor. 36 VINB1 Power Input Voltage Pins for the VI/O Buck Converter. 38 BOOT1 N-MOSFET Gate Drive Voltage for Buck1. Connect a capacitor from the switch node LXB1 to this pin. 39 LXB1 Buck1 Switch node Between High Side MOSFET and Low Side MOSFET. 40 LXB1 Buck1 Switch node Between High Side MOSFET and Low Side MOSFET. Function Block Diagram Internal Regulator Sync. Buck1 AVIN VL BOOT1 VINB1 LXB1 FBB1 BOOST LXI GD AVDD COMP LX Sequence Control EN_I2C DC/DC DAC REG I2C Interface SDA SCL VDET VGL Regulator VL DRVN VGH Regulator DRVP VGH DHB2 PGND AGND Voltage Detector EN RSTB CRST Sync. Buck2 LXB2 DLB2 FBB2 COMP2 ILIMIT2 BOOT2 VL VGL COMP1

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© (Typical values VIN = VAVIN = VINB = 12V, VAVDD = 15.6V, VI/O = 3.3V, VCORE = 1.1V, VGH = 35.5V, VGL = −6V, TA = 25°C, unless otherwise specified)

Electrical Characteristics

Recommended Operating Conditions (Note 4) Parameter Symbol Test Conditions Min Typ Max Unit Supply Current Input Voltage Range V IN 9 -- 16 V AVIN Quiescent Current I QIN LX, LXBx Not Switching -- 3.5 -- mA VIN Rising -- 8.6 9 VIN Falling 7.2 7.6 -- Under Voltage Lockout Threshold V UVLO VIN Falling Latch Reset -- 5 -- V VL Output Voltage V L -- 5 -- V Fault Detection Fault Trigger Duration -- 50 -- ms Thermal Shutdown Threshold Temperature Rising -- 150 -- °C Thermal Shutdown Hysteresis -- 50 -- °C Absolute Maximum Ratings (Note 1) z EN, EN_I2C, AVIN, VINB1, LXI, GD, AVDD, LX, LXB1, LXB2, z SDA, SCL, A0, RSTB, CRST, VL, COMP, COMP1, COMP2, FBB1, z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Parameter Symbol Test Conditions Min Typ Max Unit Logic Inputs (SDA, SCL, EN, EN_I2C) Input High Voltage V IH 1.7 -- -- V Input Low Voltage V IL -- -- 0.6 V Input Leakage Current I IH, IIL V IN = 0 or 3.3V −1 0.01 1 μA Input Capacitance -- 5 -- pF SDA Output Low Voltage V OL I SINK = 6mA -- 0.3 -- V I2C Timing Characteristics Serial-Clock Frequency f SCL 0 -- 400 kHz Bus Free Time Between STOP and START Conditions tBUF 1.3 -- -- μs Hold Time (Repeated) START Condition tHD, STA 0.6 -- -- μs SCL Pulse-Width Low t LOW 1.3 -- -- μs SCL Pulse-Width High t HIGH 0.6 -- -- μs Setup Time for a Repeated START Condition tSU, STA 0.6 -- -- μs Data Hold Time t HD, DAT 0 -- 800 ns Data Setup Time t SU, DA T 100 -- -- ns SDA and SCL Receiving Rise Time tR 20 + 0.1CB -- 300 ns SDA and SCL Receiving Fall Time t F 20 + 0.1CB -- 300 ns SDA Transmitting Fall Time t F 20 + 0.1CB -- 250 ns Setup Time for STOP Condition t SU, STO 0.6 -- -- μs Bus Capacitance C B -- -- 400 pF Pulse Width of Suppressed Spike t SP -- -- 50 ns Reset Voltage Detector Minimum Operating Voltage AVIN Minimum Voltage for RSTB 2.2 -- -- V VDET Detecting Threshold V TH VDET Falling -- 0.6 -- V VDET Threshold Hysteresis ΔVTH -- 100 -- mV RSTB Output Low Voltage V OL I SINK = 500μA -- -- 0.3 V RSTB Leakage Current I LEAK V RSTB = 5.0V -- 0.01 0.1 μA CRST Charge Current I CRST -- 8 -- μA CRST Threshold V CRST -- 1.25 -- V Boost Converter (AVDD) Adjustable Output Voltage Range V AVDD Register Address = ”00h”, 6 bits, AVDD = (12.7V to 19V) [00h to 3Fh] 12.7 -- 19 V AVDD Regulation Voltage (Default) VAVDD No load 15.444 15.6 15.756 V Oscillator Frequency f OSC 600 750 900 kHz Maximum Duty Cycle -- 90 -- %

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Parameter Symbol Test Conditions Min Typ Max Unit N-MOSFET On-Resistance R DS(ON) I LX = 500mA -- 120 -- m Ω N-MOSFET Switch Current Limit ILIM 4.4 5.6 -- A Switch Leakage Current I leak V LX = 19V -- 1 10 μA LXI Over Voltage Protection V OVP V LX Rising, Hysteresis = 1V 19.5 20 -- V AVDD Line Regulation 9V ≤ VIN ≤ 16V, IOUT = 1mA -- 0.004 -- %/V AVDD Load Regulation 1mA ≤ IOUT ≤ 2A -- 0.1 -- %/A Trans-Conductance of Error Amplifier gm -- 100 -- μA/V AVDD Fault Trip Level V FT_AVDD V AVDD Falling VAVDD x 76% VAVDD x 80% VAVDD x 84% V Isolation Switch Control GD Pull Down Voltage V LXI − VGD 5 6 7 V GD Sink Current I GD 8 12 16 µA GD Pull Up Resistance R GD 8 12 16 k Ω Short-Circuit Trigger Duration I AVDDD ≥ ILIMGD / RON, PMOS -- 200 -- μs Buck1 Controller (VI/O) FBB1 Regulation Voltage V FBB1 No Load 0.788 0.8 0.812 V Oscillator Frequency f OSC 400 500 600 kHz Phase Shift Between Buck1 and Buck2 -- 180 ° -- -- Maximum Duty Cycle -- 86 -- % Trans-Conductance of Error Amplifier gm -- 100 -- μA/V LXB1 to VINB1 N-MOSFET On-Resistance RDS(ON) I LXB1 = 500mA -- 200 -- m Ω LXB1 to PGND N-MOSFET On-Resistance I LXB1 = 500mA -- 150 -- m Ω Soft-Start Period T SS_I/O -- 300 -- μs FBB1 Fault Trip Level V FBB1 Falling 0.6144 0.64 0.6656 V LXB1 Positive Current Limit I LIM 3 3.8 -- A Buck2 Controller (VCORE) FBB2 Regulation Voltage V FBB2 No Load 0.788 0.8 0.812 V Oscillator Frequency f OSC 400 500 600 kHz Phase Shift Between Buck1 and Buck2 -- 180 ° -- -- Maximum Duty Cycle -- 50 -- % BOOT2 to DHB2 P-MOSFET On-Resistance RUG(ON)_DHB2 I LXB2 = 100mA -- 1.8 -- Ω DHB2 to LXB2 N-MOSFET On-Resistance RLG(ON)_DHB2 I LXB2 = 100mA -- 0.6 -- Ω LXB2 to DLB2 P-MOSFET On-Resistance RUG(ON)_DLB2 I LXB2 = 100mA -- 2 -- Ω DLB2 to PGND N-MOSFET On-Resistance RLG(ON)_DLB2 I LXB2 = 100mA -- 0.5 -- Ω Soft-Start Period T SS_CORE -- 300 -- μs

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Parameter Symbol Test Conditions Min Typ Max Unit FBB2 Fault Trip Level V FBB2 Falling 0.6144 0.64 0.6656 V FBB2 Short Trip Level V FBB2 Falling -- 0.16 -- V ILIMIT2 Source Current -- 40 -- μA Low Side Switch Current Limit Cycle by Cycle -- VILIMIT2 / 8 -- V Maximum ILIMIT2 Voltage Setting -- 2.4 -- V Negative Charge Pump Controller (VGL) VGL Adjustable Output Voltage Range VGL Register Address = ”02h”, 6 bits, VGL VGL Regulation Voltage (Default) VGL V DRVN = 0.6V, IDRVN = −100μA −6.3 −6 −5.7 V DRVN Sink Current Limit I DRVN,MAX V DRVN = 0.6V -- 3.5 5 mA DRVN Short Circuit Current IDRVN,SC V GL > −0.5V -- 300 -- μA VGL Load Regulation Error VDRVN = 0.6V, −50μA < IDRVN < −1mA -- 60 -- mV/mA Soft-Start Period T SS -- 3 -- ms VGL Fault Trip Level V GL Rising VGL + 1.5 -- VGL + 2.5 V VGL Short Trip Level V GL Rising −0.5 V Positive Charge Pump Controller (VGH) VGH Adjustable Output Voltage Range VGH Register Address = ”01h”, 5 bits, VGH = (24.5V to 40V) [00h to 1Fh] 24.5 -- 40 V VGH Regulation Voltage (Default) VGH V DRVP = 15.6V, IDRVP = 100μA 34.79 35.5 36.21 V DRVP Source Current Limit IDRVP,MAX V DRVP = 15.6V -- 3.5 5 mA DRVP Short Circuit Current IDRVP,SC V GH < 20% -- 80 -- μA VGH Load Regulation Error V DRVP = 15.6V, 50μA < IDRVP < 1mA -- 300 -- mV/mA Soft-Start Period T SS -- 4 -- ms VGH Fault Trip Level V GH Falling VGH x 70 VGH x 75 VGH x 80 % VGH Short Trip Level V GH Falling -- 20 -- % Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 °C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions.

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Typical Operating Characteristics Boost Efficiency vs. Load Current 100 0 0.4 0.8 1.2 1.6 2 Load Current (A) Efficiency (%) VIN = 12V, VAVDD = 15.6V Buck1 Efficiency vs. Load Current 100 0 0.4 0.8 1.2 1.6 2 Load Current (A) Efficiency (%) VIN = 12V, VI/O = 3.3V Buck2 Efficiency vs. Load Current 100 0 0.4 0.8 1.2 1.6 2 Load Current (A) Efficiency (%) VIN = 12V, VCORE = 1.1V Buck1 Output Voltage vs. Load Current 2.4 2.7 3.0 3.3 3.6 3.9 00 . 511 . 52 Load Current (A) Output Voltage (V) VIN = 12V, VI/O = 3.3V Buck2 Output Voltage vs. Load Current 0.8 0.9 1.0 1.1 1.2 1.3 00 . 511 . 52 Load Current (A) Output Voltage (V) VIN = 12V, VCORE = 1.1V Boost Output Voltage vs. Load Current 14.0 14.5 15.0 15.5 16.0 16.5 17.0 00 . 511 . 52 Load Current (A) Output Voltage (V) VIN = 12V, VAVDD = 15.6V

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Buck2 Output Voltage vs. Temperature 0.8 0.9 1.0 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 12V, VCORE = 1.1V VGH Output Voltage vs. Temperature - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) Output Voltage (V) VIN = 12V, VGH = 35.5V Buck1 Output Voltage vs. Temperature 3.0 3.1 3.2 3.3 3.4 3.5 - 5 0- 2 5 0 2 5 5 0 7 51 0 0 1 2 5 Temperature (°C) Output Voltage (V) VIN = 12V, VI/O = 3.3V Boost Output Voltage vs. Temperature 14.0 14.5 15.0 15.5 16.0 16.5 17.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 12V, VAVDD = 15.6V VGH Output Voltage vs. Load Current 0 1 53 04 56 07 5 Load Current (mA) Output Voltage (V) VIN = 12V, VGH = 35.5V VGL Output Voltage vs. Load Current 0 1 53 04 56 07 5 Load Current (mA) Output Voltage (V) VIN = 12V, VGL = −6V

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Time (500 μs/Div) Boost Load Transient Response VIN = 12V, VAVDD = 15.6V, R22 = 220kΩ, C30 = 330pF, C31= 10pF VAVDD_ac (500mV/Div) IAVDD (1A/Div) Time (100ms/Div) VIN = 12V, VAVDD = 15.6V, VI/O = 35.5V, VGL = -6V, C17= 22nF Power On Sequence 2 VAVDD (10V/Div) VGH (20V/Div) VGL (5V/Div) VRSTB (2V/Div) Time (500 μs/Div) Buck1 Load Transient Response VIN = 12V, VI/O = 3.3V, R4 = 120kΩ, C19 = 470nF VI/O_ac (100mV/Div) II/O (1A/Div) Time (500 μs/Div) Buck2 Load Transient Response VIN = 12V, VCORE = 1.1V, R23 = 24kΩ, C25 = 1nF, C26 = 10pF, R14 = 1.2kΩ, C23 = 470pF VCORE_ac (100mV/Div) ICORE (1A/Div) VGL Output Voltage vs. Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 12V, VGL = −6V Time (1ms/Div) Power On Sequence 1 VEN (5V/Div) VCORE (1V/Div) VI/O (2V/Div) VRSTB (2V/Div) VIN = 12V, VCORE = 1.1V, VI/O = 3.3V, C17= 22nF

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.©

Application Information

Single I2C Register Write Protocol Single I2C Register Read Protocol Multiple I2C Register Write Protocol Multiple I2C Register Read Protocol Register Map Address Name Description Default Value Resolution Range 00h AVDD [5 : 0] Boost 15.6V (1Dh) 0.1V 12.7V to 19V (00h to 3Fh) 01h VGH [4 : 0] VGH 35.5V (16h) 0.5V 24.5V to 40V (00h to 1Fh) 02h VGL [5 : 0] VGL −6V (2Ah) −0.1V −1.8V to −8.1V (00h to 3Fh) 03h VIO [3 : 0] VIO adjustment 0% (07h) 1% −7% to 7% (00h to 0Eh) 04h V CORE [3 : 0] V CORE adjustment 0% (07h) 1% −7% to 7% (00h to 0Eh) 05h DLY1 [3 : 0] VGL Delay Time 200ms (01h) DLYR1 0 to 15 x DLYR1 (00h to 0Fh) 06h DLY2 [3 : 0] AVDD Delay Time 400ms (02h) DLYR2 0 to 15 x DLYR2 (00h to 0Fh) 07h DLY3 [3 : 0] VGH Delay Time 10ms (01h) DLYR3 0 to 15 x DLYR3 (00h to 0Fh) 08h DLYR1 [1 : 0] DLY1 Resolution 200ms (02h) 1ms, 10ms, 200ms 09h DLYR2 [1 : 0] DLY2 Resolution 200ms (02h) 1ms, 10ms, 200ms 0Ah DLYR3 [1 : 0] DLY3 Resolution 10ms (01h) 1ms, 10ms, 200ms 0Bh SS [3 : 0] AVDD Soft-Start Time 2ms (02h) 1ms 0ms to 15ms (00h to 0Fh) 0Ch ILIMGD [3 : 0] Isolation Switch Current Limit Disable (00h) 50mV Disable, 100mV to 800mV (00h to 0Fh) FFh CTRL [7 : 0] ’’55h’’ Start Power On Sequence 00h Slave Address 1 1 0 1 0 0 0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK StopSlave ACK Slave ACKA0Stop Slave Address 1 1 0 1 0 0 0 Register Address Slave ACK Slave ACKStop Slave ACKA0 MasterNACK Stop Slave Address Re- Start 1 1 0 1 0 0 1A0 D7 D6 D5 D4 D3 D2 D1 D0 Slave Address 7 6 5 4 3 2 1 0 = LSB 1 1 0 1 0 0 A0 R/W Slave Address 1 1 0 1 0 0 0 Register Address D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK Slave ACK Slave ACKA0Stop D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK D7 D6 D5 D4 D3 D2 D1 D0 Slave ACK Stop Slave Address 1 1 0 1 0 0 0 Register Address Slave ACK Slave ACKStop Slave ACKA0 Master NACK Stop Slave Address Re- Start 1 1 0 1 0 0 1A0 D7 D6 D5 D4 D3 D2 D1 D0Master ACKD7 D6 D5 D4 D3 D2 D1 D0

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Output Code Table (unit : V) Register Code AVD D VGH VGL VIO V CORE DLY1 DLY2 DLY3 DLYR1 DLYR2 DLYR3 SS ILIMGD 00h 12.7 24.5 −1.8 −7% −7% 0ms 0ms 0ms 1ms 1ms 1ms 0ms disable 01h 12.8 25.0 −1.9 −6% −6% 1ms 1ms 1ms 10ms 10ms 10ms 1ms 100mV 02h 12.9 25.5 −2.0 −5% −5% 2ms 2ms 2ms 200ms 200ms 200ms 2ms 150mV 03h 13.0 26.0 −2.1 −4% −4% 3ms 3ms 3ms 3ms 200mV 04h 13.1 26.5 −2.2 −3% −3% 4ms 4ms 4ms 4ms 250mV 05h 13.2 27.0 −2.3 −2% −2% 5ms 5ms 5ms 5ms 300mV 06h 13.3 27.5 −2.4 −1% −1% 6ms 6ms 6ms 6ms 350mV 07h 13.4 28.0 −2.5 0 0 7ms 7ms 7ms 7ms 400mV 08h 13.5 28.5 −2.6 1% 1% 8ms 8ms 8ms 8ms 450mV 09h 13.6 29.0 −2.7 2% 2% 9ms 9ms 9ms 9ms 500mV 0Ah 13.7 29.5 −2.8 3% 3% 10ms 10ms 10ms 10ms 550mV 0Bh 13.8 30.0 −2.9 4% 4% 11ms 11ms 11ms 11ms 600mV 0Ch 13.9 30.5 −3.0 5% 5% 12ms 12ms 12ms 12ms 650mV 0Dh 14.0 31.0 −3.1 6% 6% 13ms 13ms 13ms 13ms 700mV 0Eh 14.1 31.5 −3.2 7% 7% 14ms 14ms 14ms 14ms 750mV 0Fh 14.2 32.0 −3.3 15ms 15ms 15ms 15ms 800mV 10h 14.3 32.5 −3.4 1 1h 14.4 33.0 −3.5 12h 14.5 33.5 −3.6 13h 14.6 34.0 −3.7 14h 14.7 34.5 −3.8 15h 14.8 35.0 −3.9 16h 14.9 35.5 −4.0 17h 15.0 36.0 −4.1 18h 15.1 36.5 −4.2 19h 15.2 37.0 −4.3 1Ah 15.3 37.5 −4.4 1Bh 15.4 38.0 −4.5 1Ch 15.5 38.5 −4.6 1Dh 15.6 39.0 −4.7 1Eh 15.7 39.5 −4.8 1Fh 15.8 40.0 −4.9 20h 15.9 −5.0 21h 16.0 −5.1 22h 16.1 −5.2 23h 16.2 −5.3 24h 16.3 −5.4 25h 16.4 −5.5

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© Register Code AVDD VGH VGL VIO V CORE DLY1 DLY2 DLY3 DLYR1 DLYR2 DLYR3 SS ILIMGD 26h 16.5 −5.6 27h 16.6 −5.7 28h 16.7 −5.8 29h 16.8 −5.9 2Ah 16.9 −6.0 2Bh 17.0 −6.1 2Ch 17.1 −6.2 2Dh 17.2 −6.3 2Eh 17.3 −6.4 2Fh 17.4 −6.5 30h 17.5 −6.6 31h 17.6 −6.7 32h 17.7 −6.8 33h 17.8 −6.9 34h 17.9 −7.0 35h 18.0 −7.1 36h 18.1 −7.2 37h 18.2 −7.3 38h 18.3 −7.4 39h 18.4 −7.5 3Ah 18.5 −7.6 3Bh 18.6 −7.7 3Ch 18.7 −7.8 3Dh 18.8 −7.9 3Eh 18.9 −8.0 3Fh 19.0 −8.1 40h If register data out of spec, IC will be into default value.

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© The RT6908 is a programmable multi-functional power solution for TFT LCD panels. The RT6908 contains a step- up converter for main power, a synchronous buck converter and a synchronous buck controller to provide the logic voltages for timing controller, voltage detector for the system. Moreover, a positive charge pump regulator provides the adjustable gate-high voltage and a negative charge pump regulator provides the gate low voltage. Boost Converter The boost converter is high efficiency PWM architecture. It performs fast transient responses to generate source driver supplies for TFT LCD display. The high operation frequency allows use of smaller components to minimize the thickness of the LCD panel. The output voltage can be achieved by setting the I 2C register 00h [5:0]. The Boost minimum gain ratio depends on minimum on time. It suggested that AVDD higher than 1.14XVIN for better performance. Boost Soft-Start The main boost converter has an internal soft-start function to reduce the input inrush current. The soft-start time can be achieved from 0ms to 15ms by setting the I 2C register 0Bh [3:0]. Boost Over Voltage Protection The main boost converter has an over voltage protection to protect the main switch at the LXI pin. When the LXI pin voltage rises above 20V, the boost converter turns the switch off. As soon as the output voltage falls below the over voltage threshold, the converter will resume operation. Boost Over Current Protection The RT6908 senses the inductor current that is flowing into the LX pin. The internal N-MOSFET will be turned off if the peak inductor current reaches 5.6A (typ.). Thus, the output current at the current limit boundary, denoted as I OUT(LIM), can be calculated according to the following equation : IN OUT IN SINOUT(LIM) LIM OUT OUT V( V V ) TV 1I = I V2 VL where η is the efficiency of the boost converter, ILIM is the value of the current limit and TS is the switching period. Boost Short Circuit Protection The main boost converter has a short circuit protection. This function disables the boost converter and isolation P-MOSFET if the difference voltage between the LXI and AVDD pin larger than ILIMGD I2C register 0Ch [3:0] setting. The IC will shut down if this difference voltage remains above setting value after 200μs. Besides, IC will also shut down if input voltage below UVLO threshold at AVDD short circuit period. Only input voltage below 5V (typ.) then re- power on and remove fault condition, IC can return to normal operation. Boost Under Voltage Fault Protection The main boost converter has a fault protection. This function disables the boost converter if AVDD is detected to be below 80%. The IC will shut down if AVDD remains below 80% after 50ms. Boost Inductor Selection The inductor value depends on the maximum input current. As a general rule the inductor ripple current is 20% to 40% of maximum input current. If 40% is selected as an example, the inductor ripple current can be calculated according to the following equation : η OUT OUT(MAX) IN(MAX) IN RIPPLE IN(MAX) VII = V I = 0 . 4 I where η is the efficiency of the boost converter, IIN(MAX) is the maximum input current and IRIPPLE is the inductor ripple current. The input peak current can be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : I PEAK = IRIPPLE + IIN(MAX) = 1.2 IIN(MAX) Note that the saturated current of inductor must be greater than IPEAK. The inductance can eventually be determined according to the following equation : () ( ) η××− ×× × IN OUT IN OUT OUT(MAX) OSC VV VL =

0.4 V I f

where fOSC is the switching frequency. For better system performance, a shielded inductor is preferred to avoid EMI problems.

the input ripple voltage caused by the switching operation. evaluated based on the ideal energy equalization. Figure 4. The Output Ripple Voltage without the external compensation network consisted of R22 and C30. integrator zero to maintain stability. close as possible to the chip can reduce noise sensitivity.

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© VI/O Buck Soft-Start The step-down converter has an internal soft-start to reduce the input inrush current. When the buck converter is enabled, the output voltage rises slowly from zero to the regulated voltage. The typical soft-start time is around 300μs. VI/O Buck Over Current Protection The IC senses the inductor current that is flowing out the LXB1 pin. The internal MOSFET will be turned off if the peak inductor current reaches 3.8A (typ.). VI/O Buck Short Circuit Protection To limit the short circuit current, the device has a cycle- by-cycle current limit. To avoid the short circuit current from rising above the internal current limit when the output is shorted to GND, the switching frequency is reduced as well. The switching frequency is reduced to one-half of original frequency when the output voltage is below 80% and to one-fourth of the original frequency when the output voltage is below 20%. If the “short” is removed, the buck converter will resume operation. If the voltage remains below 80% after 50ms, the IC will shut down. VI/O Buck Loop Compensation The voltage feedback loop can be compensated with an external compensation network consisted of the R4 and C19. Choose R4 to set high frequency integrator gain for fast transient response. And choose the C19 to set the integrator zero to maintain stability. VCORE Synchronous Buck Controller The synchronous buck controller is a high efficiency PWM architecture with 500kHz operation frequency and fast transient response. The controller need external high side and low side N-MOSFET as synchronous rectifier and does not required Schottky diode on the LXB2 pin. The high side MOSFET is connected between VIN and the LXB2 pin, while the low side MOSFET is connected between the LXB2 pin and GND. VCORE Buck Output Voltage Setting The regulated default output voltag e as shown in the following equation : The recommended value for R11 should be up to 10kΩ without some sacrificing. Place the resistor divider as close as possible to the chip can reduce noise sensitivity. The output voltage also can be adjusted from −7% to 7% by setting the I 2C register 04h [3:0]. VCORE Buck Soft-Start The synchronous buck converter has an internal soft-start to reduce the input inrush current. When the converter is enabled, the output voltage rises slowly from zero to the regulated voltage. The typical soft-start time is around 300μs. VCORE Buck Over Current Protection The IC has a cycle-by-cycle low side source current sensing algorithm that uses the on-resistance of the low side MOSFET as a current sensing element, so that costly sense resistors are not required. The DHB2 and DLB2 will be turned off if the low side MOSFET source current reaches setting value. Moreover, IC will restart after 50ms if over current remains 7 cycles. Low side source peak current limit threshold is 1/8 voltage at the ILIMT2 pin. Meanwhile, the real current limit value need consider the on-resistance of the low side MOSFET. CORE FBB2 FBB2 R11V = V 1 + , where V = 0.8V (typ.)R12 ILIMIT2LIM_M2 ON VI = ( A ) 8R ( s w i t c h ) when ILIM_M2 is “Low side switch current limit”. VCORE Buck Short Circuit Protection To limit the short circuit current, the device has a cycle- by-cycle current limit. To avoid the short circuit current from low side MOSFET source current limit when the output is shorted to GND, the switching operation will be stop. The switching operation will stop when the output voltage is below 20%. If the short is removed, the buck converter will resume operation. If the voltage remains below 80% after 50ms, the IC will shut down. VCORE Buck Loop Compensation The voltage feedback loop can be compensated with an external compensation network consisted of R23 and C25 and C26. Choose R23 to set high frequency integrator gain for fast transient response, C25 and C26 to set the integrator zero to maintain stability.

DS6908-01 March 2013 www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© VCORE Buck External MOSFET Selection The VCORE buck controller drives two external N-MOSFETs as the switch. There are some considerations to choose the external MOSFET. It includes MOSFET drain to source voltage stress, on-resistance, total gate charge characteristics and power dissipation for thermal performance. Buck Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current, ΔI L, will increase with higher VIN and decrease with higher inductance, as shown in below equation : OUT OUTL OSC IN VVI = 1 fL V Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve the highest efficiency operation. However, it requires a large inductor to achieve this goal. For the ripple current selection, the value of I L(MAX) = 0.4 is a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : OUT OUT OSC L(MAX) IN(MAX) VVL = 1 fI V Buck Input Capacitor Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high-side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by : ×× −OUT INRMS OUT(MAX) IN OUT V VI = I 1 VV This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For the input capacitor, a 10μF low ESR ceramic capacitor is recommended. Buck Output Capacitor Selection The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, V OUT, is determined by : OUT L OSC OUT 1V = I ESR + 8f C The output ripple will be highest at the maximum input voltage since I L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Suitable candidates such as dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications requiring high ripple current rating and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Nevertheless, higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input, VIN, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part.

DS6908-01 March 2013www.richtek.com Copyright 2013 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.© VGL Negative Regulator The VGL negative regulator controller provides low level voltage for gate driver. The linear regulator can provide a programmable output voltage. The output voltage can be adjusted by setting the I 2C register 02h [5:0]. The VGL negative regulator controller has a fault protection. This function can disable the VGL negative regulator controller when the VGL voltage is detected to be above VGL + 2V. If the voltage remains above VGL + 2V after 50ms, the IC will shut down. Moreover, If VGL voltage above −0.5V, the IDRVN source current will be limited to 300μA for short circuit protection. VGH Positive Regulator The VGH positive regulator controller provides high level voltage for gate driver. The linear regulator can provide a programmable output voltage. The output voltage can be adjusted by setting the I 2C register 01h [4:0]. The VGH positive regulator controller has a fault protection. This function can disable the VGH regulator controller when the VGH voltage is detected to be below 75%. If the VGH voltage remains below 75% after 50ms, the IC will shut down. Moreover, If VGH voltage remains below 20%, the I DRVP sink current will be limited to 80μA for short circuit protection. Voltage Detector The voltage detector monitors the VDET voltage to generate the RSTB pin signal. The RSTB pin will be floating and pulled high by V I/O if V DET is higher than the detecting level. Moreover, the detector power on delay can be determined by connect capacitor to the CRST pin and ground. The detecting level and delay time can be determined as the following equations : DET DET R25Detect voltage, falling = V 1 + , R26 where V =0.6V (typ.) Detector delay time = 0.1563 C17 10 (ms) Under Voltage Lockout Protection The UVLO circuit compares the input voltage at the AVIN pin with the UVLO threshold (8.6V rising, typ.) to ensure that the input voltage is high enough for reliable operation. The 1V (typ.) hysteresis prevents supply transients from causing a shutdown. Once the input voltage exceeds the UVLO rising threshold, start-up begins. When the input voltage falls below the UVLO falling threshold, all switch will be turned off and latched. Otherwise, input voltage need below 5V (typ.), the IC can be reset. Over Temperature Protection The RT6908 equips an Over Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when junction temperature exceeds 150 °C. Once the junction temperature cools down by approximately 50°C, the RT6908 will resume operation. To maintain continuous operation maximum, the junction temperature should be prevented from rising above 125°C. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT6908, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-40L 5x5 package, the thermal resistance, θJA, is 36°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125 °C − 25 °C) / (36 °C/W) = 2.778W for WQFN-40L 5x5 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT6908 package, the derating

DS6908-01 March 2013www.richtek.com Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138 E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138 e 0.400 0.016 L 0.350 0.450 0.014 0.018 W-Type 40L QFN 5x5 Package Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options 2 2 D E L b A e SEE DETAIL A