RT6542A

RT6542A RICHTEK | Alldatasheet

Document overview

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Technical content

Features

 Intel Cannon VR Support  Built-in 1% Reference Voltage  2-Bit Programmable Output Voltage with Integrated Transition Support  Support Intel LPM (Low-Power Mode) Feature  4700ppm/°°°°°C Programmable Current Limit by Low- Side RDS(ON) Sensing  3V to 26V Battery Input Range  Internal Voltage Ramp Soft-Start Control  Drives Large Synchronous Rectifier FETs  Integrated Boost Switch  Over/Under-Voltage Protection  Power Good Indicator  RoHS Compliant and Halogen Free  Tiny 14-Lead WDFN Package General Description The RT6542A PWM controller provides high efficiency, excellent transient response, and high DC output accuracy needed for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM supplies in notebook computers. The RT6542A supports on chip voltage programming function between 0.85V and 1.05V by controlling GX digital inputs. The constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients while maintaining a relatively constant switching frequency. The RT6542A achieves high efficiency at a reduced cost by eliminating the current-sense resistor found in traditional current-mode PWMs. Efficiency is further enhanced by its ability to drive very large synchronous rectifier MOSFETs and enter diode emulation mode at light load condition. The buck conversion allows this device to directly step down high voltage batteries at the highest possible efficiency. The RT6542A is intended for CPU core, chipset, DRAM, or other low voltage supplies as low as 0.7V. The RT6542A is available in a WDFN-14L 3x2 package. RT6542A VCC PHASE LGATE BOOT UGATE FB VIN CBYPASS EN VOUT R5* C2* GND CS PGOOD MODE RGND LPM VCC RCS R4 CIN LOUT COUT

DS6542A-01 September 2019www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin Configuration (TOP VIEW) WDFN-14L 3x2 Pin No. Pin Name Pin Function 1 MODE VCCIO/VPRIMCORE/V1.05A select pin. 2 PGOOD Open drain power good indicator. High impedance indicates power is good. 3 EN PWM enable control input. Do not leave this pin floating. 4 LPM Low power mode control pin. 5 BOOT BOOT bootstrap supply for high-side gate driver. 6 UGATE High-side gate driver output. 7 PHASE Switch node. External inductor connection for VDDQ and behave as the current sense comparator input for Low-Side MOSFET RDS(ON) sensing. 8 LGATE Low-side gate driver output. 9 VCC Supply voltage input for the analog supply and LGATE gate driver. 10 G0 2-bit input pin. 11 G1 2-bit input pin. 12 RGND Remote voltage sense ground pin. 13 FB Output voltage feedback input. Connect VOUT to converter output node. 14 CS Current limit threshold setting input. Connect a setting resistor to GND and the current limit threshold is equal to 1/10 of the voltage at this pin. 15 (Exposed Pad) GND Ground. The Exposed Pad must be soldered to a large PCB and connected to GND for maximum power dissipation.

Ordering Information

Note : Richtek products are :  RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. PGOOD EN FB RGND MODE CS BOOT PHASE VCC LGATE UGATE 1 14 GNDLPM Marking Information RT6542A Package Type QW : WDFN-14L 3x2 (W-Type) (Exposed Pad-Option 1) Lead Plating System G : Green (Halogen Free and Pb Free) 0VW 0V : Product Code W : Date Code

DS6542A-01 September 2019 www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Operation The RT6542A is a constant on-time synchronous step- down controller. In normal operation, the high-side N- MOSFET is turned on when the output voltage is lower than VREF, and is turned off after the internal one-shot timer expires. While the high-side N-MOSFET is turned off, the low-side N-MOSFET is turned on to conduct the inductor current until next cycle begins. Soft-Start (SS) For internal soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. The output voltage will track the internal ramp voltage during soft-start interval. PGOOD The power good output is an open-drain architecture. When the soft-start is finished, the PGOOD open-drain output will be high impedance. Current Limit The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. The current limit threshold can be set with an external voltage setting resistor on the CS pin. Over-Voltage Protection (OVP) & Under-Voltage Protection (UVP) The output voltage is continuously monitored for over- voltage and under-voltage protection. When the output voltage exceeds 1.2V (Typ.), UGATE goes low and LGATE is forced high. When the feedback voltage is less than 0.3V (Typ.), under-voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until VCC is re-supplied and exceeds the POR rising threshold voltage or EN is reset. R SQ BOOT UGATE PHASE VCC LGATE GND DRV Min Toff One shot Q TRIG One shot TRIG On-time compute Thermal Shutdown 0.675V PGOOD FB SS Timer Comp DEM Latch S1 Q Latch S1 Q PHASE ZCD OC threshold 10µA CS DRV - 1/10 BST switch resistance leakage UG Rds ON LG Rds ON TON EN Voltage ProgrammerG1 RGND MODE LPM UV OV 1.2V 0.3V +

DS6542A-01 September 2019www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. (VCC = 5V, VIN = 8V, VEN = 5V, VCS = 1V, TA = 25°C, unless otherwise specified)

Electrical Characteristics

Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1)  PHASE to GND  BOOT to PHASE  UGATE to PHASE  LGATE to GND  Power Dissipation, PD @ TA = 25°C  Package Thermal Resistance (Note 2)  ESD Susceptibility (Note 3) Parameter Symbol Test Conditions Min Typ Max Unit PWM Controller Supply Voltage V CC 4.5 -- 5.5 V VCC Quiescent Supply Current IQ FB forced above the regulation point, EN = 5V, LPM = 5V -- 200 -- A IQ_LPM FB forced above the regulation point, EN = 5V, LPM = 0V, VCCIO -- 30 -- A VCC Shutdown Supply Current ISD EN = 0V -- -- 10 A VFB Error Comparator Threshold G0 = 5V, G1 = 5V, MODE = floating 0.5 -- 0.5 %

DS6542A-01 September 2019 www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Switching Frequency V IN = 12V at CCM -- 560 -- kHz Minimum Off-Time 250 400 550 ns Current Sensing CS Current 9 10 11 A CS Current TC -- 4700 -- PPM/ C zero Crossing Threshold GND  PHASE 8 -- 4 mV Protection Function Current Limit Threshold Offset GND  PHASE = VCS/10 10 -- 10 mV Negative Current Limit Threshold Offset PHASE  GND = VCS/10 15 -- 15 mV UV Trip Level UV detect, falling edge 0.25 0.3 0.35 V UVP Delay V FB = 0.2V -- 5 -- s OV Trip Level OV detect, rising edge 1.14 1.2 1.26 V OVP Delay V FB = 1.31V -- 5 -- s VCC UVLO Threshold Rising edge 3.9 4.2 4.5 V VCC UVLO Hysteresis -- 100 -- mV Thermal Shutdown Latch -- 150 -- C Start Up & VID VOUT Soft-Start EN high to V OUT = 1.05V -- 2.4 -- ms Start Up Blanking Time From EN = high -- 7.4 -- ms Driver On-Resistance UGATE Driver (pull up) R UGATEsr BOOT-PHASE forced to 5V -- 2.5 5  UGATE Driver (sink) R UGATEsk BOOT-PHASE forced to 5V -- 1.5 3  LGATE Driver (pull up) R LGATEsr LGATE, high state -- 2.5 5  LGATE Driver (pull down) R LGATEsk LGATE, low state -- 0.8 1.6  Dead Time UGATE rising -- 20 -- ns LGATE rising -- 30 -- ns Internal Boost Charging Switch-On Resistance VCC to BOOT, 10mA -- -- 80  LOGIC I/O EN Input Voltage Controller OFF -- -- 0.4 V Controller ON 1.2 -- -- V G0, G1, LPM Input Voltage Logic Low -- -- 0.3 V Logic High 0.8 -- -- V MODE Select Logic-Low VPRIMCORE -- -- 0.8 V Logic-High VCCIO 2.7 -- -- V Float V1.05A 1.8 -- 2.2 V

DS6542A-01 September 2019www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit Parameter Symbol Test Conditions Min Typ Max Unit PGOOD (upper side threshold decide by OV threshold) Trip Threshold (falling) Hys = 3% 0.625 0.675 0.725 V Propagation Delay Falling edge, with respect to PGOOD threshold -- 3 -- s Output Low Voltage I SINK = 1mA -- -- 0.4 V Leakage Current High state, forced to 5V -- -- 1 A Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. RT6542A VCC9 PHASE LGATE BOOT UGATE FB VIN 0.1µF 01µF/16V EN3 100k R5* C2* 1µH 220µF x 2 15 (Exposed Pad) GND Off On CS14156k PGOOD2 MODE1 SM3380EHQG RGND 12 G0 10 LPM 4 G1 11 VVPRIMCORE : 1.05V/4.3A VV1.05A : 1.05V/5.5A VVCCIO : 0.95V/5.2A 20µF5V ILOAD = (0% to 70%) x IMAX (30% to 100%) x IMAX SR = 2.5A/µs

DS6542A-01 September 2019 www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Time 100 μs/Div) Load Transient Response ILOAD (4A/Div) PHASE (20V/Div) LGATE (50V/Div) VOUT (40mV/Div) VIN = 12V, VCC = VEN = 5V, VOUT = 1.05V, ILOAD= 0A to 3.85A Output Voltage vs. Output Current 0.96 0.98 1.00 1.02 1.04 1.06 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) VCC = VEN = 5V, VID = 1V VIN = 20V VIN = 12V VIN = 7.4V VIN = 5V Switching Frequency vs. Output Current 100 200 300 400 500 600 700 800 0.001 0.01 0.1 1 10 Output Current (A) Switching Frequency (kHz) 1 VCC = VEN = 5V, VID = 1V VIN = 5V VIN = 7.4V VIN = 12V VIN = 20V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VCC = VEN = 5V, VID = 1V VIN = 5V VIN = 7.4V VIN = 12V VIN = 20V Quiescent Current vs. Input Voltage 100 150 200 250 5 1 01 52 02 5 Input Voltage (V) Quiescent Current (μA) VCC = V EN = 5V, No Switching LPM = 0 LPM = 1 Shutdown Current vs. Input Voltage 0.5 1.5 2.5 3.5 4.5 5 1 01 52 02 5 Input Voltage (V) Shutdown Current (μA) 1 VCC = 5V, VEN = 0V

DS6542A-01 September 2019www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (2ms/Div) Power On from EN PGOOD (5V/Div) EN (5V/Div) VOUT (1V/Div) PHASE (20V/Div) VIN = 12V, VCC = 5V, VEN = 0V  5V, VID = 1V, ILoad = 0.2A Time (2ms/Div) Power Off from EN PGOOD (5V/Div) EN (5V/Div) VOUT (1V/Div) PHASE (20V/Div) VIN = 12V, VCC = 5V, VEN = 5V  0V, VID = 1V, ILOAD = 0.2A Time (50 μs/Div) LPM Ramp Up (VCCIO) VVCCIO (1V/Div) PHASE (20V/Div) VIN = 12V, VCC = VEN = 5V, LPM = 0V 5V LPM (5V/Div) PGOOD (5V/Div) Time (100 μs/Div) Under-Voltage Protection PGOOD (5V/Div) PHASE (20V/Div) LGATE (10V/Div) VOUT (1V/Div) VIN = 12V, VCC = VEN = 5V, VOUT = 1V Time (20 μs/Div) LPM Ramp Up (VPRIMCORE) LPM (5V/Div) PHASE (20V/Div) VVPRIMCORE (200mV/Div) VVPRIMCORE (200mV/Div) PGOOD (5V/Div) VIN = 12V, VCC = VEN = 5V, LPM = 0V 5V Time (100 μs/Div) Over-Voltage Protection No load, VIN = 12V, VCC = VEN = 5V, VOUT = 1V VOUT (1V/Div) PGOOD (5V/Div) LGATE (5V/Div)

DS6542A-01 September 2019 www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Application Information

The RT6542A is of a constant on-time PWM controller which provides four DC feedback voltages by controlling the G0 and G1 digital input. The constant on-time PWM control scheme handles wide input / output ratios with ease and provides 100ns “instant-on” response to load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The topology circumvents the poor load transient timing problems of fixed-frequency current mode PWMs, while avoiding the problems caused by widely varying switching frequencies in conventional constant on-time and constant off-time PWM schemes. The DRVTM mode PWM modulator is specifically designed to have better noise immunity for such a single output application. PWM Operation The Mach ResponseTM, DRVTM mode controller relies on the output filter capacitor's Effective Series Resistance (ESR) to act as a current sense resistor, so the output ripple voltage provides the PWM ramp signal. Referring to the function diagrams of the RT6542A, the synchronous high-side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the high- side MOSFET is turned off. The pulse width of this one shot is determined by the converter's input and output voltages to keep the frequency fairly constant over the input voltage range. Another one-shot sets a minimum off-time (400ns typ.) On-Time Control (tON) The on-time one-shot comparator has two inputs. One input monitors the output voltage, while the other input samples the input voltage and converts it to a current. This input voltage proportional current is used to charge an internal on-time capacitor. The on-time is the time required for the voltage on this capacitor to charge from zero volts to V OUT, thereby making the on-time of the high- side switch directly proportional to the output voltage and inversely proportional to the input voltage. The implementation results in a nearly constant switching frequency without the need of a clock generator. Diode-Emulation Mode The RT6542A automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly and without increasing V OUT ripple or load regulation. As the output current decreases from heavy load condition, the inductor current is also reduce d, and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. By emulating the behavior of diodes, the low-side MOSFET allows only partial negative current when the inductor freewheeling current becomes negative. As the load current is further decreased, it takes longer and longer to discharge the output capacitor to the level that is required for the next “ON” cycle. The on-time is kept the same as that in the heavy-load condition. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous condition. The transition load point to the light-load operation can be calculated as follows (Figure 1) : IN OUT LOAD ON (V V )It 2L  Figure 1. Boundary Condition of CCM/DCM

©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. VID Table Definition

0 X X 0

Current Limit section for a full description. pin from logic-high to logic-low. power consumption in standby or idle mode. (especially at low input voltage levels). G1/G0 pin and LPM pin as listed in Table1.

DS6542A-01 September 2019 www.richtek.com ©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Power Good Output (PGOOD) The power good output is an open-drain output and requires a pull-up resistor. When the feedback voltage is above 1.2V or below 0.3V, PGOOD will be pulled low. PGOOD is allowed to be high until soft-start ends and the output reaches 85% of its set voltage. There is a 3μs delay built into PGOOD circuitry to prevent false transition. When G0 or G1 changes, PGOOD remains in its present state for 32 clock cycles. Meanwhile, V OUT or VFB regulates to the new level. POR , UVLO and Soft-Start Power On Reset (POR) occurs when VCC rises above 4.2V (typ). After POR is triggered, the RT6542A will reset the fault latch and prepare the PWM for operation. Below 3.6V (typ.), the VCC Under-Voltage Lockout (UVLO) circuitry inhibits switching by keeping UGATE and LGATE low. A built-in soft-start is used to prevent surge current from the power supply input after EN is enabled. It clamps the ramping of the internal reference voltage which is compared with the FB signal. The typical soft-start duration is 1.2ms. Over-Voltage Protection (OVP) The output voltage can be continuously monitored for over- voltage protection. When VFB exceeds 1.2V, over-voltage protection is triggered and the low-side MOSFET is latched on. This activates the low-side MOSFET to discharge the output capacitor. The RT6542A is latched once OVP is triggered and can only be released by VCC or EN power on reset. There is a 5μs delay built into the over-voltage protection circuit to prevent false transitions. Under-Voltage Protection (UVP) The output voltage can be continuously monitored for under- voltage protection. When V FB is less than 0.3V, under- voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. In order to remove the residual charge on the output capacitor during the under voltage period, if PHASE is greater than 1V, the LGATE is forced high until PHASE is lower than 1V. There is a 5μs delay built into the under-voltage protection circuit to prevent false transitions. During soft-start, the UVP blanking time is 3.4ms. Output Inductor Selection The switching frequency (on-time) and operating point (% ripple or LIR) determine the inductor value as follows : ON IN OUT LOAD(MAX) T( V V )L LIR I   where LIR is the ratio of peak-to-peak ripple current to the maximum average inductor current. Select a low pass inductor having the lowest possible DC resistance that fits in the allowed dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I PEAK) : PEAK LOAD(MAX) LOAD(MAX) LIRII I 2  Output Capacitor Selection The output filter capacitor must have ESR low enough to meet output ripple and load transient requirement. Also, the capacitance must be high enough to absorb the inductor energy going from a full load to no load condition without tripping the OVP circuit. For CPU core voltage converters and other applications where the output is subject to violent load transient, the output capacitor's size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance : PP LOAD(MAX) VESR I In non-CPU applications, the output capacitor's size depends on how much ESR is needed to maintain at an acceptable level of output voltage ripple : PP LOAD(MAX) VESR LIR I   Organic semiconductor capacitor(s) or special polymer capacitor(s) are recommended.

©Copyright 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. following guidelines should be strictly followed. short as possible to reduce stray inductance. the current limit resistor located at the device. handling (including the chip power ground connections). on the maximum power dissipation. Figure 7. Derating Curve of Maximum Power Dissipation

DS6542A-01 September 2019 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before p lacing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuit ry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Ric htek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by i mplication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Outline Dimension W-Type 14L DFN 3x2 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options Min. Max. Min. Max. 0.700 0.800 0.028 0.031 0.000 0.050 0.000 0.002 0.175 0.250 0.007 0.010 0.150 0.250 0.006 0.010 2.950 3.050 0.116 0.120 Option1 2.450 2.550 0.096 0.100 Option2 2.550 2.650 0.100 0.104 1.950 2.050 0.077 0.081 Option1 0.750 0.850 0.030 0.033 Option2 0.850 0.950 0.033 0.037 0.300 0.400 0.012 0.016L b D E e 0.400 0.016 Symbol Dimensions In Millimeters Dimensions In Inches A