RT6220 RICHTEK | Alldatasheet
Document overview
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Technical content
Features
4.5V to 23V Input Voltage Range Adjustable from 0.6V to 5V Output Range Up to 98% Duty for 2S Battery Application 500kHz Switching Frequency ACOT® Mode Performs Fast Transient Response 31mΩΩΩΩΩ of High-Side MOSFET 20mΩΩΩΩΩ of Low-Side MOSFET Supports MLCC Output Capacitors Internal Soft-Start (1.5ms typ) Built-in OVP/UVP/OCP Power Good Indicator
Applications
Laptop Computers Tablet PCs Networking Systems Servers Personal Video Recorders Flat Panel Television and Monitors Distributed Power Systems
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Package Type QUF : UQFN-16L 3x3 (FC) (U-Type) RT6220 Lead Plating System G : Green (Halogen Free and Pb Free) PWM Operation / VOUT Protection A : with DEM/Latch AH : with DEM/Hiccup BL : without DEM/Latch BH : without DEM/Hiccup RT6220 EN VIN BOOT VBYP SW VOUT VOUT PGOOD VCC VIN VSYS VCC CIN CB L COUT RPGOOD CVCC FB PGND AGND CEN Chip Enable CBYP RBYP RB
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin Configuration (TOP VIEW) UQFN-16L 3x3 (FC) PGND VIN PGOOD SW SW AGND EN VCC BOOT VBYP FBAGND VOUT AGND 3 4 5 6 7 14 13 12 11 10 16 8 SW SW Marking Information 6J=YM DNN 6J= : Product Code YMDNN : Date Code RT6220AHGQUF 7P=YM DNN 7P= : Product Code YMDNN : Date Code RT6220BLGQUF 7M=YM DNN 7M= : Product Code YMDNN : Date Code RT6220BHGQUF 7N=YM DNN 7N= : Product Code YMDNN : Date Code RT6220AGQUF
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 VIN Power input connect to high-side MOSFET drain. Place 2pcs 10 F MLCC decoupling capacitors near input pin. 2 PGND Power ground. Connect power ground pin with wide and thick trace, adding thermal vias for better heat dissipation.
3 VBYP
Switch over input supply voltage for VCC. A low pass filter should be connected to AGND if VBYP is applied, the recommended RC filter value is RBYP = 5.1 and CBYP = 2.2F. If VBYP is not used, then connect this pin to AGND. Do not connect to VCC pin.
4 PGOOD
This pin should be connected to a pull high voltage with a 100k resistor. Recommend to pull high by VCC (5V). DO NOT pull high to external voltage which is higher than VCC (5V). 5, 6, 14 AGND Analog ground. 7 VOUT Output voltage sense input. An internal discharging circuit is connected to this pin. 8, 9, 15, 16 SW Switch node.
10 BOOT
Bootstrap supply for high-side gate driver. A capacitor is needed to drive the power switch's gate above the supply voltage. It is connected between the SW and BOOT pins to form a floating supply across the power switch driver. Recommended design value is R BOOT = 2.2 and CBOOT = 0.1F. 11 VCC 5V linear regulator output for internal control circuit. Bypass VCC to AGND with a 2.2F capacitor. VCC can only supply internal circuits. Do not connect to external loads. 12 FB Feedback voltage input. 13 EN Enable control input. Do not leave this pin floating. The slew rate of EN is recommended to be slower than 4.8V/s. User should add a RC circuit to avoid glitch noise.
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Operation Overall The RT6220 is a synchronous step-down converter with advanced constant on-time control mode. Using the ACOT® control mode can reduce the output capacitance and provide fast transient response. It can minimize the component size without additional external compensation network. Internal VCC Regulator The regulator provides 5V power to supply the internal control circuit. Connecting a 2.2μF ceramic capacitor for decoupling and stability is required. Soft-Start In order to prevent the converter output voltage from overshooting during the startup period, the soft-start function is necessary. The soft-start time is internal setting and the duration is around 1.5ms. OCP The inductor valley current is monitored cycle-by-cycle via the internal switches, preventing an on-time until the current drops below the current limit. Power Good After soft-start is finished, the power good output goes high. The PGOOD pin is an open-drain output. VCC Switch-Over The internal regulator output will switch over to VBYP if VBYP level is higher than 4.6V. Power Off There is an internal discharging circuit to discharge the residual charge of output capacitor when converter is power off. POR & Reference VOUT VCC On-Time One shot EN VBYP SW Gate Control Logic Fault Logic PGND VIN BOOT PGOOD AGND Min off Time Soft-Start OCP SW UVP58% x VREF POK OVP 91.5% x VREF 125% x VREF VREF VFB VCC VCC Switch-Over VCC VOC VCC VIN FB VCC Regulator
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Supply Current Shutdown Current V EN = 0V -- 2.5 5 A Quiescent Current VEN = 2V, no switching (RT6220A/AH) -- 100 130 A (RT6220BL/BH) -- 110 150 BOOT to SW Leakage Current BOOT to SW Leakage Current V BYP = 5V, VEN = 0V -- -- 2.5 A Switch On-Resistance Switch On-Resistance RDS(ON)_H V BOOT – VSW = 5V -- 31 -- m RDS(ON)_L -- 20 -- High Side MOSFET Leakage Current ILeakage_H V IN = 12V, VEN = 0V -- -- 1 A
Electrical Characteristics
(VIN = 12V, TA = 25 °C, unless otherwise specified) Absolute Maximum Ratings (Note 1) SW to PGND BOOT to PGND Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Current Limit Current Limit I OC Valley current of low-side switch 7.6 -- 11.4 A Switching Frequency and Minimum Off Timer Switching Frequency f SW 450 500 550 kHz Minimum Off-Time t OFF_MIN -- 200 -- ns Protections OVP Trip Threshold V OVP With respect to output voltage 120 125 130 % OVP Propagation Delay T OVPDLY -- 5 -- s UVP Trip Threshold V UVP With respect to output voltage 53 58 63 % UVP Propagation Delay T UVPDLY -- 5 -- s Reference and Soft-Start Feedback Reference Voltage VREF 0.594 0.600 0.606 V Soft-Start Time T SS From EN high to PGOOD high 1 1.5 2 ms Enable and UVLO EN Input High Voltage V ENH 1.25 1.35 1.45 V EN Hysteresis V ENHYS 50 200 250 mV EN Input Current I EN VEN = 2V -- 1 -- VEN = 0V -- 0 -- VCC UVLO Rising V CCUVLO 3.8 4.2 4.45 V VCC UVLO Hysteresis V CCHYS 75 400 650 mV VCC Regulator VCC Regulator V VCC 4.805 5 5.295 V VCC Switch Over Threshold to VBYP V BYP rising edge 4.4 4.6 4.8 V VCC Switch Over Hysteresis 150 200 400 mV Switch Over On-Resistance -- 3 5 Power Good Indicator PGOOD Threshold From Lower V OUT rising 86.5 91.5 96.5 % PGOOD Low Hysteresis V OUT falling -- 10 -- % PGOOD Low to High Delay TPGDLY -- 0.5 -- ms PGOOD Sink Current Capability VPGSINK Sink 4mA -- -- 0.4 V PGOOD Leakage Current IPGLEAK V PGOOD = 5V -- -- 100 nA
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25°C on a high effective thermal conductivity four-layer Richtek test board. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Shutdown Thermal Shutdown Threshold T SD T J rising 135 150 -- °C Thermal Shutdown Hysteresis -- 25 -- °C
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Switching Frequency vs. Load Current 100 200 300 400 500 600 0.001 0.01 0.1 1 10 Load Current (A) Switching Frequency (kHz) 1 VIN = 12V, VOUT = 1V, EN = 2V Switching Frequency vs. Load Current 100 200 300 400 500 600 0.001 0.01 0.1 1 10 Load Current (A) Switching Frequency (kHz) 1 VIN = 19V, VOUT = 1V, EN = 2V Switching Frequency vs. Load Current 100 200 300 400 500 600 0.001 0.01 0.1 1 10 Load Current (A) Switching Frequency (kHz) 1 VIN = 7.4V, VOUT = 1V, EN = 2V Efficiency vs. Load Current 100 0.001 0.01 0.1 1 10 Load Current (A) Efficiency (%) VOUT = 1V, fSW = 500kHz, L = 1μH, DCR = 3.3mΩ, EN = 2V VIN = 7.4V VIN = 12V VIN = 19V Efficiency vs. Load Current 100 0.001 0.01 0.1 1 10 Load Current (A) Efficiency (%) VOUT = 3.3V, fSW = 500kHz, L = 2.2μH, DCR = 7mΩ, EN = 2V VIN = 7.4V VIN = 12V VIN = 19V Efficiency vs. Load Current 100 0.001 0.01 0.1 1 10 Load Current (A) Efficiency (%) VBYP = VOUT = 5V, fSW = 500kHz, L = 2.2μH, DCR = 7mΩ, EN = 2V VIN = 7.4V VIN = 12V VIN = 19V Performance waveforms are tested on the evaluation board of the Typical Application Circuit, V IN = 12V, VOUT = 1V, L = 1μH, TJ = 25 °C, unless otherwise noted.
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Output Voltage vs. Load Current 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25 0.001 0.01 0.1 1 10 Load Current (A) Output Voltage (V) VIN = 12V, VOUT = 5V, EN = 2V Output Voltage vs. Load Current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0.001 0.01 0.1 1 10 Load Current (A) Output Voltage (V) VIN = 12V, VOUT = 1V, EN = 2V Output Voltage vs. Load Current 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 0.001 0.01 0.1 1 10 Load Current (A) Output Voltage (V) VIN = 12V, VOUT = 3.3V, EN = 2V Quiescent Current vs. Input Voltage 100 105 110 5 7 9 1 11 31 51 71 92 12 3 Input Voltage (V) Quiescent Current (μA) EN = 2V, No Switching Shutdown Current vs. Input Voltage 5 7 9 1 11 31 51 71 92 12 3 Input Voltage (V) Shutdown Current (μA) 1 EN = 0V Time (500 μs/Div) Power On Through EN PGOOD (5V/Div) No Load, VIN = 12V VOUT (1V/Div) EN (5V/Div) VCC (5V/Div)
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (50 μs/Div) UVP VIN = 12V, EN = High SW (10V/Div) VOUT (1V/Div) PGOOD (5V/Div) Time (50 μs/Div) OVP IL (5A/Div) VIN = 12V, VOUT = 1.25V, EN = High VOUT (1V/Div) PGOOD (5V/Div) VIN (10V/Div) VIN = 12V, EN = High, VOUT = 1V, COUT = 4 x 22μF, Time (50 μs/Div) Load Transient Response SW (20V/Div) IL (5A/Div) VOUT (20mV/Div) L = 1.2μH, IOUT = 0.6A to 6A @ 2.5A/μs No Load, VIN = 12V Time (500 μs/Div) Power Off Through EN PGOOD (5V/Div) VOUT (1V/Div) EN (5V/Div) VCC (5V/Div) Time (50 μs/Div) Load Transient Response SW (20V/Div) IL (5A/Div) VOUT (200mV/Div) VIN = 12V, EN = High, VOUT = 5V, COUT = 3 x 22μF, L = 2.2μH, IOUT = 0.6A to 6A @ 2.5A/μs Time (50 μs/Div) Load Transient Response SW (20V/Div) IL (5A/Div) VOUT (100mV/Div) VIN = 12V, EN = High, VOUT = 3.3V, COUT = 3 x 22μF, L = 2.2μH, IOUT = 0.6A to 6A @ 2.5A/μs
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The RT6220 is high-performance 500kHz 6A step-down regulators with internal power switches and synchronous rectifiers. It features an Advanced Constant On-Time (ACOT ® ) control architecture that provides stable operation for ceramic output capacitors without complicated external compensation, among other benefits. The input voltage range is from 4.5V to 23V, and the output voltage is adjustable from 0.6V to 5V. The proprietary ACOT ® control scheme improves conventional constant on-time architectures, achieving nearly constant switching frequency over line, load, and output voltage ranges. Since there is no internal clock, response to transients is nearly instantaneous and inductor current can ramp quickly to maintain output regulation without large bulk output capacitance. ACOT ® Control Architecture In order to achieve good stability with low-ESR ceramic capacitors, ACOT® uses a virtual inductor current ramp generated inside the IC. This internal ramp signal replaces the ESR ramp normally provided by the output capacitor's ESR. The ramp signal and other internal compensations are optimized for low-ESR ceramic output capacitors. Making the on-time proportional to V OUT and inversely proportional to V IN is not sufficient to achieve good constant-frequency behavior for several reasons. First, voltage drops across the MOSFET switches and inductor cause the effective input voltage to be less than the measured input voltage and the effective output voltage to be greater than the measured output voltage as sensing input and output voltage. When the load changes, the switch voltage drops change causing a switching frequency variation with load current. Also, at light loads if the inductor current goes negative, the switch dead- time between the synchronous rectifier turn-off and the high-side switch turn-on allows the switching node to rise to the input voltage. This increases the effective on-time and causes the switching frequency to drop noticeably. One way to reduce these effects is to measure the actual switching frequency and compare it to the desired range. This has the added benefit eliminating the need to sense the actual output voltage, potentially saving one pin connection. The ACOT ® uses this method, measuring the actual switching frequency and modifying the on-time with a feedback loop to keep the average switching frequency in the desired range. ACOT ® One-shot Operation The RT6220 control algorithm is simple to understand. The feedback voltage, with the virtual inductor current ramp added, is compared to the reference voltage. When the combined signal is less than the reference, the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. The on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. After the on- time, the high-side switch is turned off and the synchronous rectifier is turned on and the inductor current ramps down linearly. At the same time, the minimum off-time one-shot is triggered to prevent another immediate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. The minimum off-time is kept short (200ns typical) so that rapidly-repeated on- times can raise the inductor current quickly when needed. Diode Emulation Mode (DEM) In diode emulation mode, the RT6220 automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly. As the output current decreases from heavy load conditions, the inductor current is also reduced, and eventually comes to the point that its current valley touches zero, which is the boundary between continuous conduction and discontinuous conduction modes. To emulate the behavior of diodes, the low-side MOSFET allows only partial negative current to flow when the inductor free wheeling current becomes negative. As the load current is further decreased, it takes longer and longer time to discharge the output capacitor to the level that requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. when input voltage drops below the UVLO-falling threshold. The IC resumes switching when input voltage exceeds the UVLO-rising threshold. Over-Temperature Protection The RT6220 features an Over-Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP shuts down switching operation when the junction temperature exceeds 150°C. Once the junction temperature cools down by approximately 25°C the IC resumes normal operation with a complete soft-start. For continuous operation, provide adequate cooling so that the junction temperature does not exceed 150°C. Note that the VCC regulator remains on as the OTP is triggered. Enable and Disable The enable input (EN) has a logic-low level of 1.15V. When V EN is below this level, the IC enters shutdown mode and supply current drops to less than 5μA (typical). Besides, the switch-over switch is turned off and VCC LDO is also powered off. When V EN exceeds its logic-high level (1.35V typical), the IC is fully operational. Soft-Start The RT6220 provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. The soft-start (SS) automatically begins once the chip is enabled. During soft- start, it clamps the ramp of internal reference voltage which is compared with FB signal. And it will correct the output voltage more accurately after soft-start. The typical soft- start duration is 1.5ms. Power Off When V EN is pulled to GND or lower than the logic-low level of 1.15V, there is an internal discharging resistor to discharge the residual charge inside the output capacitors. Besides, the value of discharging resistor is about twenty ohms. Power Good Output (PGOOD) The power good output is an open-drain output that requires a pull-up resistor. When the output voltage is 20% (typical) below its set voltage, PGOOD will be pulled low. It is held low until the output voltage returns to 90% of its set voltage once more. During soft-start, PGOOD is actively held low and only allowed to be pulled high after soft-start is over and the output reaches 90% of its set voltage and the PGOOD low to high delay(500 μs typical) has passed. There is a 2μs PGOOD high to low delay built into PGOOD circuitry to prevent false triggering. In addition, the PGOOD open drain driver is supplied by VCC power source or VBYP pin voltage source in switch- over mode. When converter is powered off by EN low signal, the pull-low strength of PGOOD open drain driver decreases after VCC voltage is lower than VCC_POR threshold (typ. = 3.8V). As a result, the PGOOD pin is floated and pulled up by external voltage source. In consideration of PGOOD status after EN power off, it is recommended that connecting PGOOD pin with a 100k Ω resistor to VCC (5V). DO NOT pull high to external voltage which is higher than VCC (5V). External Bootstrap Capacitor (C BOOT) Connect a 0.1μF low ESR ceramic capacitor between the BOOT and SW pins. This bootstrap capacitor provides the gate driver supply voltage for the high-side N-MOSFET switch. The internal power MOSFET switch gate driver is optimized to turn the switch on fast enough for low power loss and good efficiency, and slow enough to reduce EMI. Switch turn-on is when most EMI occurs since V SW rises rapidly. During switch turn-off, SW is discharged relatively slowly by the inductor current during the dead-time between high-side and low-side switch on-times. In some cases it is desirable to reduce EMI further, at the expense of some additional power dissipation. The switch turn-on can be slowed by placing a small (<10 Ω) resistance between BOOT and the external bootstrap capacitor. This will slow the high-side switch turn-on and V SW's rise. Setting the Output Voltage The output voltage of the RT6220 is adjustable and with valley control. There is an easy way to determine the output voltage only by two resistors, R1 and R2. As the feedback circuit shown in Figure 5. the relation of V OUT and VREF can be derived as V OUT = (1+R1/R2) x V REF readily.
©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. lead at switching frequency. value is related to the output voltage ripple and CFF. Figure 5. The Equivalent Circuit of Feedback Loop best mix of cost, physical size, and circuit efficiency. and they can improve the circuit's transient response. and estimating a ΔIL as some percentage of that current. unnecessary for most applications. resistance that meets the cost and size requirements. capacitance variation and more temperature stability. the maximum input voltage is a conservatively safe design.
DS6220-11 July 2020www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. The amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle. The maximum duty cycle during a fast transient is a function of the on-time and the minimum off-time since the ACOT® control scheme will ramp the current using on-times spaced apart with minimum off-times, which is as fast as allowed. Calculate the approximate on-time (neglecting parasitics) and maximum duty cycle for a given input and output voltage as : ESR_STEP OUT ESRVI R OUT ONON MAX IN SW ON OFF_MIN Vtt a n d DVf t + t The actual on-time will be slightly longer as the IC compensates for voltage drops in the circuit, but we can neglect both of these since the on-time increases compensations for the voltage losses. Calculate the output voltage sag as : OUTSAG OUT IN(MIN) MAX OUT LIV 2C V D V The amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage : () 2 OUTSOAR OUT OUT LIV 2C V Most applications never experience instantaneous full load steps and the RT6220's high switching frequency and fast transient response can easily control voltage regulation at all times. Therefore, sag and soar are seldom an issue except in very low-voltage CPU core or DDR memory supply applications, particularly for devices with high clock frequencies and quick changes into and out of sleep modes. In such applications, simply increasing the amount In addition to voltage ripple at the switching frequency, the output capacitor and its ESR also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. The ACOT® transient response is very quick and output transients are usually small. However, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and OUT IN OUTIN IN SW OUT IN IV VV( 1 )Cf V V The typical operating circuit is recommended to use two 10μF low ESR ceramic capacitors on the input. Output Capacitor Selection The RT6220 is optimized for ceramic output capacitors and best performance will be obtained by using them. The total output capacitance value is usually determined by the desired output voltage ripple level and transient response requirements for sag (undershoot on positive load steps) and soar (overshoot on negative load steps). Output ripple at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's ESR and stored charge. These two ripple components are called ESR ripple and capacitive ripple. Since ceramic capacitors have extremely low ESR and relatively little capacitance, both components are similar in amplitude and both should be considered if ripple is critical. RIPPLE RIPPLE(ESR) RIPPLE(C) RIPPLE(ESR) L ESR LRIPPLE(C) OUT SW VV V VI R IV 8C f value determines the input ripple voltage of the regulator. The input voltage ripple can be approximately calculated using the following equation : 2OUT OUT LRMS OUT IN IN VV II( 1 ) I VV 1 2 The next step is to select a proper capacitor for RMS current rating. One good design uses more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank. The input capacitance current, which can be calculated using the following equation : low duty cycle applications (which require high inductance to get reasonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. Typically, load changes occur slowly with respect to the IC's 500kHz switching frequency. However, some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worst-case voltage swings in response to very fast load steps. The amplitude of the ESR step up or down is a function of the load step and the ESR of the output capacitor :
©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. protection and under-voltage protection will not be triggered. on the maximum power dissipation. Figure 6. Derating Curve of Maximum Power Dissipation and contribute to converter instability with improper layout. plane for heat sinking and noise protection. and the switching node (SW).
©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 7. PCB Layout Guide Thickness(oz) = Layer Cu thickness. Impedance between PGND and AGND should be as small as possible for unified ground voltage.
DS6220-11 July 2020 www.richtek.com ©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension U-Type 16L QFN 3x3 (FC) Package Min Max Min Max A 0.500 0.600 0.020 0.024 A1 0.000 0.050 0.000 0.002 A3 0.100 0.200 0.004 0.008 D 2.900 3.100 0.114 0.122 E 2.900 3.100 0.114 0.122 b 0.150 0.250 0.006 0.010 b1 0.100 0.200 0.004 0.008 L 0.350 0.450 0.014 0.018 L1 0.750 0.850 0.030 0.033 L2 0.550 0.650 0.022 0.026 e K 0.975 0.038 1.675 0.066 0.053 1.675 0.066 1.935 0.076 1.335 Symbol Dimensions In Millimeters Dimensions In Inches 0.400 0.016 0.975 0.038
DS6220-11 July 2020www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries.