RT6217A RICHTEK | Alldatasheet
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Technical content
Features
3A Converter With Built-in 85mΩΩΩΩΩ/40mΩΩΩΩΩ Low RDS(ON) Power FETs Input Supply Voltage Range : 4.5V to 24V Output Voltage Range : 0.791V to 6V Advanced Constant On-Time (ACOTTM) Control Ultrafast Transient Response No Needs For External Compensations Optimized for Low-ESR Ceramic Output Capacitors 0.791V ±±±±±1.5% High-Accuracy Feedback Reference Voltage Low Quiescent Current (150μμμμμA typ.) Both HS/LS FETs Protection for Robust Over-Current Protection Optional for Operation Modes : Power Saving Mode (PSM) at Light Load (RT6217A) Forced PWM Mode (RT6217B) Light-load V OUT Ripple Reduction Technology in PSM Fixed Switching Frequency : 500kHz Externally Adjustable Soft-Start Monotonic Start-up for Pre-biased Output Input Under-Voltage Lockout (UVLO) Output Under-Voltage Protection (UVP) with Hiccup Mode Power Good Indication Available In TSOT-23-8 (FC) Package Simplified Application Circuit General Description The RT6217A/B is a simple, easy-to-use, 3A synchronous step-down DC-DC converter with an input supply voltage range of 4.5V to 24V. The device build-in an accurate 0.791V reference voltage and integrates low R DS(ON) power MOSFETs to achieve high efficiency in a TSOT-23-8 (FC) package. The RT6217A/B adopts Advanced Constant On-Time (ACOT TM) control architecture to provide an ultrafast transient response with few external components and to operate in nearly constant switching frequency over the line, load, and output voltage range. The RT6217A operates in automatic PSM that maintains high efficiency during light load operation. The RT6217B operates in Forced PWM that helps meet tight voltage regulation accuracy requirements. The RT6217A/B senses both FETs current for a robust over-current protection. It features cycle-by-cycle current limit protection and prevent the device from the catastrophic damage in output short circuit, over current or inductor saturation. An externally adjustable soft-start function prevents inrush current during start-up. The device also includes input under-voltage lockout, output under-voltage protection, and over-temperature protection (thermal shutdown) to provide safe and smooth operation in all operating conditions. The RT6217A/B is offered in a TSOT- 23-8(FC) package. COUT RT6217A/B EN VIN BOOT PGOOD SW VOUT GND VIN L CBOOT FB CFF Enable SS CSS RPGOOD VPGOOD CIN
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin No. Pin Name Pin Function 1 PGOOD Open-drain power-good indication output. Once being started-up, PGOOD will be pulled low to GND if any internal protection is triggered. 2 VIN Power input. The input voltage range is from 4.5V to 24V. Connect a suitable input capacitor between this pin and GND, with a typical capacitance of 22F. 3 SW Switch node between the internal switch and the synchronous rectifier. Connect this pin to the inductor and bootstrap capacitor. 4 GND Power ground. 5 BOOT Bootstrap capacitor connection node to supply the high-side gate driver. Connect a 0.1F ceramic capacitor between this pin and SW pin. 6 EN Enable control input. A logic-high enables the converter; a logic-low forces the device into shutdown mode. 7 SS Soft-start capacitor connection node. Connect an external capacitor between this pin and ground to set the soft-start time. Do not leave this pin unconnected. A capacitor of 2.8nF to 100nF is suggested. 8 FB Feedback voltage input. Connect this pin to the midpoint of the external feedback resistive divider to set the output voltage of the converter to the desired regulation level. The device regulates the FB voltage at Feedback Threshold Voltage, typically 0.791V. Functional Pin Description Marking Information Pin Configuration (TOP VIEW) TSOT-23-8 (FC) PGOOD SW GND FB EN BOOT VIN SS Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes.
Ordering Information
J8F : TSOT-23-8 (FC) Lead Plating System G : Green (Halogen Free and Pb Free) UVP Option H : Hiccup PSM/PWM A : PSM/PWM B : Forced PWM 0T=DNN RT6217AHGJ8F 0U=DNN 0U= : Product Code DNN : Date Code RT6217BHGJ8F 0T= : Product Code DNN : Date Code
Applications
Set Top Box Portable TV Access Point Router DSL Modem LCD TV
DS6217A/B-00 January 2018 www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Operation The RT6217A/B is a high-efficiency, synchronous step- down DC-DC converter that can deliver up to 3A output current from a 4.5V to 24V input supply. The RT6217A/B adopts ACOT TM control mode, which can reduce the output capacitance and provide ultrafast transient responses, and allow minimal components sizes without any additional external compensation network. Enable Control The RT6217A/B provides an EN pin, as an external chip enable control, to enable or disable the device. If V EN is held below a logic-low threshold voltage (VENH − ΔVEN) of the enable input (EN), the converter will enter into shutdown mode, that is, the converter is disabled and switching is inhibited even if the VIN voltage is above VIN under-voltage lockout threshold (V UVLO). During shutdown mode, the supply current can be reduced to ISHDN (10μA or below). If the EN voltage rises above the logic-high threshold voltage (V ENH) while the VIN voltage is higher than UVLO threshold (VUVLO), the device will be turned on, that is, switching being enabled and soft-start sequence being initiated. SW Reg Driver SW VCC VCC Control VIBIAS On Time Minoff OC VREF EN EN VINBOOT GND UV SW VIN GND PGOOD FB Ripple Gen.SW Soft- Start Control SS Comparator UGATE LGATE VIN Input Under-Voltage Lockout In addition to the EN pin, the RT6217A/B also provides enable control through the VIN pin. It features an under- voltage lockout (UVLO) function that monitors the internal linear regulator (VCC). If V EN rises above V ENH first, switching will still be inhibited until the VIN voltage rises above V UVLO. It is to ensure that the internal regulator is ready so that operation with not- fully-enhanced internal MOSFET switches can be prevented. After the device is powered up, if the input voltage V IN goes below the UVLO- falling threshold voltage (VUVLO − ΔVUVLO), this switching will be inhibited; if V IN rises above the UVLO-rising threshold (VUVLO), the device will resume switching. Low-Side Current Limit Protection The RT6217A/B features cycle-by-cycle valley-type current limit protection, measuring the inductor current through the synchronous rectifier (low-side switch). The inductor current level is determined by measuring the low- side switch voltage between the SW pin and GND, which is proportional to the switch current, during the low-side on-time. For greater accuracy, temperature compensation is added to the voltage sensing. Once the current rises above the low-side switch valley current limit (I LIM_L), the
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. on-time one-shot will be inhibited until the inductor current ramps down to the current limit level (ILIM_L), that is, another on-time can only be triggered when the inductor current goes below the low-side current limit. This function can prevent the average output current from greatly exceeding the guaranteed low-side current limit value. If the output load current exceeds the available inductor current (clamped by the above-mentioned low-side current limit), the output capacitor needs to supply the extra current such that the output voltage will begin to drop. If it drops below the output under-voltage protection trip threshold, the IC will stop switching to avoid excessive heat. Output Under-Voltage Protection The RT6217A/B includes output under-voltage protection (UVP) against over-load or short-circuited condition by constantly monitoring the feedback voltage V FB. If V FB drops below the under-voltage protection trip threshold (typically 50% of the internal reference voltage), the UV comparator will go high to turn off both the internal high- side and low-side MOSFET switches. Hiccup Mode If the output under-voltage condition continues for a period of time, the RT6217A/B will enter output under-voltage protection with hiccup mode. When the protection function is triggered, the device will shut down for a period of time and then attempt to recover automatically by initiating a new soft-start sequence. Once the soft-start ends, the fault condition will determine the IC's operation. If the fault condition is removed, the converter will resume normal operation; otherwise, the cycle will be repeated until this fault condition is cleared. Hiccup mode allows the circuit to operate safely with low input current and power dissipation, and then resume normal operation as soon as the over-load or short-circuit condition is removed. Soft-Start (SS) The soft-start function is used to prevent large inrush currents while the converter is being powered up. The RT6217A/B provides an SS pin so that the soft-start time can be programmed by selecting the value of the external soft-start capacitor C SS connected from the SS pin to GND. During the start-up sequence, the soft-start capacitor is charged by an internal current source ISS (typically, 4μA) to generate a soft-start ramp voltage as a reference voltage to the PWM comparator. If the output is for some reasons pre-biased to a certain voltage during start-up, the device will initially the switching of both high-side and low-side switches. And only when this ramp voltage is greater than the feedback voltage V FB, the switching will be resumed. The output voltage can then ramp up smoothly to its targeted regulation voltage, and the converter can have a monotonic smooth start-up. For soft-start control, the SS pin should never be left unconnected. Power Good Indication The RT6217A/B provides a power-good (PGOOD) open- drain output pin. It is to be connected to an external voltage source through a pull-up resistor. The power-good function is activated after soft-start is finished and is controlled by a comparator connected to the feedback signal V FB. If VFB raises above a power-good threshold (V TH_PGLH) (typically 95% of the target value), the PGOOD pin will be in high impedance and V PGOOD will be held high after a certain delay elapsed. When VFB drops by a power-good hysteresis (ΔVTH_PGLH) (typically 5% of the target value) or exceeds VTH_PGHL (typically 115% of the target value), the PGOOD pin will be pulled low. For VFB above VTH_PGHL, VPGOOD will be pulled high again when VFB drops back by a power-good hysteresis (ΔVTH_PGHL) (typically 5% of the target value). Once being started-up, if any internal protection is triggered, PGOOD will be pulled low to GND. External Bootstrap Capacitor Connect a 0.1μF low-ESR ceramic capacitor between the BOOT and SW pins. This bootstrap capacitor supplies for the gate driver of the high-side N-channel MOSFET switch. Over-Temperature Protection (Thermal Shutdown) The RT6217A/B includes an over-temperature protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when junction temperature exceeds a thermal shutdown threshold T SD. Once the junction temperature cools down by a thermal shutdown hysteresis (ΔTSD), the IC will resume normal operation with a complete soft-start.
DS6217A/B-00 January 2018 www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified) Absolute Maximum Ratings (Note 1) Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4) Parameter Symbol Test Conditions Min Typ Max Unit Supply Voltage VIN Supply Input Operating Voltage V IN 4.5 -- 24 V VIN Under-Voltage Lockout Threshold VUVLO V IN Rising 3.7 3.9 4.1 V VIN Under-Voltage Lockout Threshold-Hysteresis VUVLO -- 350 -- mV Supply Current Shutdown Current I SHDN V EN = 0V -- -- 10 A Quiescent Current I Q VEN = 2V, VFB = 1V, VSS = 0V (not switching) -- 150 250 A Soft-Start Soft-Start Current I SS -- 4 -- A Enable Voltage EN Rising Threshold V ENH 1.2 1.4 1.6 V EN Hysteresis VEN 80 150 220 mV
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the lead of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Feedback Voltage Feedback Threshold Voltage V TH_FB 779 791 803 mV Internal MOSFET High-Side Switch On-Resistance R DS(ON)_H V BOOTVSW = 4.8V -- 85 -- m Low-Side Switch On-Resistance R DS(ON)_L -- 40 -- m Current Limit Low-Side Switch Valley Current Limit I LIM_L 3.3 4.2 4.9 A High-Side Switch Peak Current Limit I LIM_H -- 5.5 -- A Switching Frequency Switching Frequency f SW -- 500 -- kHz On-Time Timer Control Maximum Duty Cycle D MAX -- 90 -- % Minimum On-Time t ON_MIN -- 60 -- ns Thermal Shutdown Thermal Shutdown Threshold T SD -- 160 -- C Thermal Shutdown Hysteresis TSD -- 25 -- C Output Under Voltage Protections UVP Trip Threshold UVP detect -- 50 -- % Hysteresis -- 10 -- % Power Good Power-Good High Threshold V TH_PGLH V FB rising. PGOOD goes High. -- 95 -- % Power-Good High Hysteresis VTH_PGLH V FB falling. PGOOD goes Low. -- 5 -- % Power-Good Low Threshold V TH_PGHL V FB rising. PGOOD goes Low. -- 115 -- % Power-Good Low Hysteresis VTH_PGHL V FB falling. PGOOD goes High. -- 5 -- %
©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. Suggested Component Values
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Time (2 μs/Div) Output Ripple Voltage VOUT (20mV/Div) VSW (5V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 3A, L = 1.5μH Output Voltage vs. Output Current 0.95 1.00 1.05 1.10 1.15 1.20 00 . 511 . 522 . 53 Output Current (A) Output Voltage (V) VOUT = 1.05V VIN = 24V VIN = 19V VIN = 12V VIN = 4.5V Output Voltage vs. Temperature 1.02 1.03 1.04 1.05 1.06 1.07 1.08 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 12V VIN = 24V VIN = 4.5V VOUT = 1.05V, IOUT = 1.2A Output Voltage vs. Temperature 4.90 4.94 4.98 5.02 5.06 5.10 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 24V VIN = 12V VIN = 7V VOUT = 5V, IOUT = 1.2A Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VOUT = 1.05V VIN = 4.5V VIN = 12V VIN = 19V VIN = 24V Time (100 μs/Div) Load Transient Response VOUT (20mV/Div) IOUT (1A/Div) VIN = 12V, VOUT = 1.05V, IOUT = 1.5A to 3A, L = 1.5μH
DS6217A/B-00 January 2018 www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (10ms/Div) Power Off from VIN VOUT (1V/Div) VSW (10V/Div) IOUT (2A/Div) VIN (10V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 3A, L = 1.5μH Time (10ms/Div) Power On from VIN VOUT (1V/Div) VSW (10V/Div) IOUT (2A/Div) VIN (10V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 3A, L = 1.5μH Time (5ms/Div) Power On from EN VOUT (1V/Div) VSW (10V/Div) IOUT (2A/Div) VEN (2V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 3A, L = 1.5μH Time (200 μs/Div) Power Off from EN VOUT (1V/Div) VSW (10V/Div) IOUT (2A/Div) VEN (2V/Div) VIN = 12V, VOUT = 1.05V, IOUT = 3A, L = 1.5μH
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The output stage of a synchronous buck converter is composed of an inductor and capacitor, which stores and delivers energy to the load, and forms a second-order low- pass filter to smooth out the switch node voltage to maintain a regulated output voltage. Inductor Selection When designing the output stage of the synchronous buck converter, it is recommended to start with the inductor. However, it may require several iterations because the exact inductor value is generally flexible and is optimized for low cost, small form factor, and high overall performance of the converter. Further, inductors vary with manufacturers in both material and value, and typically have a tolerance of ±20%. Three key inductor parameters to be specified for operation with the device are inductance (L), inductor saturation current (I SAT), and DC resistance (DCR), which affects performance of the output stage. An inductor with lower DCR is recommended for applications of higher peak current or load current, and it can improve system performance. Lower inductor values are beneficial to the system in physical size, cost, DCR, and transient response, but they will cause higher inductor peak current and output voltage ripple to decrease system efficiency. Conversely, higher inductor values can increase system efficiency at the expense of larger physical size, slower transient response due to the longer response time of the inductor. A good compromise among size, efficiency, and transient response can be achieved by setting an inductor current ripple (ΔI L) of about 20% to 50% of the desired full output load current. To meet the inductor current ripple (ΔI L) requirements, a minimum inductance must be chosen and the approximate inductance can be calculated by the selected input voltage, output voltage, switching frequency SW), and inductor current ripple (ΔIL), as below : OUT IN OUT IN SW L VV VL = Vf I Once the inductance is chosen, the inductor ripple current (ΔIL) and peak inductor current (IL_PEAK) can be calculated, as below : OUT IN OUT L IN SW L_PEAK OUT_MAX L L_VALLY OUT_MAX L VV VI= Vf L 1I = I I 2 1I = I I 2 where IOUT_MAX is the maximum rated output current or the required peak current. The inductor must be selected to have a saturation current and thermal rating which exceed the required peak inductor current I L_PEAK. For a robust design to maintain control of inductor current in overload or short-circuit conditions, some applications may desire inductor saturation current rating up to the high-side switch current limit of the device. However, the built-in output under-voltage protection (UVP) feature makes this unnecessary for most applications. I L_PEAK should not exceed the minimum value of the device's high-side switch current limit because the device will not be able to supply the desired output current. By reducing the inductor current ripple (ΔI L) to increase the average inductor current (and the output current), IL_PEAK can be lowered to meet the device current limit requirement. For best efficiency, a low-loss inductor having the lowest possible DCR that still fits in the allotted dimensions will be chosen. Ferrite cores are often the best choice. However, a shielded inductor, possibly larger or more expensive, will probably give fewer EMI and other noise problems. The following design example is illustrated to walk through the steps to apply the equations defined above. The RT6217A/B's Typical Application Circuit for output voltage of 1.05V at maximum output current of 3A and an input voltage of 12V with inductor current ripple of 1.5A (i.e. 50%, in the recommended range of 20% to 50%, of the maximum rated output current) is taken as the design example. The approximate minimum inductor value can first be calculated as below : 1.05 12 1.05L = = 1.28 μH12 500kHz 1.5A
DS6217A/B-00 January 2018 www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. where fSW is 500kHz. The inductor current ripple will be set at 1.5A, as long as the calculated inductance of 1.28μH is used. However, the inductor of the exact inductance value may not be readily available, and therefore an inductor of a nearby value will be chosen. In this case, 1.5 μH inductance is available and actually used in the Typical Application Circuit. The actual inductor current ripple (ΔI and required peak inductor current (I L_PEAK) can be calculated as below : L 1.05 12 1.05I = = 1.28A12 500kHz 1.5 μH L_PEAK OUT_MAX L 11 . 2 8I = I I = 3 + = 3.64A 22 For the 1.5μH inductance value, the inductor saturation current and thermal rating should exceed 3.64A. Input Capacitor Selection Input capacitors are needed to smooth out the RMS ripple current (I RMS) imposed by the switching currents and drawn from the input power source, by reducing the ripple voltage amplitude seen at the input of the converters. The voltage rating of the input filter capacitors must be greater than the maximum input voltage. It's also important to consider the ripple current capabilities of capacitors. The RMS ripple current (I RMS) of the regulator can be determined by the input voltage (V IN), output voltage (VOUT), and rated output current (I OUT) as the following equation : OUT INRMS OUT IN OUT V VI = I 1 VV From the above, the maximum RMS input ripple current occurs at maximum output load, which will be used as the requirements to consider the current capabilities of the input capacitors. Furthermore, for a single phase buck converter, the duty cycle is approximately the ratio of output voltage to input voltage. The maximum ripple voltage usually occurs at 50% duty cycle, that is, V IN = 2 x VOUT. The maximum IRMS, as IRMS (Max), can be approximated as 0.5 x IOUT_MAX, where IOUT_MAX is the maximum rated output current. Besides, the variation of the capacitance value with temperature, DC bias voltage, switching frequency, and allowable peal-to-peak ripple voltage that reflects back to the input, also need to be taken into consideration. For example, the capacitance value of a capacitor decreases as the DC bias across the capacitor increases; also, higher switching frequency allows the use of input capacitors of smaller capacitance values. Ceramic capacitors are most commonly used to be placed right at the input of the converter to reduce ripple voltage amplitude because only ceramic capacitors have extremely low ESR which is required to reduce the ripple voltage. Note that the capacitors need to be placed as close as to the input pins as possible for highest effectiveness. Ceramic capacitors are preferred also due to their low cost, small size, high RMS current ratings, robust inrush surge current capabilities, and low parasitic inductance, which helps reduce the high-frequency ringing on the input supply. However, care must be taken when ceramic capacitors are used at the input, and the input power is supplied by a wall adapter, connected through a long and thin wire. When a load step occurs at the output, a sudden inrush current will surge through the long inductive wire, which can induce ringing at the device's power input and potentially cause a very large voltage spike at the VIN pin to damage the device. For applications where the input power is located far from the device input, it may be required that the low-ESR ceramic input capacitors be placed in parallel with a bulk capacitor of other types, such as tantalum, electrolytic, or polymer, to dampen the voltage ringing and overshoot at the input, caused by the long input power path and input ceramic capacitor. It is suggested to choose capacitors with higher temperature ratings than required. Several ceramic capacitors may be parallel to meet application requirements, such as the RMS current, size, and height. The Typical Application Circuit can use one 22μF, or two 10μF and one high-frequency- noise-filtering 0.1μF low- ESR ceramic capacitors at the input.
DS6217A/B-00 January 2018www.richtek.com ©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Output Capacitor Selection Output capacitance affects the output voltage of the converter, the response time of the output feedback loop, and the requirements for output voltage sag and soar. The sag occurs after a sudden load step current applied, and the soar occurs after a sudden load removal. Increasing the output capacitance reduces the output voltage ripple and output sag and soar, while it increases the response time that the output voltage feedback loop takes to respond to step loads, Therefore, there is a tradeoff between output capacitance and output response. It is recommended to choose a minimum output capacitance to meet the output voltage requirements of the converter, and have a quick transient response to step loads. The ESR of the output capacitor affects the damping of the output filter and the transient response. In general, low-ESR capacitors are good choices due to their excellent capability in energy storage and transient performance. The RT6217A/B, therefore, is specially optimized for ceramic capacitors. Consider also DC bias and aging effects while selecting the output capacitor. Output Voltage Ripple The output voltage ripple at the switching frequency is a function of the inductor current ripple going through the output capacitor's impedance. To derive the output voltage ripple, the output capacitor with capacitance, C OUT, and its equivalent series resistance, RESR, must be taken into consideration. The output peak-to-peak ripple voltage ΔV P-P, caused by the inductor current ripple ΔIL, is characterized by two components, which are ESR ripple ΔVP-P_ESR and capacitive ripple ΔVP-P_C, can be expressed as below : P-P P-P_ESR P-P_C P-P_ESR L ESR LP-P_C OUT SW V = V V V = I R IV = 8C f If ceramic capacitors are used as the output capacitors, both the components need to be considered due to the extremely low ESR and relatively small capacitance. For the RT6217A/B's Typical Application Circuit for output voltage of 1.05V, and actual inductor current ripple (ΔI L) of 1.28A, using two paralleled 22 μF ceramic P-P_ESR L ESR LP-P_C OUT SW P-P P-P_ESR P-P_C V = I R = 1.28A 5m = 6.4mV I 1.28AV = = 8C f 84 4 μF5 0 0 k H z = 7.27mV V = V V = 1 3 . 6 7 m V Output Transient Undershoot and Overshoot In addition to the output voltage ripple at the switching frequency, the output capacitor and its ESR also affect output voltage sag, which is undershoot on a positive load step, and output voltage soar, which is overshoot on a negative load step. With the built-in ACOT TM architecture, the IC can have very fast transient responses to the load steps and small output transients. However, the combination of a small ceramic output capacitor (that is, of little capacitance) and a low output voltage (that is, only little charge stored in the output capacitor), used in low-duty-cycle applications (which require high inductance to get reasonable ripple currents for high input voltages), causes an increase in the size of voltage variations (i.e. sag/soar) in response to very quick load changes. Typically, the load changes slowly, compared with the IC's switching frequency. However, for present-day applications, more and more digital blocks may exhibit nearly instantaneous large transient load changes. Therefore, in the following section, how to calculate the worst-case voltage swings in response to very fast load steps will be explained in details. Both of the output transient undershoot and overshoot have two components : a voltage step caused by the output capacitor's ESR, and a voltage sag or soar due to the finite output capacitance and the inductor current slew rate. The following formulas can be used to check if the ESR is low enough (which is usually not a problem with ceramic capacitors) and if the output capacitance is large enough to prevent excessive sag or soar on very fast load steps, with the chosen inductor value. The voltage step (ΔV OUT_ESR) caused by the ESR is a function of the load step (ΔIOUT) and the ESR (RESR) of the output capacitor, described as below : capacitors with ESR of about 5mΩ as output capacitors, the two output ripple components are as below :
DS6217A/B-00 January 2018 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before p lacing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuit ry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Ric htek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by i mplication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Outline Dimension TSOT-23-8 (FC) Surface Mount Package Min Max Min Max A 0.700 1.000 0.028 0.039 A1 0.000 0.100 0.000 0.004 B 1.397 1.803 0.055 0.071 b 0.220 0.380 0.009 0.015 C 2.591 3.000 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.585 0.715 0.023 0.028 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 Symbol Dimensions In Millimeters Dimensions In Inches