RT5759AGQUF

RT5759A RICHTEK | Alldatasheet

Document overview

Manufacturer or author: jessica_hsu
PDF pages: 35

Technical content

Features

 Dramatically Fast Transient Response  Advanced COT Control Loop  Optimized for Ceramic Output Capacitors  3V to 6.5V Input Voltage Range  Integrated 12mΩΩΩΩΩ/8mΩΩΩΩΩ MOSFETs  Internal Start-Up into Pre-Biased Outputs  Power Good Indicator  Overcurrent and Over-Temperature Protections  Undervoltage Protection with Hiccup Mode  VID Control Range Via I 2C Compatible Interface : 0.6V to 1.725V step = 12.5mV

Applications

 Mobile Phones and Handheld Devices  STB, Cable Modem, and xDSL Platform  WLAN ASIC Power / Storage (SSD and HDD)  General Purpose for POL LV Buck Converter  TV

Ordering Information

Note : Richtek products are :  RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. RT5759A Package Type QUF : UQFN-13L 3x3 (FC) (U-Type) Lead Plating System G : Green (Halogen Free and Pb Free)

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin Configuration (TOP VIEW) UQFN-13L 3x3 (FC) Marking Information SW BOOT EN WDT AVCC AGND VIN SS SDA PGOOD SCL PGND FB 11 10 9 TG=YM DNN TG= : Product Code YMDNN : Date Code Simplified Application Circuit RT5759A PGOOD SW PGND FB AGND VIN AVCC EN BOOT VOUT VIN SS WDT VAVCC VPGOOD Enable Signal SDA SCL VIN

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 EN Enable control input. A logic-high enables the converter; a logic-low forces the IC into shutdown mode and reduces the supply current.

2 WDT

Control input for output voltage reset. Reset the output voltage register 0x02 to factory default setting value when this pin is pulled low. "Do Not" leave this pin floating. 3 BOOT Bootstrap, supply for high-side gate driver. Connect a 0.1 F ceramic capacitor between BOOT and the SW pins. 4 SW Switch node. Connect this pin to an external L-C filter. 5 PGND System GND. The power GND of the controller circuit. Use wide PCB traces to make the connections.

6 VIN

Input voltage. Support 3V to 6.5V input voltage. Connect this pin with a suitable capacitance for noise decoupling. The bypass capacitor should be placed as close to the VIN pin as possible. 7 AVCC LDO output for internal analog power. Connect a 4.7 F capacitor as close to the VCC pin as possible. 8 AGND Analog GND. AGND and PGND are connected with a short trace and at only one point to reduce circulating currents. 9 PGOOD Power good indicator output. This pin has an open-drain structure. Pull this pin high to a voltage source with a 100k resistor. 10 SDA I 2C interface, DATA. 11 SCL I 2C interface, CLK. 12 SS Soft-start time control pin. Connect a capacitor between the SS pin and AGND to set the soft-start time. The default internal start-up time is 1.2ms without external capacitor. 13 FB Feedback input. The pin is used to set the output voltage of the converter via the I2C interface.

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Comparator VIBIAS BOOT PGND SW AZC Driver SW Logic ControlUV OC Min Off FB Reg VIN UGATE LGATE Ramp Generator VREF SS DAC OUT Comparator PGOOD+ AGND DAC OUT 95% DAC VOUT = 0.6V to 1.725V DAC OUT EN EN Serial Interface 7 bits SCLSDA WDT On-Time VIN AVCC +EA- VREG5 VREG5 VREG5 SW

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Operation The RT5759A is a low voltage synchronous step-down converter that can support input voltage ranging from 3V to 6.5V and the output current can be up to 9A. The RT5759A uses ACOT ® mode control. To achieve good stability with low-ESR ceramic capacitors, the ACOT ® uses a virtual inductor current ramp generated inside the IC. This internal ramp signal replaces the ESR ramp normally provided by the output capacitor's ESR. The ramp signal and other internal compensations are optimized for low- ESR ceramic output capacitors. In steady-state operation, the feedback voltage, with the virtual inductor current ramp added, is compared to the reference voltage. When the combined signal is less than the reference, the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. The on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. After the on- time, the high-side switch is turned off and the synchronous rectifier is turned on and the inductor current ramps down linearly. At the same time, the minimum off-time one-shot is triggered to prevent another immediate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. The minimum off-time is kept short so that rapidly-repeated on-times can raise the inductor current quickly when needed. Shutdown, Start-Up and Enable (EN) The enable input (EN) has a logic-low level of 0.74V. When V EN is below this level, the IC enters shutdown mode and supply current drops to less than 1μA. When VEN exceeds its logic-high level of 0.92V, the IC is fully operational. When V EN exceeds its logic-high level, the pre-regulator turns on first. The power-up sequence from EN logic high to PGOOD going high is shown in Figure 1. Undervoltage Protection (UVLO) The UVLO continuously monitors the AVCC voltage to make sure the device works properly. When the AVCC is high enough to reach the UVLO high threshold voltage, the step-down converter softly starts or pre-bias to its regulated output voltage. When the AVCC decreases to its low threshold voltage, the device shuts down. Power Good Power Good pin is an open-drain logic output that is pulled to ground when the output voltage is lower or higher than its specified threshold under the conditions of OVP , OTP, dropout, EN shutdown, or during start-up time. Start-up time is the time of V OUT soft-start when power up or enable up. During the start-up time, PGOOD is low even the output voltage is within the specified threshold voltage. Only when the PGOOD indicator is high and output voltage is within the specified threshold voltage, then PGOOD is high. External Bootstrap Capacitor (C BOOT) Connect a 0.1 μF low ESR ceramic capacitor between BOOT and SW. This bootstrap capacitor provides the gate driver supply voltage for the high-side N-MOSFET switch. Output Undervoltage Protection (UVP) When the output voltage is lower than 70% reference voltage after soft-start, the UVP is triggered. Over-Temperature Protection (OTP) The RT5759A includes an Over-Temperature Protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when the junction temperature exceeds 150°C. Once the junction temperature cools down and returns to 100°C, the IC will resume normal operation with a complete soft-start. For continuous operation, provide adequate cooling so that the junction temperature does not exceed 150°C.

Electrical Characteristics

Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1)  Power Dissipation, PD @ TA = 25°C  Package Thermal Resistance (Note 2)  ESD Susceptibility (Note 3) Parameter Symbol Test Conditions Min Typ Max Unit Supply Voltage Input Voltage V IN 3 -- 6.5 V Supply Current Sleep Supply Current I Q V FB > 0.6V -- -- 100 A Shutdown Supply Current I SHDN V EN = 0V -- -- 1 A UVLO UVLO Rising Threshold V UVLO_R V AVCC rising -- 2.625 2.8 V UVLO Falling Threshold V UVLO_F V AVCC falling -- 2.5 -- V Logic Threshold EN Input Rising Threshold V ENH 0.77 0.92 1.07 V EN Input Falling Threshold V ENL 0.58 0.74 0.9 V EN Hysteresis VEN -- 0.18 -- V Input Current I EN V EN = 2V -- 1 5 A

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Shutdown Thermal Shutdown Threshold TSD -- 150 -- C Thermal Recovery Threshold TRC -- 100 -- C Output Voltage and Soft-Start Output Voltage V OUT CCM 0.7425 0.75 0.7575 V Soft-Start Time t SS VOUT = 0.75V, leave SS pin floating, 10% to 90%VOUT -- 1.2 -- ms RDS(ON) Switch On-Resistance High-Side R DS(ON)_H -- 12 -- Low-Side R DS(ON)_L -- 8 -- Current Limit Current Limit I LIM Valley current 9.1 10.8 12.5 A Switching Frequency and Minimum Off-Time Switching Frequency f SW 0x01[1:0] = 10b, CCM 0.8 1 1.2 MHz Minimum Off-Time t OFF_MIN -- 100 -- ns Protections UVP Trip Threshold V UVP -- 70 -- % UVP Time Delay t UVPDLY -- 5 -- s Power Good PGOOD Rising Threshold VTH_PGLH V FB rising (Good) -- 95 -- %VFB VTH_PGLH V FB rising (Fault) -- 110 -- PGOOD Falling Threshold VTH_PGHL V FB falling (Fault) -- 90 -- VTH_PGHL V FB falling (Good) -- 105 -- PGOOD Enable Delay Time 0x05 PGDSET[3:2] = 01b -- 10 -- s Discharge Resistor Discharge Resistor R DISCHG V EN = 0V, VAVCC = 5V -- 50 --  Regulation Line Regulation CCM -- 0.5 -- % Load Regulation (Note 5) CCM -- 0.5 -- % Watch-Dog Reset Watch-Dog Reset Input Voltage VWDT_H High level 1.2 -- -- V VWDT_L Low level -- -- 0.4

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. Parameter Symbol Test Conditions Min Typ Max Unit I2C SDA, SCL Input Voltage High level 1.2 -- -- V Low level -- -- 0.4 Fast Mode SCL Clock Rate f SCL -- -- 400 kHz Hold Time for a Repeated START Condition tHD;STA After this period, the first clock pulse is generated. 0.6 -- -- s Low Period of the SCL Clock t LOW 1.3 -- -- s High Period of the SCL Clock t HIGH 0.6 -- -- s Set-Up Time for a Repeated START Condition tSU;STA 0.6 -- -- s Data Hold Time t HD;DAT 0 -- 0.9 s Data Set-Up Time t SU;DAT 100 -- -- ns Set-Up Time for STOP Condition tSU;STO 0.6 -- -- s Bus Free Time between a STOP and a START Condition tBUF 1.3 -- -- s Rising Time of Both SDA/SCL Signals tr 20 -- 300 ns Falling Time of Both SDA/SCL Signals tf 20 -- 300 ns SDA/SCL Output Low Sink Current IOL SDA voltage = 0.4V 2 -- -- mA

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit RT5759A PGOOD SCL SW PGND SDA SS FB AGND VINAVCCEN BOOT VOUT 0.75V/9A VIN Enable Signal VIN 100k 10k 4.7μF 100nF 88μF 0.47μH 2 12 13 8 3671 10k 0.1μF 10μF WDT

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Output Voltage vs. Output Current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 1.5 3 4.5 6 7.5 9 Output Current (A) Output Voltage (V) VOUT = 1V, fSW = 1MHz VIN = 6.5V VIN = 5V VIN = 3V Switching Frequency vs. Input Voltage 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Switching Frequency (MHz) 1 VOUT = 1V Output Voltage vs. Input Voltage 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Output Voltage (V) IOUT = 0A IOUT = 3A IOUT = 6A IOUT = 9A VOUT = 1V, fSW = 1MHz Efficiency vs. Output Current 100 0123456789 Output Current (A) Efficiency (%) VIN = 6.5V, fSW = 1MHz VOUT = 1.5V VOUT = 1.2V VOUT = 1V VOUT = 0.8V VOUT = 0.6V Efficiency vs. Output Current 100 0123456789 Output Current (A) Efficiency (%) VIN = 5V, fSW = 1MHz VOUT = 1.5V VOUT = 1.2V VOUT = 1V VOUT = 0.8V VOUT = 0.6V Efficiency vs. Output Current 100 0123456789 Output Current (A) Efficiency (%) VIN = 3V, fSW = 1MHz VOUT = 1.5V VOUT = 1.2V VOUT = 1V VOUT = 0.8V VOUT = 0.6V

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Switching Frequency vs. Temperature 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 -50 -25 0 25 50 75 100 125 Temperature (°C) Switching Frequency (MHz) 1 VIN = 5V, VOUT = 1V Current Limit vs. Input Voltage 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Current Limit (A) VOUT = 1V Current Limit vs. Temperature 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Limit (A) VIN = 5V, VOUT = 1V Shutdown Supply Current vs. Input Voltage 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 33 . 544 . 555 . 566 . 5 Input Voltage (V) Shutdown Supply Current ( μA) 1 VEN = 0V Shutdown Supply Current vs. Temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Shutdown Supply Current ( μA) 1 VIN = 5V, VEN = 0V Sleep Supply Current vs. Input Voltage 105 120 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Sleep Supply Current ( μA) VEN = high

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (100 μs/Div) Load Transient Response VOUT (20mV/Div) IOUT (4.5A/Div) VIN = 5V, VOUT = 1V, IOUT = 0A to 9A Time (100 μs/Div) Load Transient Response VOUT (10mV/Div) IOUT (4.5A/Div) VIN = 5V, VOUT = 1V, IOUT = 4.5A to 9A Time (20ms/Div) Output Ripple Voltage VOUT (10mV/Div) VSW (2V/Div) VIN = 5V, VOUT = 1V, IOUT = 0A Reference Voltage vs. Temperature 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 -50 -25 0 25 50 75 100 125 Temperature (°C) Reference Voltage (V) VIN = 5V Reference Voltage vs. Input Voltage 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 0.63 0.64 0.65 3 3.5 4 4.5 5 5.5 6 6.5 Input Voltage (V) Reference Voltage (V) Sleep Supply Current vs. Temperature 105 120 -50 -25 0 25 50 75 100 125 Temperature (°C) Sleep Supply Current ( μA) VIN = 5V, VEN = high

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (400ns/Div) Output Ripple Voltage VOUT (10mV/Div) VSW (2V/Div) VIN = 5V, VOUT = 1V, IOUT = 9A Time (4ms/Div) Power On from EN VOUT (1V/Div) VEN (2V/Div) IL (10A/Div) VIN = 5V, VOUT = 1V, IOUT = 9A VSW (5V/Div) Time (4ms/Div) Power Off from EN VOUT (1V/Div) VEN (2V/Div) IL (10A/Div) VIN = 5V, VOUT = 1V, IOUT = 9A VSW (5V/Div) Time (10ms/Div) UVP Short (Hiccup Mode) VOUT (1V/Div) VIN (5V/Div) IL (10A/Div) VSW (5V/Div) VIN = 5V, VOUT = 1V, IOUT = short

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 1. The RT5759A Register Summary Table 2. MANUFACTURER_ID Table 3. FREQ_REG Set VID change slew rate and PWM frequency.

7 Reserved Reserved bit

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Bits Name Description 6 : 0 SEL Supply voltage : SEL[6:0] = 0101000b : 1.1V SEL[6:0] = 0101001b : 1.1125V SEL[6:0] = 0101010b : 1.125V SEL[6:0] = 0101011b : 1.1375V SEL[6:0] = 0101100b : 1.15V SEL[6:0] = 0101101b : 1.1625V SEL[6:0] = 0101110b : 1.175V SEL[6:0] = 0101111b : 1.1875V SEL[6:0] = 0110000b : 1.2V SEL[6:0] = 0110001b : 1.2125V SEL[6:0] = 0110010b : 1.225V SEL[6:0] = 0110011b : 1.2375V SEL[6:0] = 0110100b : 1.25V SEL[6:0] = 0110101b : 1.2625V SEL[6:0] = 0110110b : 1.275V SEL[6:0] = 0110111b : 1.2875V SEL[6:0] = 0111000b : 1.3V SEL[6:0] = 0111001b : 1.3125V SEL[6:0] = 0111010b : 1.325V SEL[6:0] = 0111 011b : 1.3375V SEL[6:0] = 0111100b : 1.35V SEL[6:0] = 0111101b : 1.3625V SEL[6:0] = 0111110b : 1.375V SEL[6:0] = 0111111b : 1.3875V SEL[6:0] = 1000000b : 1.4V SEL[6:0] = 1000001b : 1.4125V SEL[6:0] = 1000010b : 1.425V SEL[6:0] = 1000011b : 1.4375V SEL[6:0] = 1000100b : 1.45V SEL[6:0] = 1000101b : 1.4625V SEL[6:0] = 1000110b : 1.475V SEL[6:0] = 1000111b : 1.4875V SEL[6:0] = 1001000b : 1.5V SEL[6:0] = 1001001b : 1.5125V SEL[6:0] = 1001010b : 1.525V SEL[6:0] = 1001011b : 1.5375V SEL[6:0] = 1001100b : 1.55V SEL[6:0] = 1001101b : 1.5625V SEL[6:0] = 1001110b : 1.575V SEL[6:0] = 1001111b : 1.5875V SEL[6:0] = 1010000b : 1.6V SEL[6:0] = 1010001b : 1.6125V SEL[6:0] = 1010010b : 1.625V SEL[6:0] = 1010011b : 1.6375V SEL[6:0] = 1010100b : 1.65V SEL[6:0] = 1010101b : 1.6625V SEL[6:0] = 1010110b : 1.675V SEL[6:0] = 1010111b : 1.6875V SEL[6:0] = 1011000b : 1.7V SEL[6:0] = 1011001b : 1.7125V SEL[6:0] = 1011010b to 1111111b : 1.725V

3 Discharge

2 PWM PWM[2] = 0b : PSKIP mode (default)

1 Enable Enable[1] = 0b : disable

0 Reserved Reserved bit

Table 6. STATUS_REG

1 OT OT[1] = 0b : no OT

0 UV UV[0] = 0b : no UV

1 WDT_EN

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Inductor Selection When designing the output stage of the synchronous buck converter, it is recommended to start with the inductor. However, it may require several iterations because the exact inductor value is generally flexible and is optimized for low cost, small form factor, and high overall performance of the converter. Further, inductors vary with manufacturers in both material and value, and typically have a tolerance of ±20%. Three key inductor parameters to be specified for operation with the device are inductance (L), inductor saturation current (I SAT), and DC resistance (DCR), which affects performance of the output stage. An inductor with lower DCR is recommended for applications of higher peak current or load current, and it can improve system performance. Lower inductor values are beneficial to the system in physical size, cost, DCR, and transient response, but they will cause higher inductor peak current and output voltage ripple to decrease system efficiency. Conversely, higher inductor values can increase system efficiency at the expense of larger physical size, slower transient response due to the longer response time of the inductor. A good compromise among size, efficiency, and transient response can be achieved by setting an inductor current ripple (ΔI L) of about 20% to 50% of the desired full output load current. To meet the inductor current ripple (ΔI L) requirements, a minimum inductance must be chosen and the approximate inductance can be calculated by the selected input voltage, output voltage, switching frequency SW), and inductor current ripple (ΔIL), as below :    OUT IN OUT IN SW L VV VL = Vf I Once the inductance is chosen, the inductor ripple current (ΔIL) and peak inductor current (IL_PEAK) can be calculated, as below : OUT IN OUT L IN SW L_PEAK OUT_MAX L L_VALLEY OUT_MAX L VV VI= Vf L 1I = I I 2 1I = I I 2 where IOUT_MAX is the maximum rated output current or the required peak current. The inductor must be selected to have a saturation current and thermal rating which exceed the required peak inductor current I L_PEAK. For a robust design to maintain control of inductor current in overload or short-circuit conditions, some applications may desire inductor saturation current rating up to the switch current limits of the device. However, the built-in output undervoltage protection (UVP) feature makes this unnecessary for most applications. For best efficiency, a low-loss inductor having the lowest possible DCR that still fits in the allotted dimensions will be chosen. Ferrite cores are often the best choice. However, a shielded inductor, possibly larger or more expensive, will probably give fewer EMI and other noise problems. The following design example is illustrated to walk through the steps to apply the equations defined above. The RT5759A's Typical Application Circuit for output voltage of 0.75V at maximum output current of 9A and an input voltage of 5V with inductor current ripple of 1.8A (i.e. 20%, in the recommended range of 20% to 50%, of the maximum rated output current) is taken as the design example. The approximate minimum inductor value can first be calculated as below : 1 5 0.75L = = 0.472 μH51 M H z1 . 8 A where fSW is 1MHz. The inductor current ripple will be set at 1.8A, as long as the calculated inductance of 0.472μH is used. However, the inductor of the exact inductance value may not be readily available, and therefore an inductor of a nearby value will be chosen. In this case, 0.47 μH Richtek’s component specification does not include the following information in the Application Information section. Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their own designs and to ensure the functional suitability of their components and systems.

Application Information

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. L 1 5 0.75I= = 1 . 8 A51 M H z0 . 4 7μH L_PEAK OUT_MAX L 11 . 8 AI = I I = 9 + = 9.9A 22 inductance is available and actually used in the Typical Application Circuit. The actual inductor current ripple (ΔIL) and required peak inductor current (I L_PEAK) can be calculated as below : For the 0.47μH inductance value, the inductor saturation current and thermal rating should exceed 9.9A. Input Capacitor Selection Input capacitors are needed to smooth out the RMS ripple current (I RMS) imposed by the switching currents and drawn from the input power source, by reducing the ripple voltage amplitude seen at the input of the converters. The voltage rating of the input filter capacitors must be greater than the maximum input voltage. It is also important to consider the ripple current capabilities of capacitors. The RMS ripple current (I RMS) of the regulator can be determined by the input voltage (V IN), output voltage (VOUT), and rated output current (I OUT) as the following equation : OUT INRMS OUT IN OUT V VI = I 1 VV  From the above, the maximum RMS input ripple current occurs at maximum output load, which will be used as the requirements to consider the current capabilities of the input capacitors. Furthermore, for a single-phase buck converter, the duty cycle is approximately the ratio of output voltage to input voltage. The maximum ripple voltage usually occurs at 50% duty cycle, that is, V IN = 2 x VOUT. The maximum IRMS, as IRMS (Max), can be approximated as 0.5 x IOUT_MAX, where IOUT_MAX is the maximum rated output current. Besides, the variation of the capacitance value with temperature, DC bias voltage, switching frequency, and allowable peal-to-peak ripple voltage that reflects back to the input, also needs to be taken into consideration. For example, the capacitance value of a capacitor decreases as the DC bias across the capacitor increases; also, higher switching frequency allows the use of input capacitors of smaller capacitance values. Ceramic capacitors are most commonly used to be placed right at the input of the converter to reduce ripple voltage amplitude because only ceramic capacitors have extremely low ESR which is required to reduce the ripple voltage. Note that the capacitors need to be placed as close as to the input pins as possible for highest effectiveness. Ceramic capacitors are preferred also due to their low cost, small size, high RMS current ratings, robust inrush surge current capabilities, and low parasitic inductance, which helps reduce the high-frequency ringing on the input supply. However, care must be taken when ceramic capacitors are used at the input, and the input power is supplied by a wall adapter, connected through a long and thin wire. When a load step occurs at the output, a sudden inrush current will surge through the long inductive wire, which can induce ringing at the device's power input and potentially cause a very large voltage spike at the VIN pin to damage the device. For applications where the input power is located far from the device input, it may be required that the low-ESR ceramic input capacitors be placed in parallel with a bulk capacitor of other types, such as tantalum, electrolytic, or polymer, to dampen the voltage ringing and overshoot at the input, caused by the long input power path and input ceramic capacitor. It is suggested to choose capacitors with higher temperature ratings than required. Several ceramic capacitors may be parallel to meet application requirements, such as the RMS current, size, and height. The Typical Application Circuit can use one 10μF and one high-frequency- noise-filtering 0.1 μF low-ESR ceramic capacitors at the input. Output Capacitor Selection Output capacitance affects the output voltage of the converter, the response time of the output feedback loop, and the requirements for output voltage sag and soar. The sag occurs after a sudden load step current applied, and the soar occurs after a sudden load removal. Increasing the output capacitance reduces the output voltage ripple and output sag and soar, while it increases the response time that the output voltage feedback loop takes to respond to step loads. Therefore, there is a tradeoff between output capacitance and output response. It is recommended to choose a minimum output capacitance to meet the output

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. PP PP _ E S R PP _ C P P_ESR L ESR LPP _ C OUT SW V = V + V V = I R IV = 8C f         If ceramic capacitors are used as the output capacitors, both the components need to be considered due to the extremely low ESR and relatively small capacitance. For the RT5759A's Typical Application Circuit for output voltage of 0.75V, and actual inductor current ripple (ΔI L) of 1.8A, using four paralleled 22μF ceramic capacitors with ESR of about 5mΩ as output capacitors; the two output ripple components are as below : P P_ESR L ESR LPP _ C OUT SW PP PP _ E S R PP _ C V = I R = 1.8A 5m = 9mV I 1.8AV = = 8C f 88 8 μF1 M H z = 2.56mV V = V V = 11.56mV      Output Transient Undershoot and Overshoot In addition to the output voltage ripple at the switching frequency, the output capacitor and its ESR also affect output voltage sag, which is undershoot on a positive load step, and output voltage soar, which is overshoot on a negative load step. With the built-in ACOT ® architecture, the IC can have very fast transient responses to the load steps and small output transients. However, the combination of a small ceramic output capacitor (that is, of little capacitance) and a low output voltage (that is, only little charge stored in the output capacitor), used in low-duty-cycle applications (which require high inductance to get reasonable ripple currents for high input voltages), causes an increase in the size of voltage variations (i.e. sag/soar) in response to very quick load changes. Typically, the load changes slowly, compared with the IC's switching frequency. However, for present- day applications, more and more digital blocks may exhibit nearly instantaneous large transient load changes. Therefore, in the following section, how to calculate the worst-case voltage swings in response to very fast load steps will be explained in details. Both of the output transient undershoot and overshoot have two components : a voltage step caused by the output capacitor's ESR, and a voltage sag or soar due to the finite output capacitance and the inductor current slew rate. The following formulas can be used to check if the ESR is low enough (which is usually not a problem with ceramic capacitors) and if the output capacitance is large enough to prevent excessive sag or soar on very fast load steps, with the chosen inductor value. The voltage step ( ΔV OUT_ESR ) caused by the ESR is a function of the load step (ΔIOUT) and the ESR (RESR) of the output capacitor, described as below : ΔVOUT_ESR = ΔIOUT x RESR The voltage amplitude (ΔVOUT_SAG) of the capacitive sag is a function of the load step ( ΔIOUT), the output capacitor value (COUT), the inductor value (L), the input-to-output voltage differential, and the maximum duty cycle (DMAX). And, the maximum duty cycle during a fast transient can be determined by the on-time (t ON) and the minimum off- time (tOFF_MIN) since the ACOT® control scheme will ramp voltage requirements of the converter, and have a quick transient response to step loads. The ESR of the output capacitor affects the damping of the output filter and the transient response. In general, low-ESR capacitors are good choices due to their excellent capability in energy storage and transient performance. The RT5759A, therefore, is specially optimized for ceramic capacitors. Consider also DC bias and aging effects while selecting the output capacitor. Output Voltage Ripple The output voltage ripple at the switching frequency is a function of the inductor current ripple going through the output capacitor's impedance. To derive the output voltage ripple, the output capacitor with capacitance, C OUT, and its equivalent series resistance, RESR, must be taken into consideration. The output peak-to-peak ripple voltage ΔV P−P, caused by the inductor current ripple ΔIL, is characterized by two components, which are ESR ripple ΔV P-P_ESR and capacitive ripple ΔVP−P_C; they can be expressed as below :

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Low-Side Current-Limit Protection The RT5759A features a cycle-by-cycle valley-type current limit protection, measuring the inductor current through the synchronous rectifier (low-side switch). The inductor current level is determined by measuring the low-side switch voltage between the SW pin and GND, which is proportional to the switch current, during the low-side on- time. For greater accuracy, temperature compensation is added to the voltage sensing. Once the current rises above the low-side switch valley current limit (I LIM), the on-time one-shot will be inhibited until the inductor current ramps down to the current limit level (I LIM), that is, another on- time can only be triggered when the inductor current goes below the low-side current limit. This function can prevent the average output current from greatly exceeding the guaranteed low-side current limit value. If the output load current exceeds the available inductor current (clamped by the above-mentioned low-side current limit), the output capacitor needs to supply the extra current such that the output voltage will begin to drop. If it drops below the output undervoltage protection trip threshold, the IC will stop switching to avoid excessive heat. I 2C Interface A general-purpose serial interface to control and monitor the configuration registers is provided in the RT5759A and the I 2C slave address of the RT5759A would be 0x62. This I2C interface supports standard slave mode (100kbps) and fast mode (400kbps). A multiple bytes reading or writing over the I 2C interface could also be done through the RT5759A (see Figure 9).

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. on the maximum power dissipation. Figure 10. Derating Curve of Maximum Power

DS5759A-01 January 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Suggested Inductors for Typical Application Circuit Component Supplier Part No. Inductance ( H) DCR (m ) Dimensions (mm) Recommended Component Selection for Typical Application Circuit Component Supplier Part No. Capacitance ( F) Case Size MURATA GRM32ER71H106KA12L 10 1210 TDK C3225X5R1E226MT 22 1210 MURATA GRM188R61C475KAAJ 4. 7 0603

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. RT5759A DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension U-Type 13L QFN 3x3 (FC) Package Min Max Min Max A 0.500 0.600 0.020 0.024 A1 0.000 0.050 0.000 0.002 A3 0.100 0.200 0.004 0.008 b 0.150 0.250 0.006 0.010 b1 0.310 0.410 0.012 0.016 b2 0.320 0.420 0.013 0.017 b3 0.740 0.840 0.029 0.033 D 2.900 3.100 0.114 0.122 E 2.900 3.100 0.114 0.122 e L 0.300 0.400 0.012 0.016 L1 0.740 0.840 0.029 0.033 L2 0.480 0.580 0.019 0.023 L3 0.740 0.840 0.029 0.033 L4 0.390 0.490 0.015 0.019 L5 1.410 1.510 0.056 0.059 H10 H11 1.050 0.041 0.350 0.014 1.150 0.045 1.550 0.061 1.050 0.041 0.400 0.016 0.600 0.024 0.420 0.017 0.600 0.024 0.750 0.030 0.280 0.011 Symbol Dimensions In Millimeters Dimensions In Inches 0.400 0.016

DS5759A-01 January 2023www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than ci rcuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no respon sibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Footprint Information Package Number of Pin Tolerance P Ax Bx C D K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 H ±0.05UQFN3x3-13(FC) 13 Footprint Dimension (mm)

DS5759A-01 January 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Datasheet Revision History Version Date Description Item 01 2023/1/10 Modify General Description on P1 Features on P1 Functional Pin Description on P3 Functional Block Diagram on P4 Typical Application Circuit on P10 Functional Register Table on P16 Application Information on P20, 21, 22, 24

Summary

9A, 6.5V, 1MHz, ACOT® Synchronous Step-Down Converter with I2C Interface January 2023

Description