RT5753

RT5753 RICHTEK | Alldatasheet

Document overview

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Technical content

Features

   Input Voltage Range from 2.5V to 6V    Integrated 100mΩ ΩΩ ΩΩ and 70mΩ ΩΩ ΩΩ FETs    100% Duty Cycle for Lowest Dropout    Internal Reference Voltage with 1% Accuracy    1.2MHz Typical Switching Frequency    Power Saving Mode for Light Loads (RT5753A/C/E/F)    Advanced Constant On-Time (ACOT® ) Control    Internal Soft-Start (1.5ms/750μ μμ μμs)    Enable Control Input    Power Good Indicator    Both FETs Overcurrent Protection    Negative Overcurrent Protection (RT5753B/D)    Input Undervoltage Lockout Protection    Output Undervoltage Protection    Over-Temperature Protection    RoHS Compliant and Halogen Free

Applications

 Mobile Phones and Handheld Devices  STB, Cable Modem, and xDSL Platforms  WLAN ASIC Power / Storage (SSD and HDD)  General Purpose for POL LV Buck Converters Simplified Application Circuit FB PGNDAGND PG VIN EN SW VOUTVIN L CIN RT5753 RFB1 RFB2 COUT VPG Chip Enable CFF RPG

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Pin Configuration (TOP VIEW) WDFN-8L 2x2/WDFN-8SL 2x2

Ordering Information

QW: WDFN-8L 2x2 (W-Type) QWA: WDFN-8SL 2x2 (W-Type) (Exposed Pad-Option 2) Lead Plating System G: Richtek Green Policy Compliant RT5753 UVP Option H: Hiccup (For A, B, C, D only) L: Latched-Off PWM Operation Mode A: SS TIME = 1.5m(typ.) & Automatic PSM & Rdischg = 100ohm B: SS TIME = 1.5m(typ.) & Forced PWM & Rdischg = 100ohm C: SS TIME = 750 μs(typ.) & Automatic PSM & Rdischg = 100ohm D: SS TIME = 750 μs(typ.) & Forced PWM & Rdischg = 100ohm E: SS TIME = 1.5m(typ.) & Automatic PSM & Rdischg = 50ohm F: SS TIME = 750 μs(typ.) & Automatic PSM & Rdischg = 50ohm Note : Richtek products are Richtek Green Policy compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Marking Information 54W RT5753AHGQW 54 : Product Code W : Date Code RT5753ALGQW 51W 51 : Product Code W : Date Code RT5753BLGQW 4YW 4Y : Product Code W : Date Code RT5753BHGQW 4ZW 4Z : Product Code W : Date Code RT5753AHGQWA 5K : Product Code W : Date Code RT5753ALGQWA 5J : Product Code W : Date Code RT5753BHGQWA 5H : Product Code W : Date Code RT5753BLGQWA 5G : Product Code W : Date Code 5KW 5JW 5HW 5GW RT5753CHGQW 5Y : Product Code W : Date Code RT5753CLGQW 5X : Product Code W : Date Code RT5753DHGQW 5W : Product Code W : Date Code RT5753DLGQW 5V : Product Code W : Date Code RT5753CHGQWA 62 : Product Code W : Date Code RT5753CLGQWA 61 : Product Code W : Date Code RT5753DHGQWA 60 : Product Code W : Date Code RT5753DLGQWA 5Z : Product Code W : Date Code 5YW 5XW 5WW 5VW 62W 61W 60W 5ZW

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. 6LW 6KW RT5753FLGQW 6L : Product Code W : Date Code RT5753FLGQWA 6K : Product Code W : Date Code

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Functional Pin Description Pin No. Pin Name Pin Function 1 FB Output voltage sense. Sense the output voltage at the FB pin through a resistive divider. The feedback reference voltage is 0.6V typically. 2 PG Open-drain power-good indicator output. Once being started-up, PG will be pulled low to ground if any internal protection is triggered.

3 VIN

Power input. The input voltage range is from 2.5V to 6V. Connect a suitable input capacitor between this pin and PGND pins, usually one 22F or higher than 22F ceramic capacitors is recommended. 4, 9 (Exposed Pad) PGND Power ground. The exposed pad is internally unconnected which must be soldered to a large PCB cooper area and connected to PGND for maximum power dissipation. 5 NC No internal connection. Keep this pin floating. 6 SW Switch node between the internal switch and the synchronous rectifier. Connect this pin to the inductor. 7 EN Enable control input. Connect this pin to logic high enables the device and connect this pin to ground disables the device. 8 AGND Analog ground. PG VIN PGND EN VREF Shutdown Control SWFB Driver TON Logic Control SW Current Limit Detector Comparator+-+ Error Amplifier UVLO OTP SW - VFB Ramp Generator UV FBVIN 90%VREF SW Discharge Resistor *OVP AGND *OVP : OVP is designed for RT5753AL/BL/CL/DL/EL/FL FB

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. the on-time one-shot generator. and soft-start sequence being initiated. voltage as a reference voltage to the PWM comparator. Figure 1. Start-Up Sequence

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. indication profile is shown below. Table 1. PG Pin Status

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. maximum range of operation as a secondary fail-safe and therefore should not be relied upon operationally. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Negative Overcurrent Limit The RT5753B/D is the part which is forced to PWM and allows negative current operation. In case of PWM operation, high negative current may be generated as an external power source which is tied to output terminal unexpectedly. As the risk described above, the internal circuit monitors negative current in each on-time interval of low-side MOSFET and compares it with NOC threshold. Once the negative current exceeds the NOC threshold, the low-side MOSFET is turned off immediately, and then the high-side MOSFET will be turned on to discharge the energy of output inductor. This behavior can keep the valley of negative current at NOC threshold to protect low-side MOSFET. However, the negative current can't be limited at NOC threshold anymore since minimum off-time is reached.

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Recommended Operating Conditions (Note 3) Absolute Maximum Ratings (Note 1) ESD Ratings (Note 2)  ESD Susceptibility Thermal Parameter WDFN-8L 2x2 WDFN-8SL 2x2 Unit JA Junction-to-ambient thermal resistance (JEDEC standard) 49.5 48.2 C/W JC(Top) Junction-to-case (top) thermal resistance 167.1 158.5 C/W JC(Bottom) Junction-to-case (bottom) thermal resistance 5.8 5.5 C/W JA(EVB) Junction-to-ambient thermal resistance (specific EVB) 49.7 49.7 C/W JC(Top) Junction-to-top characterization parameter 5.01 5.01 C/W JB Junction-to-board characterization parameter 30.5 30.5 C/W Thermal Information (Note 4 and Note 5)

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Electrical Characteristics

Parameter Symbol Test Conditions Min Typ Max Unit Supply Voltage VIN Supply Input Operating Voltage VIN 2.5 -- 6 V Undervoltage Lockout Threshold V UVLO V IN rising 2.15 2.3 2.45 V Undervoltage Lockout Threshold Hysteresis VUVLO -- 300 -- mV Supply Current (Shutdown) I SHDN VEN = 0V, TA = 25°C -- -- 2 VEN = 0V -- -- 15 Supply Current (Quiescent) I Q VEN = 2V, VFB = 0.7V, not switching -- 23 35 A Soft-Start Soft-Start Time t SS 0%VOUT to 95%VOUT, RT5753A/B/E 1 1.5 2.4 ms 0%VOUT to 95%VOUT, RT5753C/D/F 0.5 0.75 1.2 Enable Voltage Enable Voltage Threshold VEN_H EN high-level input voltage 0.8 -- 1.2 V VEN_L EN low-level input voltage 0.4 -- 0.85 Enable Pull-Low Current IEN_PL -- 1.5 -- A Feedback Voltage Feedback Threshold Voltage V FB 0.594 0.6 0.606 V Feedback Input Current I FB V FB = 0.6V, TA = 25°C -- 0.1 0.4 µA Internal MOSFET High-Side On-Resistance R DS(ON)_H -- 100 120 Low-Side On-Resistance R DS(ON)_L -- 70 85 Current Limit High-Side Switch Current Limit I LIM_H VIN = 3.6V, VOUT = 1.2V, L = 1H, TA = 25C 3.6 4.14 4.8 A Low-Side Switch Valley Current Limit ILIM_L 3 3.45 3.9 Switching Frequency Switching Frequency f SW 1 1.2 1.44 MHz On-Time Timer Control Minimum Off-Time t OFF_MIN -- 90 -- ns Output Voltage Protection Output Undervoltage Threshold (RT5753AH/BH/CH/DH : Hiccup) (RT5753AL/BL/CL/DL/EL/FL : Latch-Off) V UVP -- 40 -- % (VIN = 3.6V. T J = T A = −40°C to 125 °C. Typical value is tested at T A = 25 °C. The limit over temperature is guaranteed by characterization, unless otherwise noted.)

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Output Overvoltage Threshold (RT5753AL/BL/CL/DL/EL/FL: Latch-Off, Deglitch Time = 2s) VOVP V FB rising 110 120 130 % Thermal Shutdown Thermal Shutdown Threshold T SD -- 150 -- Thermal Shutdown Hysteresis TSD -- 20 -- Power Good Power Good High Threshold V TH_PGLH V FB rising, PG goes high 83 90 -- % Power Good Falling Threshold V TH_PGHL V FB falling, PG goes low 78 85 -- % Power Good Sink Current Capability I PG sinks 5mA -- -- 0.4 V Output Discharge Resistor Output Discharge Switch On-Resistor (RT5753A/B/C/D) RDISCHG V EN = 0V (Protection) -- 100 -- Output Discharge Switch On-Resistor (RT5753E/F) -- 50 -- Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. Devices are ESD sensitive. Handling precautions are recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. For more information about thermal parameter, see the Application and Definition of Thermal Resistances report, AN061. Note 5. θJA(EVB), ψJC(Top) and ψJB are measured on a high effective-thermal-conductivity four-layer test board which is in size of 70mm x 50mm; furthermore, all layers with 1 oz. Cu. Thermal resistance/parameter values may vary depending on the PCB material, layout, and test environmental conditions.

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Table 2. Suggested Component Values Table 3. Recommended External Components

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 2.5V VIN = 3.3V VIN = 3.6V VIN = 4.5V VIN = 5V RT5753B/D, VOUT = 1.2V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 3.3V VIN = 3.6V VIN = 4.5V VIN = 5V RT5753B/D, VOUT = 1.8V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 4.5V VIN = 5V RT5753B/D, VOUT = 3.3V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 4.5V VIN = 5V RT5753A/C/E/F, VOUT = 3.3V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 3.3V VIN = 3.6V VIN = 4.5V VIN = 5V RT5753A/C/E/F, VOUT = 1.8V Efficiency vs. Output Current 100 0.001 0.01 0.1 1 10 Output Current (A) Efficiency (%) VIN = 2.5V VIN = 3.3V VIN = 3.6V VIN = 4.5V VIN = 5V RT5753A/C/E/F, VOUT = 1.2V

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Switching Frequency vs. Temperature 1.00 1.05 1.10 1.15 1.20 1.25 1.30 -50 -25 0 25 50 75 100 125 Temperature (°C) Switching Frequency (MHz) 1 Current Limit vs. Temperature 4.0 4.2 4.4 4.6 4.8 5.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Limit (A) High-side MOSFET, VIN = 3.6V Current Limit vs. Temperature 3.0 3.2 3.4 3.6 3.8 4.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Limit (A) Low-side MOSFET, VIN = 3.6V Output Voltage vs. Output Current 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) RT5753B/D, VIN = 5V, VOUT = 1.2V Output Voltage vs. Input Voltage 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.5 3 3.5 4 4.5 5 5.5 6 Input Voltage (V) Output Voltage(V) VOUT = 1.2V, I OUT = 1.5A Output Voltage vs. Output Current 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) RT5753A/C/E/F, VIN = 5V, V OUT = 1.2V

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Quiescent Current vs. Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) Quiescent Current (μA) VIN = 3.6V Shutdown Current vs. Temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Shutdown Current (μA) 1 VIN = 3.6V Input UVLO Threshold vs. Temperature 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 100 125 Temperature (°C) Input UVLO Threshold(V ) Falling Rising Enable Voltage Threshold vs. Temperature 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -50 -25 0 25 50 75 100 125 Temperature (°C) Enable Voltage Threshold(V ) Falling Rising Reference Voltage vs. Temperature 0.55 0.56 0.57 0.58 0.59 0.60 0.61 0.62 -50 -25 0 25 50 75 100 125 Temperature (°C) Reference Voltage (V) VIN = 3.6V, IOUT = 0A Time (20 μs/Div) Load Transient Response VOUT (50mV/Div) IOUT (500mA/Div) VIN = 5V, VOUT = 3.3V, L = 1 μH, COUT = 44μF, IOUT = 100mA to 1A, TR = TF = 1μs

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (20 μs/Div) Load Transient Response VOUT (50mV/Div) IOUT (1A/Div) VIN = 3.6V, VOUT = 1.2V, L = 1 μH, COUT = 44μF, CFF = 22pF, IOUT = 2A to 3A, TR = TF = 1μs Time (20 μs/Div) Load Transient Response VOUT (50mV/Div) IOUT (500mA/Div) VIN = 3.6V, VOUT = 1.2V, L = 1 μH, COUT = 44μF, CFF = 22pF, IOUT = 100mA to 1A, TR = TF = 1μs Time (20 μs/Div) Load Transient Response VOUT (100mV/Div) IOUT (1A/Div) VIN = 5V, VOUT = 3.3V, L = 1 μH, COUT = 44μF, IOUT = 2A to 3A, TR = TF = 1μs Time (50 μs/Div) Output Ripple Voltage VOUT (20mV/Div) VSW (4V/Div) VIN = 3.6V, VOUT = 1.2V, I OUT = 10mA, L = 1μH, COUT = 44μF, CFF = 22pF Time (500ns/Div) Output Ripple Voltage VOUT (20mV/Div) VSW (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 1.5A, L = 1μH, COUT = 44μF Time (50 μs/Div) Output Ripple Voltage VOUT (20mV/Div) VSW (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 10mA, L = 1μH, COUT = 44μF

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (500ns/Div) Output Ripple Voltage VOUT (10mV/Div) VSW (4V/Div) VIN = 3.6V, V OUT = 1.2V, I OUT = 1.5A, L = 1μH, COUT = 44μF, CFF = 22pF Time (1ms/Div) Power On from EN VOUT (500mV/Div) VEN (1V/Div) IOUT (1A/Div) VPG (2V/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A VPG reference source pull high to 3.6V RT5753A/B/E Time (50 μs/Div) Power Off from EN VOUT (1V/Div) VEN (1V/Div) IOUT (1A/Div) VPG (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 3A, VPG reference source pull high to 5V RT5753A/B/C/D Time (2ms/Div) Power On from VIN VOUT (2V/Div) VIN (2V/Div) VSW (4V/Div) IOUT (2A/Div) VIN = 5V, VOUT = 3.3V, IOUT = 3A RT5753A/B/E Time (1ms/Div) Power On from EN VOUT (1V/Div) VEN (1V/Div) IOUT (1A/Div) VPG (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 3A, VPG reference source pull high to 5V RT5753A/B/E Time (5ms/Div) Power Off from VIN VOUT (2V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 5V, VOUT = 3.3V, IOUT = 3A RT5753A/B/C/D

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (50 μs/Div) Power Off from EN VOUT (500mV/Div) VEN (1V/Div) IOUT (1A/Div) VPG (2V/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A VPG reference source pull high to 3.6V RT5753A/B/C/D Time (5ms/Div) Power Off from VIN VOUT (1V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A RT5753A/B/C/D Time (2ms/Div) Power On from VIN VOUT (2V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 5V, VOUT = 3.3V, IOUT = 3A RT5753C/D/F Time (1ms/Div) Power On from EN VOUT (1V/Div) VEN (1V/Div) IOUT (1A/Div) VPG (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 3A VPG reference source pull high to 5V RT5753C/D/F Time (5ms/Div) Power On from VIN VOUT (1V/Div) VIN (2V/Div) VSW (4V/Div) IOUT (2A/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A RT5753A/B/E Time (50 μs/Div) Power Off from EN VOUT (1V/Div) VEN (1V/Div) IOUT (1A/Div) VPG (4V/Div) VIN = 5V, VOUT = 3.3V, IOUT = 3A RT5753E/F VPG reference source pull high to 5V

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Time (5ms/Div) Power On from VIN VOUT (1V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A RT5753C/D/F Time (1ms/Div) Power On from EN VOUT (500mV/Div) VEN (1V/Div) IOUT (1A/Div) VPG (2V/Div) VIN = 3.6V, VOUT = 1.2V, IOUT = 3A VPG reference source pull high to 3.6V RT5753C/D/F Time (5ms/Div) Power Off from VIN VOUT (1V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 3.6V, VOUT = 1.2V, I OUT = 3ART5753E/F Time (50 μs/Div) Power Off from EN VOUT (500mV/Div) VEN (1V/Div) IOUT (1A/Div) VPG (2V/Div) VIN = 3.6V, VOUT = 1.2V, I OUT = 3A VPG reference source pull high to 3.6V RT5753E/F Time (5ms/Div) Power Off from VIN VOUT (2V/Div) VIN (2V/Div) IOUT (2A/Div) VSW (4V/Div) VIN = 5V, VOUT = 3.3V, I OUT = 3A RT5753E/F

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.

Application Information

The output stage of a synchronous buck converter is composed of an inductor and capacitor, which stores and delivers energy to the load, and forms a second-order low- pass filter to smooth out the switch node voltage to maintain a regulated output voltage. Inductor Selection The inductor selection trade-offs among size, cost, efficiency, and transient response requirements. Generally, three key inductor parameters are specified for operation with the device: inductance value (L), inductor saturation current (I SAT), and DC resistance (DCR). A good compromise between size and loss is to choose the peak-to-peak ripple current equals to 20% to 50% of the IC rated current. The switching frequency, input voltage, output voltage, and selected inductor ripple current determines the inductor value as follows : OUT IN OUT IN SW L V( V V )L = Vf I   Once an inductor value is chosen, the ripple current (ΔIL) is calculated to determine the required peak inductor current. OUT IN OUTL IN SW V( V V )I= Vf L L_PEAK OUT_MAX L 1I = I + I 2  IL(PEAK) should not exceed the minimum value of IC's upper current limit level. Besides, the current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. For the selected inductor, the inductor’s saturation and thermal rating should meet or greater than the ripple current (ΔI L). For more conservative, the rating for inductor saturation current must be equal to or greater than switch current limit of the device rather than the inductor peak current. For EMI sensitive application, choosing shielding type inductor is preferred. Input Capacitor Selection Input capacitance, C IN, is needed to filter the pulsating current at the drain of the high-side power MOSFET. CIN should be sized to do this without causing a large variation in input voltage. The waveform of C IN ripple voltage and ripple current are shown in Figure 4. The peak-to-peak voltage ripple on input capacitor can be estimated as equation below : where OUT IN VD = V  CIN OUT OUT IN SW 1DV = D I + I ESR Cf For ceramic capacitors, the equivalent series resistance (ESR) is very low, the ripple which is caused by ESR can be ignored, and the minimum input capacitance can be estimated as equation below :   IN_MIN OUT_MAX CIN_MAX SW D1 DC I Vf =   where ΔVCIN_MAX is maximum input ripple voltage. Figure 4. CIN Ripple Voltage and Ripple Current Richtek’s component specification does not include the following information in the Application Information section. own designs and reserve suitable design margin to ensure the functional suitability of their components and systems.

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. In addition, the input capacitor needs to have a very low ESR and must be rated to handle the worst-case RMS input current of : OUT INRMS OUT_MAX IN OUT V VI I 1 VV   It is common to use the worse I RMS ≅ I OUT/2 at V IN = 2VOUT for design. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size, height and thermal requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. Ceramic capacitors are ideal for switching regulator applications because of its small size, robustness and very low ESR. However, care must be taken when these capacitors are used at the input. A ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. If the RT5753 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the device's rating. This situation is easily avoided by placing the low ESR ceramic input capacitor in parallel with a bulk capacitor with higher ESR to damp the voltage ringing. The input capacitor should be placed as close as possible to the VIN pins, with a low inductance connection to the GND of the IC. In addition to a larger bulk capacitor, a small ceramic capacitors of 0.1μF should be placed close to the VIN and GND pin. This capacitor should be 0402 or 0603 in size. Output Capacitor Selection The RT5753 are optimized for ceramic output capacitors and best performance will be obtained by using them. The total output capacitance value is usually determined by the desired output voltage ripple level and transient response requirements for sag (undershoot on load apply) and soar (overshoot on load release). Output Ripple The output voltage ripple at the switching frequency is a function of the inductor current ripple going through the output capacitor's impedance. To derive the output voltage ripple, the output capacitor with capacitance, C OUT, and its equivalent series resistance, RESR, must be taken into consideration. The output peak-to-peak ripple voltage V RIPPLE, caused by the inductor current ripple ΔIL, is characterized by two components, which are ESR ripple V RIPPLE(ESR) and capacitive ripple VRIPPLE(C), and can be expressed as below : RIPPLE RIPPLE(ESR) RIPPLE(C) RIPPLE(ESR) L ESR LRIPPLE(C) OUT SW V = V V V = I R IV = 8C f If ceramic capacitors are used as the output capacitors, both the components need to be considered due to the extremely low ESR and relatively small capacitance. Output Transient Undershoot and Overshoot In addition to voltage ripple at the switching frequency, the output capacitor and its ESR also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. The ACOT ® transient response is very quick and output transients are usually small. The following section shows how to calculate the worst-case voltage swings in response to very fast load steps. The output voltage transient undershoot and overshoot each have two components : the voltage steps caused by the output capacitor's ESR, and the voltage sag and soar due to the finite output capacitance and the inductor current slew rate. Use the following formula to check if the ESR is low enough (typically not a problem with ceramic capacitors) and the output capacitance is large enough to prevent excessive sag and soar on very fast load step edges, with the chosen inductor value. The amplitude of the ESR step up or down is a function of the load step and the ESR of the output capacitor : V ESR _STEP = ΔIOUT x RESR The amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle. The maximum duty cycle during a fast transient

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Layout Considerations Follow the PCB layout guidelines for optimal performance of the device.  Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. The high current path comprising of input capacitor, high-side FET, inductor, and the output capacitor should be as short as possible. This practice is essential for high efficiency.  Place the input MLCC capacitors as close to the VIN and PGND pins as possible. The major MLCC capacitors should be placed on the same layer as the RT5753.  SW node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the SW node to prevent stray capacitive noise pickup.  Connect feedback network behind the output capacitors. Place the feedback components next to the FB pin.  For better thermal performance, design a wide and thick plane for PGND pin or add a lot of vias to GND plane.  AGND and PGND are connected with a via and at only one point to reduce circulating currents. An example of PCB layout guide is shown from Figure 12. Thermal Considerations In many applications, the RT5753 does not generate much heat due to its high efficiency and low thermal resistance of its WDFN-8L 2x2 and WDFN-8SL 2x2 packages. However, in applications which the RT5753 runs at a high ambient temperature and high input voltage or high switching frequency, the generated heat may exceed the maximum junction temperature of the part. The junction temperature should never exceed the absolute maximum junction temperature of the part. The junction temperature should never exceed the absolute maximum junction temperature T J(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. If the junction temperature reaches approximately 150°C, the RT5753 stops switching the power MOSFETs until the temperature cools down by 20°C. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (TJ(MAX) − TA) / θJA(EFFECTIVE) where TJ(MAX) is the maximum junction temperature of the die. For recommended operating condition specifications, the maximum junction temperature is 150 °C. TA is the ambient temperature, and θJA(EFFECTIVE) is the system- level junction to ambient thermal resistance. It can be estimated from thermal modeling or measurements in the system. The thermal resistance of the device strongly depends on the surrounding PCB layout and can be improved by providing a heat sink of surrounding copper ground. The addition of backside copper with thermal vias, stiffeners, and other enhancements can also help reduce thermal resistance. Experiments in the Richtek thermal lab show that simply set θ JA(EFFECTIVE) as 110% to 120% of the θJA is reasonable to obtain the allowed PD(MAX). As an example, consider the case when the RT5753 is used in applications where V IN = 5V, I OUT = 3A, f SW = by using WE-74437324010 (1 μH, 22mΩ DCR) as the inductor and measured at room temperature. The core  O 2D, RT OUT CORE 1 ηP = P I DCR + P = 1.03Wη    Considering the θJA(EFFECTIVE) is 59.64°C/W by using the RT5753 evaluation board with 4 layers PCB, all layers with 1 oz. Cu, the junction temperature of the regulator operating in a 25°C ambient temperature is approximately : T loss, 16.5mW, can be obtained from its website in this case. In this case, the power dissipation of the RT5753 is

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 12. Layout Guide the VIN and GND pins as possible. network behind the top layer. Add extra vias for thermal Dissipation. plane at only one point to reduce circulating currents.

DS5753-05 November 2023 www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Outline Dimension W-Type 8L DFN 2x2 Package Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.950 2.050 0.077 0.081 D2 1.000 1.250 0.039 0.049 E 1.950 2.050 0.077 0.081 E2 0.400 0.650 0.016 0.026 e 0.500 0.020 L 0.300 0.400 0.012 0.016 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A

©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. RT5753 DS5753-05 November 2023www.richtek.com W-Type 8SL DFN 2x2 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options Min. Max. Min. Max. 0.700 0.800 0.028 0.031 0.000 0.050 0.000 0.002 0.175 0.250 0.007 0.010 0.200 0.300 0.008 0.012 1.900 2.100 0.075 0.083 Option1 1.150 1.250 0.045 0.049 Option2 1.550 1.650 0.061 0.065 1.900 2.100 0.075 0.083 Option1 0.750 0.850 0.030 0.033 Option2 0.850 0.950 0.033 0.037 0.250 0.350 0.010 0.014 0.500 0.020 L b D E e Symbol Dimensions In Millimeters Dimensions In Inches A

DS5753-05 November 2023 www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Footprint Information PABCD S x S y M Package Tolerance Footprint Dimension (mm)Number of Pin PABCD S x S y M Option1 1.30 0.90 Option2 1.60 0.90 Package Tolerance Footprint Dimension (mm)Number of Pin 0.50 2.80 1.30

DS5753-05 November 2023www.richtek.com ©Copyright 2023 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Datasheet Revision History Version Date Description Item 04 2023/1/10 Modify Add RT5753EL, RT5753FL General Description on P1 Features on P1 Simplified Application Circuit on P1 Ordering Information on P2 Marking Information on P4 Functional Block Diagram on P5 Operation on P6, 7, 8, 9 Electrical Characteristics on P11, 12 Typical Application Circuit on P13 Typical Operating Characteristics on p14 Application Information on P21 05 2023/11/7 Modify Electrical Characteristics on P11 Typical Application Circuit on P17