RT5510 RICHTEK | Alldatasheet
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Features
Class-D Speaker AMP 4.8W Output Power @ 9.5V, 8 Load, THD < 1% 6.5W Output Power @ 9.5V, 4 Load, THD < 1% 0/3/6/9/12/15/18dB Boost Gain 20V Output Noise Add DRE to Reduce Output Noise Boost Converter Adaptive Boost for Speaker, Boost from Battery Supply Up to Programmed Voltage, Max 9.5V Accurate Input Current Limit Analog Part : Current Sense, Slope Compensation, Feedback ADC Alternate Mode Supported Digital Part : Voltage Loop and End-Point Prediction in Boost Mode Digital Digital Audio Interface Support I2S, Left-Justified, Right-Justified, TDM and DSPA/B Flexible Interrupt Controller Clip Control (Battery Safeguard) to Prevent Drawing Larger Current from Battery When Low VBAT Watchdog to Monitor Application Process Status and Shutdown the System Volume Control RoHS Compliant and Halogen Free Simplified Application Circuit Control Interface Audio Interface OUTP OUTN 1.8V VBATVBAT DVDD LX SDA SCL LRCK BCK DATAI DATAO RT5510 AGND VREF IOVDDIOVDD DGND PGND BGND LBST CINB CVREF
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Marking Information 5H : Product Code YMDNN : Date Code 5H YM DNN Pin Configuration (TOP VIEW) SDAVBATBGNDBGND SCL WDT/ADS2ADS1LXLX DATAO RSTNVREFVBSTVBST DATAI DGNDAGNDOUTPPVDD LRCK INTVSNSPPGNDPVDD BCK IOVDDVSNSNPGNDOUTN DVDD F4F3F2F1 F5 E4E3E2E1 E5 D4D3D2D1 D5 C4C3C2C1 C5 B4B3B2B1 B5 A4A3A2A1 A5 WL-CSP-30B 2.25x2.60 (BSC) Functional Pin Description Pin No. Pin Name Type Pin Function A1 OUTN O Class-D inverting output. A2, B2 PGND P Power ground. A3 VSNSN I Voltage sense negative input. A4 IOVDD P Digital I/O supply voltage. A 0.1F external capacitor is required. A5 DVDD P Digital supply voltage. A 0.1F external capacitor is required. B1, C1 PVDD P Class-D supply voltage. Voltage is provided by VBST pin. A 22F external capacitor is required. B3 VSNSP I Voltage sense positive input. B4 INT O Interrupt output. B5 BCK I I2S interface bit clock data input. C2 OUTP O Class-D non-inverting output. C3 AGND G Analog ground. C4 DGND G Digital ground. C5 LRCK I I2S interface word select data input. D1, D2 VBST O Boost converter output voltage. D3 VREF P Reference voltage output. A 1F external capacitor is required. D4 RSTN I Hardware reset input, high active. Normally keep low level, go high level for hardware reset. D5 DATAI I I2S interface digital audio data input. E1, E2 LX P Boost converter switch input node. E3 ADS1 I Address select input 1.
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Pin No. Pin Name Type Pin Function E4 WDT/ADS2 I Watchdog input/Address select 2. The RT5510 will latch the level of WDT/ADS2 once 768s after the edge of RSTN pin or analog POR goes from low to high or software reset from high to low for address select function. E5 DATAO O I2S interface digital audio data output. F1, F2 BGND G Boost converter ground. F3 VBAT P Battery supply voltage . Connect 2.7V to 5.5 V battery supply. A 0.1F external capacitor is required. F4 SDA I/O I2C interface data input, Open drain structure. A 4.7k external pull-up resistor is required. F5 SCL I I2C interface clock input, Open drain structure. A 4.7k external pull-up resistor is required. Functional Block Diagram DVDD Signal Path Processing Class-D Preamp PreampVoltage Trim Data Current Trim Data Bandgap Reference Tc Comp. CMP Digital Control DAC VADC IADC Boost Converter PGA IDAC IDAC CMP VBAT & Temp. Sensing Class-G Algorithm & Battery Safeguard PLL Watchdog I2C Interrupt Controller I2S Interface eFuse ADS1 WDT/ADS2 SCL SDA RSTN INT BCK LRCK DATAI DATAO DGND IOVDD BGND LX VBST VBAT PVDD VREF OUTP OUTN VSNSP VSNSN PGND AGND OSC1M VREF LDO
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Operation Class-D Audio Amplifier The RT5510 is a 9.5V boosted class-D audio amplifier capable of delivering up to 4.8W rms output power into an 8 speaker at a supply voltage of 3.6V. The audio amplifier features low noise (20 Vrms). Signal gains are configurable through analog (D_SPK_BOOST[2:0] 0 to 18dB, 3dB/step) and digital (VOLUME[7:0] 12 to 115.5dB, 0.5dB/step) circuits. Over-current protection with threshold of 3A is also implemented in the high efficiency bridge -tied-load (BTL) devices to provide additional protection alongside the current limit of boost convert er. The 3-level PWM scheme supports filter less speaker drive. PLL The on -chip PLL generates the 24.576MHz clock as the internal operating clock source. The PLL uses t he BCK of I 2S interface as the reference clock and the programmability of the PLL allows the support of various sample ra te of audio data, like 8k / 11.025k / 12k / 16k / 22.05k / 24k / 32k / 44.1k / 48k / 88.2k / 96kHz. Combining PLL_N_I and PLL_N_F forms an unsigned number in u13.16 format, which specifies the ratio of 24.576MHz clock over the reference clock, BCK. PLL_CLK = BCK × (PLL_N_I + PLL_N_F 216 ) X (PLL_N_I.PLL_N_F) PLL BCK PLL_CLK = 24.576MHz Over-Voltage Protection The over-voltage (OV) protection detects whether the PVDD voltage exceeds 11.5V to 12.5V. If the OV flag is raised, analog circuits will be shut down. System will check the PVDD voltage and update the status every 200ms. Over-Current Protection The over-current protection can detect the over-current fault on class-D. The fault on the class-D which causes a large current over 3A triggers the OC flag to the digital control system and disable s the analog blocks by 200ms. After 200ms cooling time, the OC protection detects the current again to determinate if the OC event is finished. Under-Voltage Protection The under -voltage protection can detect the under-voltage fault on power supply VBAT. The UV flag is triggered when VBAT is lower than UVLO , then digital control system disable s the analog blocks by 200ms. After 200ms cooling time, the UV protection detects the voltage again to determinate if the UV event is finished. Over-Temperature Protection The over -temperature protection can detect the over-temperature fault on the chip. Th e OT protection is triggered when temperature sensed by TEMP sense is higher than 1 50°C, then the digital control system disables the analog blocks by 200ms. After 200ms cooling time, the OT protection detects the temperature again to determinate if the OT event is finished with the hysteresis threshold 120°C. VBAT Sense The VBAT sense monitors the battery voltage between the range from 2V to 6.375V with 8bit resolution, the output is shown in the register “ 0x48 VBAT” with the equation battery voltage (V) = VBAT code (DEC) / 40. Temp. Sensing Temperature sense monitors the temperature of the chip with the range between 40°C to 175°C with 9-bit resolution, the output is shown in the register “VPTAT” with the equation code = temperature (K) = temperature (°C) + 273.
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Absolute Maximum Ratings (Note 1) Power Dissipation, PD @ TA = 25C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
Electrical Characteristics
(VBAT = 3.6V, Data bit = 24 bits, BCK mode = 64fs, SR = 48kHz, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit System Digital I/O Voltage IOVDD 1.71 1.8 3.6 V Digital Supply Voltage DVDD 1.71 1.8 2 V Speaker Amp Supply Voltage PVDD 2.7 3.6 9.5 V Battery Supply Voltage VBAT 2.7 3.6 5.5 V UVLO for VBAT UVLO 2.1 2.3 2.4 V Iq, Boost in Battery Mode (Note 5) IQ_VBAT VBAT and LX 1 3 5 mA IQ_DVDD 9 12 15 ISD on VBAT ISD_VBAT DVDD = 1.8V 0 0.5 1 A ISD on DVDD ISD_DVDD VBAT = 2.7 to 5.5V, DVDD = 1.8V, BCK = LRCK = DAI = 0V 0 4 20 A ILEAK in Shipping Mode ILEAK VBAT = 4.2V, DVDD = 0V 0 0.5 1 A
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Parameter Symbol Test Conditions Min Typ Max Unit System Efficiency PO = 2.5W, including DC to DC converter, 100Hz audio signal 76 80 84 % Over-Temperature Protection OTP -- 150 -- °C Over-Temperature Protection Hysteresis OTP -- 30 -- °C Boost Boost Output Voltage VBST 2.7 -- 9.5 V VBST Accuracy VBST 0.1 -- 0.1 V Class-D Maximum Output Power PO 1kHz, PVDD = 3.6V, 8 load, 1% THD + N 0.6 0.65 0.7 W 1kHz, PVDD = 9.5V, 8 load, 1% THD + N 4.7 4.8 4.9 1kHz, PVDD = 9.5V, 4 load @ 1% THD + N, VBAT = 4.2V -- 6.5 -- Output Offset Voltage Vos 0 1 3 mV Output Noise Vn A-weighting 15 20 25 V Signal to Noise Ratio SNR PVDD = 9.5V, THD + N < 1%, Gain = 15dB, A-weighting 107 109 111 dB Dynamic Range DR 60dBFS, 1kHz, A-weighting, Gain = 15dB 107 109 111 dB Total Harmonic Distortion + Noise THD+N 1kHz, PO = 350mW, 8 load 90 70 50 dB Power Supply Rejection Ratio PSRRVBAT 217Hz, VBAT ripple = 200mVpp 70 80 95 dB Over-Current Protection of Speaker OCP_SPK OUTP/OUTN short to PVDD or PGND, or OUTP short to OUTN 2.7 3 3.3 A Over-Voltage Protection OVP 11.5 12 12.5 V Current Sense Resolution -- 16 -- Bits Accuracy 1A Ipeak, 25°C, PVDD = 3.6 to 9.5V 3 -- 3 % Temperature Variation 1A Ipeak, 25 to +85°C, PVDD = Signal to Noise Ratio SNR 65 70 75 dB Total Harmonic Distortion + Noise THD+N f = 1kHz, PO = 3W 50 45 40 dB Current Sense Full Scale Peak current which will give full scale digital output 3 -- 3 A Current Sense Gain Linearity f = 1kHz from 50mAp to 1Ap 1.5 -- 1.5 % Voltage Sense Resolution -- 16 -- Bits Accuracy 8V peak voltage 3 -- 3 % Signal to Noise Ratio SNR A-weighting 77 82 87 dB Total Harmonic Distortion + Noise THD+N f = 1kHz, PO = 3W 60 55 50 dB
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Voltage Sense Full scale 12 -- 12 V Voltage Sense Gain linearity f = 1kHz from 0.4Vp to 8Vp -- 1 -- % Battery Sense Resolution -- 8 -- Bits Voltage Resolution 50 -- 50 mV Full Scale Input Voltage -- 6.375 -- V Accuracy VBAT = 3.6V 1 -- 1 % VREF LDO Voltage -- 1.5 -- V Output Capacitor Output is stable 0.5 1 2.5 F I2C Interface Electrical Characteristics (Note 6) SDA, SCL Input Threshold VIH 0.7 x DVDD -- -- V VIL -- -- 0.3 x DVDD Pull-Down Current IFO2 -- 2 -- A Digital Output Low (SDA) VOL IPULLUP = 3mA -- -- 0.4 V Clock Operating Frequency fSCL -- -- 400 kHz Bus Free Time Between Stop and Start Condition tBUF 1.3 -- -- s Hold Time After (Repeated) Start Condition tHD,STA 0.6 -- -- s Repeated Start Condition Setup Time tSU,STA 0.6 -- -- s Stop Condition Time tSU,STD 0.6 -- -- s Data Hold Time tHD,DAT (OUT) 225 -- -- ns Input Data Hold Time tHD,DAT (IN) 0 -- 900 ns Data Setup Time tSU,DAT 100 -- -- ns Clock Low Period tLOW 1.3 -- -- s Clock High Period tHIGH 0.6 -- -- s Clock Data Falling Time tF 20 -- 300 ns Clock Data Rising Time tR 20 -- 300 ns Spike Suppression Time tSP -- -- 50 ns I2S Interface Electrical Characteristics (Note 6) High-Level Input Voltage VIH 0.7 x DVDD -- -- V Low-Level Input Voltage VIL -- -- 0.3 x DVDD V Setup Time, LRCK to SCLK Rising Edge tsu1 10 -- -- ns
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Parameter Symbol Test Conditions Min Typ Max Unit Hold Time, LRCK from SCLK Rising Edge th1 10 -- -- ns Setup Time, SDIN to SCLK Rising Edge tsu2 10 -- -- ns Hold Time, SDIN from SCLK Rising Edge th2 10 -- -- ns Rise/fall Time for SCLK/LRCLK tr -- -- 8 ns Note 1. Continuously stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at T A = 25 C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Quiescent, or ground current, is the difference between input and output currents. It is defined by IQ = IIN - IOUT under no load condition (IOUT = 0mA). The total current drawn from the supply is the sum of the load current plus the ground pin current. Note 6. Guaranteed by design.
Table 1. Recommended Components Information
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Typical Operating Characteristics THD+N vs. Output Power -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1 10 Output Power (W) THD+N (dB) VBAT = 3V, 1kHz, RL = 8 + 33H 40degree 25degree 85degree THD+N vs. Output Power -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1 10 Output Power (W) THD+N (dB) VBAT = 3.6V, 1kHz, RL = 8 + 33H 40degree 25degree 85degree THD+N vs. Output Power -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1 10 Output Power (W) THD+N (dB) VBAT = 4.2V, 1kHz, RL = 8 + 33H 40degree 25degree 85degree THD+N vs. Output Power -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1 10 Output Power (W) THD+N (dB) VBAT = 5.5V, 1kHz, RL = 8 + 33H 40degree 25degree 85degre e THD+N vs. Output Power -90 -80 -70 -60 -50 -40 -30 -20 -10 0.001 0.01 0.1 1 10 Output Power (W) THD+N (dB) VBAT = 3.6V, 1kHz, RL = 8 + 33H DVDD 2VDVDD 1.8V DVDD 1.71V THD+N vs. Frequency -90 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 100000 Frequency (Hz) THD+N (dB) VBAT = 4.2V, Output Power = 0.35W, RL = 8 + 33H 40degree 25degree 85degre e
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Efficiency vs. Output Power 100 0 1 2 3 4 5 Output Power (W) Efficiency (%) VBAT = 3.6V, RL = 8 + 33H, 100Hz input frequency Efficiency with DVDD Efficiency without DVDD THD+N vs. Frequency -90 -80 -70 -60 -50 -40 -30 -20 -10 10 100 1000 10000 100000 Frequency (Hz) THD+N (dB) VBAT = 4.2V, Output Power = 4.8W, RL = 8 + 33H 40degree 25degree 85degre Output Power vs. Battery Supply Voltage 0.0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0 Battery Supply Voltage (V) Output Power (W) Adaptive mode RL = 8 + 33H, PO at THD+N = 1% Battery mode Output Power vs. Battery Supply Voltage Battery Supply Voltage (V) Output Power (W) RL = 4 + 33H, PO at THD+N = 1% Adaptive mode Battery mode PSRR -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 1 10 100 1000 10000 100000 Ripple Frequency (Hz) PSRR (dB) VBAT = 3.6V, RL = 8 + 33H, ripple = 200mVpp on VBAT VBAT = 3.6V, RL = 8, + 33H, PO = 4.3W Boost Output (2V/Div) Boost Change Mode Behavior Time (2.5ms/Div) IVBAT (1A/Div)
Table 2. Address Selection Via Pins ADS1 and WDT/ADS2
0 DVDD 0110101x (35H) 0 : write, 1 : read
Clock Line, Clock signal) are used to perform serial communication between integrated circuits in the system. The corresponding I2C communication pins in the RT5510 are SDA and SCL. only allows transitions when SCL is low level. paragraph for the RT5510 Read / Write function description.
The RT5510 single-byte data-write function format is shown in Figure 3. the single-byte data write function. Figure 3. Single-byte and Multiple-byte I2C Format
block operational status in different modes is depicted in Figure 6. Figure 6. Operation Mode
- When PWDN is set to 1, chip will enter power-down mode.
- Power consumption is minimum and PWM outputs are floating.
- Chip will enter suspend mode.
- Most of the data path are off, and PWM outputs are floating.
- PLL keeps in free-run mode and CK1M is used to monitor BCK/SR
on I2S bus to see if they are correct.
- If set PWDN/AMPE at register 0x03 as condition, chip will enter
operating mode when BCK and sampling rate are valid.
- Chip enters fault mode when an error event of physical protection
mechanisms occurs (OCP/OVP/UVP/OTP).
- The boost and AMP are OFF.
- The system exits from Fault mode after the protection event
released for a checking cycle of about 200ms.
implemented at the start after it enters the operating mode. The above procedure is shown in Figure 9 and ramp is setting by register 0x 28 bit [2:0]. Figure 9. I2S Mode Change without PWDN Table 3. Ramp Control Setting
Table 4. Data Format List mode and frame synchronizer in TDM mode.
- IMON : The current sense signal.
- VMON : The voltage sense signal.
- VBAT : The voltage sense for battery.
- VTEMP : The temperature sense of chip.
- SPKPROT_GAIN : The gain of safeguard for speaker protection.
VTEMP, VBAT, IMON and SPKPROT_GAIN. The SDI signal is only 16bit available for each channel. Figure 10. Only One Smart PA I2S Left-Justified Format disabled. The SDI signal is only 16bit available for each channel. Figure 11. Two Smart PA I2S Standard Format Table 5. TX Data Structuring in I2S Mode
000 VMON[15:0] VTEMP[8:1] VBAT[7:0] IMON[15:0] SPKPROT_GAIN[15:0]
001 DAC_BIQ[23:0] 8’h0 {DC_CUT_DATA[25:0], 8’h0}
010 Hi-Z[31:0] VMON[15:4] IMON[15:4] 8’h00
011 VMON[15:4] IMON[15:4] 8’h0 Hi-Z[31:0]
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com
Application Information
When enable, the watchdog block monitors the edge -to-edge period of the watchdog input signal. If the period between edges is greater than the watchdog timer setting, the watchdog input signal is invalid. It means the protection algorithm is no longer function normally. The boost and speaker amplifier should be automatically disable to prevent damage. When the period between edges of watchdog input signal becomes less than the timer setting, the boost and speaker amplifier will be automatically enable. Please refer to Table 6. Table 6. Amp Behavior Configuration at Watchdog Timeout WD_RESP = 00 The Amp neither mutes nor shut down when the watchdog is triggered. The boost converter’s output voltage is not affected. WD_RESP = 01 The Amp shuts down immediately and the output transition is Hi-Z. The boost converter ramps down to VBAT then enters bypass mode. The boost converter ramps down to VBAT then enters bypass mode. Figure 17. Watchdog Timeout Edge Rate Configuration becomes invalid and the boost and speak amplifier are turned off. In the following period, t3 turns to be less than T. Then, the boost and speaker amplifier are turned on again. Table 7. Boost Mode Selection
the speaker output signal to achieve the best efficiency. the boost converter change mode to determine whether the boost converter output voltage needs to be changed. The boost converter has up to three output voltage configurations that can be set by the user. target 2 voltage. The boost converter has a maximum configurable voltage of 9.5V. determine whether to change the output voltage of the boost converter. reduces the output voltage and is configured to bypass, supplying the load energy directly from the battery. Figure 18. Boost Behavior speaker output signal. This ensures that the speaker output signal gets enough voltage level from boost converter.
Figure 19. DAC and Processing Time Table 8. Boost Output Voltage and Change Mode Threshold
meet the application of RL = 8 and output 4.8W. This limit value can be set lower according to the selected inductor. limited. The CC_MAX value from 0000000 to 0110100 and 1111110 to 1111111 are not allowed for use. Table 9. Boost Current Limitation may cause the system to malfunction or restart. dynamic and vary with battery voltage. When the batt ery voltage is reduced, the class-D output voltage will decay. voltage drop when playing music. excessive output signal will be clipped according to the set clip control parameter.
defined by VBCPS, CPSLP and VBAT. The battery voltage hysteresis can be set via BVHYS register. Figure 22. Clip Threshold Depend on VBAT Table 11. Hard Clipping
8 HARD_CLIP_EN 0 : Disable hard clipping
Figure 23. Signal Hard Clipping DRE technique is used. The DRE, Dynamic Range Expansion, stands for expanding the dynamic range of a signal. end is compressed by the inverse of this ratio.
resistor, this signal via an amplifier and an A/D converter. Both signal output are pin DATAO. Figure 26. Voltage and Current Setting Monitor Structure Table 12. V/ I Sense ADC
3 D_CSADC_EN
2 D_VSADC_EN
Users can use the algorithm and the RT5510 to reach speaker protection. to estimate the speaker excursion. ESR. Choose X5R or X7R temperature characteristic to keep capacitance in higher temperature.
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com When select capacitor, users have to ensure the DC bias characteristics in component datasheet, it will show the capacitance reduction per centage from rating. It is suggested to choose capacitor voltage rating at least 2x the maximum DC voltage application range to avoid capacitance reduction. For boost VBST = 9.5V application, a 10F for input capacitor and a 100nF for DVDD decoupling capacitor are recommended. Boost output capacitor is important for supply Class -D amplifier PVDD power. This capacitor can reduce boost output voltage ripple and keep the boost output voltage stable. If the output capacitance drops to low, the supply power PVDD for class-D amplifier will be too low and get worst performance. The output ripple can be determined as following equation : OUT S OUT IN SOUT C_esr OUT Boost D I T I V D TΔV = + ( + ) rη C 1-D 2 L Boost capacitor connected to BST is important for stability. The CPVDD capacitance is changed by DC bias. When select capacitor, please notice the DC bias characteristics. The recommended minimum CPVDD capacitance is 6F for 3.6W output power, 8F for 4.3W output power, and 10F for 5W output power. Boost Inductor Selection Small size and better efficiency are the major concerns for portable devices, such as the RT5510 is used for mobile phone. The inductor should have low core loss at 1MHz (Min.) and low DCR for better efficiency. The maximum current of inductor is highly depends on the speaker impedance which determines the output current of the boost converter. The inductor saturation current rating should be considered to cover the inductor peak current which can be approximated by the following equation : OUT OUT IN SL_max IN Boost V I V D TI = + η V 2 L The following is the inductor selection reference. The recommended typical inductance is 1H for the RT5510 boost converter. Inductor selection must consider the saturation current and DC resistance specifications. The rating inductance might be reduced by inductor current and heat , please refer to the inductance decrease current and temperature rise current in inductor datasheet. Therefore, please note the input current limit, and don’t let the inductor into saturation state. For system efficiency, it is suggested to choose a low DC resistance component. Thermal Considerations The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calcu lated using the following formula : PD(MAX) = (TJ(MAX) - TA) / JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and JA is the junction-to-ambient thermal resistance. For continuous operation, the maximum operating junc tion temperature indicated under Recommended Operating Conditions is 125 °C. The junction -to-ambient thermal resistance, JA, is highly package dependent. For a WL-CSP-30B 2.25x2.60 (BSC) package, the thermal resistance, JA, is 22.8°C/W on a standard JEDEC 51-7 high effective-thermal-conductivity four-layer test board. The maximum power dissipation at TA = 25°C can be calculated as below : PD(MAX) = (125°C - 25°C) / (29°C/W) = 3.44W for a WL-CSP-30B 2.25x2.60 (BSC) package.
temperature on the maximum power dissipation. Figure 27. Derating Curve of Maximum Power Dissipation
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Place the filter capacitor as close as possible to the VBST pin, then use shortest trace to link the capacitors and the trace width is 20mil at least. Use more vias to connect to main ground to reduce parasitic inductance and resistance. r BCK LRCK DATAO WDT/ ADS2 LX LX BGND DATAI SCL DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT IOVDD DVDD INT Use more vias to connect to Main Ground. CPVDD PVDD Cap 22µF/25V 0805 Connect PVDD to the VBST filter capacitor from an independent path to make sure the voltage feed into PVDD is well filtered. The shortest path may bypass the filter capacitor so that causes higher voltage ripple than expected on PVDD. r BCK LRCK DATAO WDT/ ADS2 LX LX BGND DATAI SCL DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT IOVDD DVDD INT The path from VBST to PVDD do not shorter than filter capacitor, it can cause higher ripple. CPVDD PVDD Cap 22µF/25V 0805 For achieving good audio quality, the ground connection of decoupling capacitors (IOVDD and DVDD caps) should be linked to DGND first before going to main ground. Identically the VREF decoupling capacitor ground connection should be linked to AGND first before going to main ground. The trace width of IOVDD, DVDD and VREF are 6 mil at least.
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 r IOVDD Cap DVDD Cap r r Main Ground DGND AGND TOP 2nd Layer GND 3rd Layer Main Ground Bottom BCK LRCK DATAO WDT/ ADS2 LX LX BGND DATAI SCL DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT IOVDD DVDD INT CIOVDD CDVDD 0.1µF/6.3V 0402 CVREF 1µF/6.3V 0402 VREF Cap Separate three ground planes (PGND and BGND, DGND and AGND) to isolate the noisy ground from other sensitive grounds and route the shortest path for high current return from Power/Boost ground plane before connecting to main ground to make sure the digital and analog circuit get a su fficient clean ground before influence by noisy high current path. Analog ground: - Dedicate a GND plane or trace to isolate other noisy ground. - GND side of VREF decoupling capacitor should be connected to AGND first before going to main ground or connect to main ground directly from GND side of capacitor. CSP device PVDD Cap Main ground layer Power/Boost ground VREF Cap Ground Side of Capacitor Analog ground Ground Side of Capacitor Top Layer 2nd Layer 3rd Layer TOP 2nd Layer GND 3rd Layer Main Ground Bottom 4th Layer
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com CSP device Top Layer 2nd Layer 3rd Layer 4th Layer PVDD Cap Main ground layer Power/Boost ground Digital ground DVDD Cap Power and Boost ground : - Dedicate a GND plane to isolate the noisy ground from other sensitive grounds. - Use multiple vias to connect main ground. Digital ground : - Dedicate a GND plane or trace to isolate other noisy ground. - GND side of DVDD decoupling capacitor should be connected to DGND first before going to main ground or connect to main ground directly from GND side of capacitor. TOP 2nd Layer GND 3rd Layer Main Ground Bottom Ground Side of CapacitorGround Side of Capacitor BCK LRCK DATAO WDT/ADS2 LX LX BGND DVDD DATAI SCL IOVDD INT DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT The traces of OUTA and OUTB should be kept equal width and length . When using the ferrite bead filter, it should be placed close to chip for better EMI performance. For achieving good accuracy for speaker protection, route separates trace from VSNSP and VSNSN to SPK side. Bead 0402 Bead 0402 Cap 0402 Cap 0402 rr BCK LRCK DATAO WDT/ ADS2 LX LX BGND DATAI SCL DGND RSTN SDA VSNSN VSNSP AGND VREF ADS1 PGND PGND OUTP VBST OUTN PVDD PVDD VBST A B C D E F BGND VBAT IOVDD DVDD INT
The RT5510 layout suggestion for 4 layers evaluation board is shown in Figure 28. Figure 28. Suggested 4 Layers PCB Layout
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Register Table Registers Description Address Byte Bits Bits Name Default Type Description 0x00 2 15:12 Reserved 0000 R Reserved 11:8 DEVICE_ID 0000 R/W Device ID 7:0 CHIP_ID[7:0] 11100000 R Chip Revision ID E0 : First version E1 : 2nd version E2 : 3rd version ….. 0x01 1 7:5 Reserved 000 R Reserved
4 PLL_LOCK 0 R 0 : PLL is locked to BCK (default)
1 : PLL is unlocked to BCK
3 BCK_CLOCK_STABLE 0 R 0 : BCK rate stable (default)
1 : BCK rate unstable
2 BCK_VALID 0 R
0 : BCK stable and match with BCK_MODE setting (default) 1 : BCK unstable and miss match with BCK_MODE setting
1 BCK_LOSS 0 R 0 : BCK no loss(default)
1 : BCK loss
0 LRCK_LOSS 0 R 0 : LRCK no loss(default)
1 : LRCK loss 0x03 1
7 SW_RESET 0 R/W
0 : Chip doesn’t Software reset (default) 1 : Chip reset by Software reset 6:4 Reserved 000 R Reserved
3 AMPDS 0 R/W
0 : Enter soft mode before off mode (enable ramp control) (default) 1 : Enter off mode directly (disable ramp control)
2 AMPE 0 R/W
0 : Disable Class-D (default) 1 : Enable Class-D
1 SPKM 0 R/W
0 : Unmute (default) 1 : Force speaker mute (with ramp control)
0 PWDN 1 R/W
0 : Chip enable 1 : Chip power down (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x04 1
7 IF_WDT_EN 1 R/W 0 : Watchdog interrupt disable
1 : Watchdog interrupt enable (default)
6 IF_BCK_STABLE_EN 1 R/W
0 : BCK un-stable interrupt disable 1 : BCK un-stable interrupt enable (default)
5 IF_PLL_LOCK_EN 1 R/W
0 : PLL unlock interrupt disable 1 : PLL unlock interrupt enable (default)
4 IF_UV_EN 1 R/W
0 : Under-voltage interrupt disable 1 : Under-voltage interrupt enable(default)
3 IF_OV_EN 1 R/W
0 : Over-voltage interrupt disable 1 : Over-voltage interrupt enable (default)
2 IF_OCP_EN 1 R/W
0 : AMP NMOS or PMOS over-current interrupt disable 1 : AMP NMOS or PMOS over-current interrupt enable (default)
1 IF_BST_OC_EN 1 R/W
0 : Boost over-current interrupt disable 1 : Boost over-current interrupt enable (default)
0 IF_OT_EN 1 R/W
0 : Over-temperature interrupt disable 1 : Over-temperature interrupt enable (default) 0x05 1
7 IF_WDT 0 R/W1C
Watchdog interrupt flag, write 1 to clear 0 : Chip operating mode (default) 1 : Interrupt flag = 1, WDT invalid
6 IF_BCK_STABLE 0 R/C
BCK un-stable interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, BCK un-stable
5 IF_PLL_LOCK 0 R/C
0 : Chip operating mode (default) 1 : Interrupt flag = 1, PLL unlock
4 IF_UV 0 R/C
Under-voltage interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, protection occurs
3 IF_OV 0 R/C
Over-voltage interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, protection occurs
2 IF_OCP 0 R/C
AMP NMOS or PMOS over-current interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, protection occurs
1 IF_BST_OC 0 R/C
Boost over-current interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, protection occurs
0 IF_OT 0 R/C
Over-temperature interrupt flag 0 : Chip operating mode (default) 1 : Interrupt flag = 1, protection occurs
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x06 1 7:0 CRC8 00000000 R/W I2C write data checksum 0x09 1 7:6 Reserved 00 R Reserved
5 D_UVP_FLAG 0 R
Battery voltage under threshold 0 : Normal (default) 1 : Over threshold, protection occurs
4 D_OVP_FLAG 0 R
Class-D amplifier supply voltage (VDDP) over threshold 0 : Normal (default) 1 : Over threshold, protection occurs
3 OCPP_FLAG 0 R
Class-D output stage high-side OC flag 0 : Normal (default) 1 : Over threshold, protection occurs
2 OCPN_FLAG 0 R
Class-D output stage low-side OC flag 0 : Normal (default) 1 : Over threshold, protection occurs
1 D_OCP_FLAG 0 R
Boost Converter current over threshold 0 : Normal (default) 1 : Over threshold, protection occurs
0 D_OTP_FLAG 0 R
Class-D amplifier temperature over threshold 0 : Normal (default) 1 : Over threshold, protection occurs
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x10 1 7:6 AUD_BIT 00 R/W 00 : 24bits (default) 01 : 20bits 10 : 18bits 11 : 16bits 5:3 BCK_MODE 010 R/W If MODE_DET_EN = 1, the detected BCK mode is read out If MODE_DET_EN = 0, the BCK_MODE is written to indicate the BCK mode 000 : 32fs 001 : 48fs 010 : 64fs (default) 011 : 96fs 100 : 128fs 101 : 256fs Others : Not support 2:0 SR_MODE 011 R/W If MODE_DET_EN = 1, the detected SR is read out If MODE_DET_EN = 0, the SR_MODE is written to indicate the sampling rate 000 : 32k 001 : Not support 010 : 96k/88.2k 011 : 48k/44.1k (default) 100 : 16k 101 : 24k/22.05k 110 : 8k 111 : 12k/11.025k
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x11 1
7 I2S_LOSS_DET_EN 1 R/W
0 : Disable BCK/LRCK LOSS auto-detect 1 : Enable BCK/LRCK LOSS auto-detect (default)
6 BCK_STABLE_CHK_
0 : Disable BCK stable and valid check 1 : Enable BCK stable and valid check (default)
5 MODE_DET_EN 1 R/W
0 : Disable sampling rate auto-detect and write SR_MODE/BCK_MODE to indicate the sampling rate and BCK mode 1 : Enable SR & BCK mode auto-detect and read SR_MODE/BCK_MODE will return the detection result (default)
4 DSP_MODE_SEL 0 R/W 0 : DSP mode A (default)
1 : DSP mode B
3 TDM_OFFSET 0 R/W
The number of bits between the frame sync signal transitioning and data being driven on the data line 0 : The first data can be sampled at the first BCK rising edge after FSYNC rising edge (default) 1 : The first data can be sampled at the second BCK rising edge after FSYNC rising edge 2:0 AUD_FMT 000 R/W 000 : I2S (default) 001 : Left justify mode 010 : Right justify mode 011 : DSP mode 100 : 8 TDM slots (slot #0 to slot #7) 101 : 16 TDM slots (slot #0 to slot #15) 110 : 32 TDM slots (slot #0 to slot #31) 111 : Reserved
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x12 1 7:6 I2SLRS 01 R/W Audio input selection 00 : Left channel 01 : (Left + Right)/2 (default) 10 : Right channel 11 : Reserved 5:3 I2SDOLS 000 R/W DATAO left channel output selection 000 : {IMON[15:0], VTEMP[7:0], VBAT[7:0]} (default) 001 : {DAC_BIQ[23:0], 8'h0} 011 : {VMON[15:0], IMON[15:0]} 100 : {DC_CUT_DATA[25:0], 6’h0} 101 : {SAFE_DATA_OUT[19:0], 12’h0} 110 : {DF_DATA_OUT[21:0], 10’h0} 111 : {DF_DATA_OUT_HC[21:0], 10’h0} 2:0 I2SDORS 000 R/W DATAO right channel output selection 000 : {VMON[15:0], SPKPROT_GAIN[15:0]} (default) 001 : {DC_CUT_DATA[25:0], 8’h0} 100 : {SAFE_DATA_OUT[19:0], 12’h0} 101 : {DF_DATA_OUT[21:0], 10’h0} 110 : {DF_DATA_OUT_HC[21:0], 10’h0} 111 : {DF_DATA_OUT_IN[21:0], 10’h0} 0x13 1 7:6 TDM_RX_LEN 10 R/W RX length control 00 : 1 slot (8bits) 01 : 2 slot (16bits) 10 : 3 slot (24bits) (default) 11 : Reserved
5 Reserved 0 R Reserved
4:0 TDM_RX_LOC 00000 R/W RX location control, indicate which slot the data MSB is loaded in 00000 : Slot 0 (default) 00001 to 11110 : Slot 1 to Slow30 11111 : Slot 31
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x14 2 15:13 Reserved 000 R Reserved 12:8 TDM_TX_LEN 00000 R/W TX length control, indicate how many bytes should be transmitted from slot TDM_TX_LOC 00000 : TX disable (default) 00001 : TX length 1 slots 00010 : TX length 2 slots 00001 to 10000 : TX length 1 to 16 slots Others : Reserved
7 TDM_TEST_EN 0 R/W
0 : TDM TX debug data test mode disable (default) 1: TDM TX debug data test mode enable 6:5 Reserved 00 R Reserved 4:0 TDM_TX_LOC 00000 R/W TX location control, indicate which slot the data MSB is loaded in 00000 : Slot 0 (default) 00001 to 11110 : Slot 1 to Slow30 11111 : Slot 31 0x18 1 7:3 Reserved 00000 R Reserved
2 HPF_VS_EN 1 R/W
0 : Disable HPF for voltage sense 1 : Enable HPF for voltage sense (default)
1 HPF_IS_EN 1 R/W
0 : Disable HPF for current sense 1 : Enable HPF for current sense (default)
0 HPF_AUD_IN_EN 1 R/W 0 : Disable HPF for audio in
1 : Enable HPF for audio in (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x20 1
7 WD_EN 1 R/W 0 : Disable watchdog
1 : Enable watchdog (default)
6 Reserved 0 R Reserved
5:4 WD_TIMEOUT_SEL 10 R/W Configure the minimum edge rate (rising or falling) of WDT pin, if violated, WD_RESP will be triggered 00 : At least one edge occurs every 5ms 01 : At least one edge occurs every 20ms 10 : At least one edge occurs every 35ms (default) 11 : At least one edge occurs every 50ms 3:2 Reserved 00 R Reserved 1:0 WD_RESP 10 R/W If watchdog timeout happened, WD_RESP will guide the behavior of AMP 00 : The Amp neither mutes nor shut down when the watchdog is triggered. The boost converter’s output voltage is not affected. 01 : The Amp shuts down immediately and the output transition is Hi-Z. The boost converter ramps down to VBAT then enters bypass mode. 10 : The Amp mutes according to the configuration of VOLCTRL, instant mute or soft mute. The boost converter ramps down to VBAT then enters bypass mode. (default) 11 : Signal in is multiplied by WD_RP when watchdog timeout is happened, instead of R_VOLUME. 0x21 1 7:0 WD_RP 00101000 R/W Volume during watchdog timeout, downward, 12 to 115.5dB in 0.5dB step, (default 00101000 = 8dB) e.g. 00000000 = 12dB Equation : Volume = (WD_RP (DEC) x 0.5dB) + 12dB 0x24 2 15:9 Reserved 0000000 R Reserved
8 HARD_CLIP_EN 1 R/W 0 : Disable hard clipping
1 : Enable hard clipping(default) 7:0 HARD_CLIP_TH 00000000 R/W Hard Clip threshold if HARD_CLIP_EN = 1 Downward, 12 to 115.5dB in 0.5dB step, (default 00000000 = 12dB) e.g. 00000001 = 11.5dB Equation : Hard Clip threshold = (HARD_CLIP_TH (DEC) x 0.5dB) + 12dB
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x28 1 7:3 Reserved 00000 R Reserved 2:0 VOLCTRL 000 R/W Ramp control when new volume setting is different from old setting : 000 : No ramp up/down (default) 001 : 0.5dB per sample 010 : 0.5dB per 2 samples 011 : 0.5dB per 4 samples 100 : 0.5dB per 8 samples 101 : 0.5dB per 16 samples 110 : 0.5dB per 32 samples 111 : 0.5dB per 64 samples 0x29 1 7:0 VOLUME 00011000 R/W Volume, downward 12 to 115.5dB in 0.5dB step, (default 00011000 = 0dB) e.g. 00000000 = 12dB Equation : Digital volume = (VOLUME (DEC) x 0.5dB) + 12dB 0x30 1 7:4 Reserved 0000 R Reserved 3:1 VBCPS 001 R/W Clip threshold setting 000 : 3.9V 001 : 3.75V (default) 010 : 3.6V 011 : 3.45V 100 : 3.3V 101 : 3.15V 110 : 3V 111 : 2.85V
0 CLPE 1 R/W 0 : Disable clip
1 : Enable clip (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x31 2 15:14 CLIPRR 00 R/W Rate of Vo threshold recover when VBAT return 00 : Increase by 1/8 of original Vo per 1s (default) 01 : Increase by 1/8 of original Vo per 1.5s 10 : Increase by 1/8 of original Vo per 11 : Increase by 1/8 of original Vo per 2.5s 13:12 CLIPDR 00 R/W Rate of Vo threshold drop when VBAT is low 00 : 1/16 of original per sample (default) 01 : 1/8 of original Vo 10 : 1/4 of original Vo 11 : 1 step to target 11:10 BVHYS 00 R/W Battery voltage recovery hysteresis 00 : Battery voltage + 0.05 (default) 01 : Battery voltage + 0.1 10 : Battery voltage + 0.15 11 : Battery voltage + 0.2 9:0 CPSLP 1000000000 R/W Clip slope setting : For example, set clip slope = 12, signal path gain = 11.1 CPSLP value (DEC) = Clip slope × 256 / Signal path gain CPSLP value (Bin) = 0100010100 CPSLP value (Bin) =1000000000 (default), the Clip slope is 22.2. 0x32 2 15:0 VOMIN 16'h1DDD R/W Minimum Clip threshold converted from (V) For example, set minimum clip threshold = 2.85V, signal path gain = 11.1 VOMIN (DEC) = 2.85 × 32768 / Signal path gain VOMIN (HEX) = 20DD Set VOMIN = 1DDD (default), signal path gain = 11.1, minimum clip threshold = 2.59V. 0x3F 1 7:3 Reserved 00000 R Reserved 2:0 T0_SEL 000 R/W The selection of T0, 22 to 29°C 000 : 22°C (default) 001 : 23°C 010 : 24°C 011 : 25°C 100 : 26°C 101 : 27°C 110 : 28°C 111 : 29°C
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x40 1 7:6 BST_TOT 01 R/W Level timeout time in adaptive mode : 00 : 500s 01 : 1ms (default) 10 : 2ms 11 : 4ms 5:4 SLEW_RATE 01 R/W VBST slew rate when using boost mode : 00 : 2.5mV/s 01 : 5mV/s (default) 10 : 10mV/s 11 : 20mV/s
3 PSM_EN 1 R/W 0 : Disable PSM
1 : Enable PSM (default)
2 DCM_EN 1 R/W 0 : Disable DCM
1 : Enable DCM (default) 1:0 BST_MODE 00 R/W Boost mode 00 : Disable (default) 01 : Battery 10 : Fixed 11 : Adaptive 0x41 2 15:12 Reserved 0000 R Reserved 11:6 BST_THT1 100001 R/W VBST target in fixed mode or highest VBST target in adaptive mode 000000 : Disabled 000001 to 100001 : 2.9 + BST_THT1 x 0.2V e.g. 000001 : 3.1V, 100001 : 9.5V (default), 100010 to 111111 : Reserved 5:0 BST_TH1 011011 R/W Boost threshold for BST_THT1 000000 : Disabled 000001 to 100001 : 1.3 + BST_TH1 x 0.2V e.g. 000001 : 1.5V, 100001 : 7.9V, 011011 : 6.7V (default), 100010 to 111111 : Reserved 0x42 2 15:12 Reserved 0000 R Reserved 11:6 BST_THT2 010111 R/W Middle VBST target in adaptive mode 000000: Disabled 000001 to 100001 : 2.9 + BST_THT2 x 0.2V e.g. 000001 : 3.1V, 100001 : 9.5V, 010111 : 7.5V (default), 100010 to 111111 : Reserved 5:0 BST_TH2 001111 R/W Boost threshold for BST_THT2 000000 : Disabled 000001 to 100001 : 1.3 + BST_TH2 x 0.2V e.g. 000001 : 1.5V, 100001 : 7.9V, 001111 : 4.3V (default) 100010 to 111111 : Reserved
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0x43 2 15:12 Reserved 0000 R Reserved 11:6 BST_THT3 001011 R/W Lowest VBST target in adaptive mode 000000 : Disabled 000001 to 100001 : 2.9 + BST_THT3 x 0.2V e.g. 000001 : 3.1V, 100001 : 9.5V, 001011 : 5.1V (default), 100010 to 111111 : Reserved 5:0 BST_TH3 000111 R/W Boost threshold for BST_THT3 000000 : Disabled 000001 to 100001 : 1.3 + BST_TH3 x 0.2V e.g. 000001 : 1.5V, 100001 : 7.9V, 000111 : 2.7V (default), 100010 to 111111 : Reserved 0x45 1
7 Reserved 0 R Reserved
6:0 CC_MAX 1100111 R/W The IDAC1 peak value 0110101 : 2A 1000011 : 2.5A 1010001 : 3A 1011111 : 3.5A 1100111 : 4A (default) 1101111 : 4.5A 1111101 : 5A 0x46 1
6 OTP_MODE 0 R/W
0 : Digital OTP to trigger auto-recovery (default) 1 : Analog OTP flag to trigger auto-recovery
5 BST_OCP_MODE 1 R/W
0 : Boost digital OCP if OCP_PROT_EN = 1 1 : Boost Analog OCP for limit PWM duty (without OCP) (default)
4 AMP_OCP_PROT_EN 1 R/W
0 : Disable speaker OCP protection 1 : Enable speaker OCP protection (default)
3 OVP_PROT_EN 1 R/W 0 : Disable OVP protection
1 : Enable OVP protection (default)
2 UVP_PROT_EN 1 R/W 0 : Disable UVP protection
1 : Enable UVP protection (default)
1 BST_OCP_PROT_EN 1 R/W
0 : Disable boost OCP protection 1 : Enable boost OCP protection (default)
0 OTP_PROT_EN 1 R/W 0 : Disable OTP protection
1 : Enable OTP protection (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Address Byte Bits Bits Name Default Type Description 0x47 2 15:9 Reserved 0000000 R Reserved 8:0 VPTAT 000000000 R VPTAT code (DEC) = Chip temperature (°C) + 273°C e.g. VPTAT code = 100101010, VPTAT code (DEC) = 298, chip temperature = 25°C 0x48 1 7:0 VBAT 00000000 R Battery voltage (V) = VBAT code (DEC) / 40 e.g. 10100000 = 160 (DEC), Battery voltage = 160 / 40 = 4V 0x68 1 7:5 Reserved 000 R Reserved
4 Time out_disable 0 R/W
0 : Enter DRE if timeout to find zero crossing (default) 1 : Not enter DRE if timeout to find zero crossing
3 DRE_method_sel 0 R/W
0 : Enter DRE at zero crossing (default) 1 : Enter DRE if signal < threshold 2:1 DRE_HOLD_SEL 10 R/W Hold time before entering DRE 00 : 16ms 01 : 32ms 10 : 64ms (default) 11 : 128ms
0 DRE_EN 1 R/W 0 : Disable DRE
1 : Enable DRE (default) 0x69 1 7:0 DRE_THDMODE 01000000 R/W Threshold = 20log (DRE_THDMODE (DEC) × 2 ^ (11)), DRE_THDMODE= 30.1dB (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Address Byte Bits Bits Name Default Type Description 0xA3 1 7:5 D_SPK_BOOST[2:0] 101 R/W Class-D gain control [000:110] = 0 to 18dB, 3dB per step 000 : 0dB 001 : 3dB 010 : 6dB 011 : 9dB 100 : 12dB 101 : 15dB (default) 110 : 18dB Others : Reserved
4 Reserved 0 R Reserved
3 D_CSADC_EN 1 R/W
0 : Disable 1 : Enable (default)
2 D_VSADC_EN 0 R/W
0 : Disable (default) 1 : Enable
1 D_SPK_DC_TRACE_
0 : Disable 1 : Enable (default)
0 D_EN_TRIWAVE 1 R/W
Enable triangle wave generator 0 : Disable 1 : Enable (default)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS5510-00 October 2019 www.richtek.com Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.500 0.600 0.020 0.024 A1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 D 2.560 2.640 0.101 0.104 D1 2.000 0.079 E 2.210 2.290 0.087 0.090 E1 1.600 0.063 e 0.400 0.016 30B WL-CSP 2.25x2.60 Package (BSC)
Copyright © 2019 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5510-00 October 2019 Footprint Information Package Number of Pin Type Footprint Dimension (mm) Tolerance e A B WL-CSP2.25x2.60-30(BSC) 30 NSMD 0.400 0.240 0.340 ±0.025 SMD 0.270 0.240 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is curre nt and complete. Richtek cannot as sume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its su bsidiaries.