Power Management

RT5045A

Richtek Technology Corp...

Power Management Unit Total Power Solution for SSD

Manufacturer: Richtek Technology Corp...

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Features

 Supply Input Voltage Range : 2.9V to 5.5V  Six High Efficiency, Low Voltage Buck Converters  Up to 85% Efficiency at 10mA, and at Half Rated Output Current  CH1 : 2.3V to 3V in 25mV step, Output 4A max.  CH2 : 0.9V to 1.6V in 25mV step, Output 1A max.  CH3 : 1.5V to 2.1V in 25mV step, Output 1A max.  CH4 : 0.7V to 1.3V in 25mV step, Output 2A max.  CH5 : 0.7V to 1.3V in 25mV step, Output 1A max.  CH6 : 0.7V to 1.3V in 25mV step, Output 3.5A max.  CH2/3 2MHz CH4/5/6 2.5MHz Default Switching Frequency and Programmable 1 to 3MHz  2MHz Default Switching Freq uency and Programmable 0.8 to 2.3MHz (CH1)  VSEL0 & VSEL1 for Programmable Default Output Voltage  One low quiescent current LDO with Output 200mA max.  Low Power Mode (LPM) for Ultra Low Quiescent Current  High-speed I 2C Interfaces for Programming Outputs  POR Threshold Select ion and Open-Drain POR Indicator  Power Sequence Control During Startup  OVP , UVP, UVLO  Thermal Shutdown Protection Simplified Application Circuit LDO CH1 SSD PVIN1 PVIN2 PVIN3 PVIN4 PVIN5 PVIN6 AVDD SCL SDA VSEL0 VSEL1 PORSEL POR I2C VR Volt Default Setting POR Vth Selection POR Information PVIN AVIN RT5045A SW1 FB1 CH2 SW2 FB2 CH3 SW3 FB3 CH4 SW4 FB4 CH5 SW5 FB5 CH6 SW6 FB6

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 Pin Configurations (TOP VIEW) VSEL0PORSELPGND LDO FB1 PGND1 LX1 PVIN1 SCL SDA AGND AVDD AGND VSEL1 PGND6 LX6 POR PVIN6 PGND FB2 PGND2 PGND PGND PGND6 LX6 FB6 PVIN6 FB5 LX5 PGND5 PVIN2 FB3 PVIN3 LX3 PGND3/4 LX4 PVIN4 FB4 LX2 PGND PVIN3 LX3 PGND3/4 LX4 PVIN4 PVIN5 PGND PGND1 LX1 PVIN1 PGND PGND WL-CSP-52B 3.19x3.59 (BSC) Marking Information RT5045AWSC : Product Number YMDNN : Date CodeRT5045A WSC YMDNN

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Functional Pin Description Pin No. Pin Name Pin Function A1 LDO LDO Output. A2 SCL I2C Interface Clock Signal. A3 SDA I2C Interface Data Signal. A4, A6 AGND Analog Ground. A5 AVDD Analog Power Input for Control Logic and LDO Input. A7 POR Power On Reset Information. When AVDD > VPORTH, POR = high level. When AVDD < VPORTH – 100mV, POR = low level. A8 FB6 CH6 Buck Converter Output Voltage Feedback Input. B1 FB1 CH1 Buck Converter Output Voltage Feedback Input. B2, B3, E7, F2, F7, G2, G7, H2 PGND Power Ground. B4 PORSEL POR Threshold Voltage Select. B5 VSEL0 Power Rails Default Voltage Select Pin0. Pull down resistance 1.5M typ. B6 VSEL1 Power Rails Default Voltage Select Pin1. Pull down resistance 1.5M typ. B7, B8 PGND6 CH6 Buck Converter Power Ground. C1, C2 PGND1 CH1 Buck Converter Power Ground. C7, C8 LX6 CH6 Buck Converter Switched Output. D1, D2 LX1 CH1 Buck Converter Switched Output. D7, D8 PVIN6 CH6 Buck Converter Input. E1, E2 PVIN1 CH1 Buck Converter Input. E8 FB5 CH5 Buck Converter Output Voltage Feedback Input. F1 FB2 CH2 Buck Converter Output Voltage Feedback Input. F8 PGND5 CH5 Buck Converter Power Ground. G1 PGND2 CH2 Buck Converter Power Ground. G8 LX5 CH5 Buck Converter Switched Output. H1 LX2 CH2 Buck Converter Switched Output. H3, J3 PVIN3 CH3 Buck Converter Input. H4, J4 LX3 CH3 Buck Converter Switched Output. H5, J5 PGND3/4 CH3 and CH4 Buck Converter Power Ground. H6, J6 LX4 CH4 Buck Converter Switched Output. H7, J7 PVIN4 CH4 Buck Converter Input. H8 PVIN5 CH5 Buck Converter Input. J1 PVIN2 CH2 Buck Converter Input. J2 FB3 CH3 Buck Converter Output Voltage Feedback Input. J8 FB4 CH4 Buck Converter Output Voltage Feedback Input.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 Function Block Diagram LX1 PGND1 FB1 PVIN1 CH1 LX4 PGND4 FB4 PVIN4 CH4 LDO AVDD LDO POR 0.7V to 1.3V AVDD AGND Power Control LX5 PGND5 FB5 PVIN5 0.7V to 1.3V CH5 LX6 PGND6 FB6 PVIN6 0.7V to 1.3V 3.5A CH6 1.656V to 2.16V 2.3V to 3V 0.2A 2.3V to 3V LX2 PGND2 FB2 PVIN2 CH2 0.9V to 1.6V LX3 PGND3 FB3 PVIN3 CH3 1.5V to 2.1V I2C Voltage Select POR Select SCL SDA VSEL0 VSEL1 PORSEL

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Operation The RT5045A provides six synchronous Buck regulators and one LDO to satisfy the entire power system of SSD. This device can communicate with processors through I2C interface for programming the voltage, monitoring the status, or in/out the power saving mode. Buck Converter The RT5045A incorporates six high -efficiency synchronous switching Buck converters that deliver various voltages. CH1 features peak current mode architecture of Buck converter. For preventing the unstable when duty > 50% traditionally, it adds external ramp and compensation to reduce duty cycle perturbation and stabilize the current loop. CH1 can operate up to 100% duty to let the lowest input voltage still maintain the regulator work. And the output voltage will be the lowest input voltage decreases dropout voltage on the resistance of current path. Unlike CH1, the control scheme of other buck converters are constant-on-time current mode for low output vo ltage, quick transient response. The buck converters have a full set of protection. Buck Over-Current Protection The buck converters provides over current protection by detecting low-side MOSFET valley inductor current for CH2~CH6 and by detection high -side MOSFET peak current for CH1. If the sensed inductor current is over the current limit threshold, the OCP will be triggered. When OCP is tripped, the buck converter will keep the over current threshold level until the ove r current condition is removed. Buck Under Voltage Protection The output voltages are c ontinuously monitored for under voltage protection. If the output voltage falls below 60% of the reference voltage, under voltage protection is triggered and then the high -side and low- side MOSFET will turn off. The UVP circuit will turn off all rails and latched. The way to cannel the latched behavior is to re-give AVDD power of RT5045A. Buck Output Over Voltage Protection The output voltages are continuously monitored for over voltage protection. If the output voltage exceeds 120% of the reference, over voltage protection is triggered and then the high -side and low-side MOSFET will turn off. The power MOS will keep turn off until the over voltage condition is removed. Linear Dropout Regulator The RT5045A includes one performance linear dropout regulators. The LDO contains an independent current limit and under voltage protection circuit to prevent unexpected applications. When the path current is over the current limit, the current limit circuit fixes the gate voltage to limit the output current. And if t he output voltage is less than 60% of reference voltage, the UVP circuit will shut-down all rails and latched. The way to cannel the latched behavior is to re-give AVDD power of RT5045A. Over-Temperature Protection If the temperature of the buck converter is over 150°C, the OTP circuit acts and makes all power rails shutdown. They recover back with power -up sequence when the temperature of PMIC is low to 125°C. VSEL0, VSEL1 The RT5045A applies four set default output voltages for all power rails when the d evice starts a power up sequence. PORSEL PORSEL is a logic pin to select the threshold voltage of AVDD to raise POR signal. If AVDD voltage is over the threshold voltage, the device starts a POR rising function. When set PORSEL = 1, the threshold voltage of AVDD is 3.8V, else the threshold voltage is 2.8V. POR POR pin is a signal to inform the system that the power up sequence of the RT5045A is completed. If AVDD voltage is larger than the POR rising threshold voltage, the POR will go high with a timing delay. If AVDD voltage is less than POR falling threshold voltage, the POR falls right away.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 Absolute Maximum Ratings (Note 1)  Power Dissipation, PD @ TA = 25C  Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)

Electrical Characteristics

(AVDD = 3.3V, PVIN = 3.3V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit PMIC AVDD Supply Voltage VAVIN 2.9 3.3 5.5 V AVDD Supply Current IAVIN All Voltage Rails off -- 15 25 A AVDD Supply Current in Sleep Mode CH5 = LPM, other voltage rails off -- 15 25 A VSEL0, VSEL1, PORSEL High VIH Logic signal rising threshold 1.2 -- -- V VSEL0, VSEL1, PORSEL Low VIL Logic signal falling threshold -- -- 0.4 V AVDD UVLO Hysteresis Hysteresis -- 100 -- mV AVDD UVLO Threshold VAVUV POR_OPTION = 0, PORSEL = 0, UVLO falling 2.673 2.7 2.727 V POR_OPTION = 0, PORSEL = 1, UVLO falling 3.663 3.7 3.737 AVDD UVLO Hysteresis Hysteresis -- 100 -- mV POR Threshold VPORTH POR_OPTION = 0, PORSEL = 0, POR falling 2.673 2.7 2.727 V POR_OPTION = 0, PORSEL = 1, POR falling 3.663 3.7 3.737 POR Hysteresis Hysteresis -- 100 -- mV POR Output Low VPORLO Sink current = 5mA -- -- 0.4 V

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit POR Rising Delay Time AVDD > VPORTH, detect the POR rising edge. VSEL = 0, VSEL1 = 0 9 10 11 ms Thermal Shutdown Threshold TSD -- 150 -- C Thermal Shutdown Hysteresis -- 25 -- C CH1 (4A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 2.3 -- 3 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 2.5 +2% V DC Output Voltage Programmable step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 2.5V, L = 0.47H, COUT = 22F x 2, IOUT = 0.2 to 1.5A at SR = 0.13A/s -- -- 84 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 35 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 18 -- m Current Limit IOC Peak current, IMAX[6:5] = 10 5 5.8 -- A Switching Frequency FSW FREQ[2:0] = 110 1.8 2 2.2 MHz Minimum On-Time TON -- 150 200 ns OVP Trip Threshold VOVP OVP detected 115 120 125 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance -- 50 --  Efficiency VIN = 3.3V, VOUT = 2.5V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 2.5V, Load = 1A 90 -- -- CH2 (1A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 0.9 -- 1.6 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 1.35 +2% V DC Output Voltage Programmable Step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 Parameter Symbol Test Conditions Min Typ Max Unit Transient Load Regulation VIN = 3.3V, VOUT = 1.5V -- -- 75 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 40 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 20 -- m Current Limit IOC Valley current, IMAX[6:5] = 10, 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 101 1.8 2 2.2 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP OVP detected 120 125 130 % OVP Propagation Delay TOVPDLY 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance -- 100 --  Efficiency VIN = 3.3V, VOUT = 1.5V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1.5V, Load = 500mA 85 -- -- CH3 (1A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 1.5 -- 2.1 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 1.8 +2% V DC Output Voltage Programmable step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1.8V -- -- 90 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 45 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 25 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 101 1.8 2 2.2 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP OVP detected 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance -- 50 --  Efficiency VIN = 3.3V, VOUT = 1.8V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1.8V, Load = 500mA 85 -- --

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit CH4 (2A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 0.7 -- 1.3 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 1 +2% V DC Output Voltage Programmable step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 45 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 25 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2.5 3 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP OVP detected 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance TDIS -- 150 --  Efficiency VIN = 3.3V, VOUT = 1V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1V, Load = 1A 85 -- -- CH5 (1A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 0.7 -- 1.3 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 1 +2% V DC Output Voltage Programmable Step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 50 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 30 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 2 2.5 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 Parameter Symbol Test Conditions Min Typ Max Unit OVP Trip Threshold VOVP OVP detected 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance -- 150 --  Efficiency VIN = 3.3V, VOUT = 1V, Load = 1mA, LPM 85 -- -- VIN = 3.3V, VOUT = 1V, Load = 500mA 85 -- -- CH6 (3.5A) AVDD Quiescent Current IINQ Enable, no switching , not include IAVIN -- 25 35 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 10 20 A Output Voltage Scaling Controlled by I2C 0.7 -- 1.3 V Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 1 +2% V DC Output Voltage Programmable Step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation Force PWM -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 1V -- -- 50 mV H/S Switch On Resistance RDS(ON)H VIN = 5V -- 40 -- m L/S Switch On Resistance RDS(ON)L VIN = 5V -- 20 -- m Current Limit IOC Valley current, IMAX[6:5] = 10 4.5 5 -- A Switching Frequency FSW FREQ[2:0] = 110 2.2 2.5 2.75 MHz Minimum Off-Time TOFF -- 120 160 ns OVP Trip Threshold VOVP OVP detected 120 125 130 % OVP Propagation Delay TOVPDLY -- 1 -- s UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.5 0.8 ms Discharge Resistance -- 150 --  Efficiency VIN = 3.3V, VOUT = 1V, Load = 10mA 85 -- -- VIN = 3.3V, VOUT = 1V, Load = 1A 85 -- -- LDO (0.2A) AVDD Quiescent Current IINQ Enable, not include IAVIN -- 28 38 A AVDD LPM Quiescent IINLP LPM enable, not include IAVIN -- 15 25 A Output Voltage Scaling VSEL0 = 0, VSEL1 = 0 VSEL0 = 0, VSEL1 = 1 2.3 -- 3 V VSEL0 = 1, VSEL1 = 0 VSEL0 = 1, VSEL1 = 1 1.656 -- 2.16

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Default VOUT VSEL0 = 0, VSEL1 = 0 2% 2.5 +2% V DC Output Voltage Programmable Step VSTEP -- 25 -- mV Line Regulation -- 0.5 -- %/V Load Regulation -- 0.5 -- %/A Transient Load Regulation VIN = 3.3V, VOUT = 2.5V, Load = 20mA to 180mA during 5s -- -- 125 mV Dropout Voltage VDROP VIN = 3.3V, VOUT = 2.5V Load = 200mA -- 100 200 mV Current Limit IOC -- 0.4 -- A UVP Trip Threshold VUVP UVP detected 55 60 65 % UVP Propagation Delay (Note 5) TUVPDLY -- 2 -- s Soft-Start Time TSS -- 0.3 0.6 ms Discharge Resistance TDIS -- 100 --  Power Supply Rejection Rate PSRR Load = 100mA, F = 100Hz -- 50 -- dB Load = 100mA, F = 100kHz -- 28 -- I2C for Fast Mode Parameter Symbol Test Conditions Min Typ Max Unit SDA, SCL Input Voltage High-Level 1.2 -- -- V Low-Level -- -- 0.4 Fast Mode SCL Clock Rate fSCL -- -- 400 kHz Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD;STA 0.6 -- -- s LOW Period of the SCL Clock tLOW 1.3 -- -- s HIGH Period of the SCL Clock tHIGH 0.6 -- -- s Set-Up Time for a Repeated START Condition tSU;STA 0.6 -- -- s Data Hold Time tHD;DAT 0 -- 0.9 s Data Set-Up Time tSU;DAT 100 -- -- ns Set-Up Time for STOP Condition tSU;STO 0.6 -- -- s Bus Free Time between a STOP and START Condition tBUF 1.3 -- -- s Rising Time of both SDA and SCL Signals tr 20 -- 300 ns Falling Time of both SDA and SCL Signals tf 20 -- 300 ns SDA and SCL Output Low Sink Current IOL SDA or SCL Voltage = 0.4V 2 -- -- mA

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 I2C High Speed Mode Parameter Symbol Test Conditions Min Typ Max Unit SDA, SCL Input Voltage High-Level 1.2 -- -- V Low-Level -- -- 0.4 High Speed Mode SCL Clock Rate fSCL -- -- 3.4 MHz Hold Time (Repeated) START Condition. After this Period, the First Clock Pulse is Generated tHD;STA 160 -- -- ns LOW Period of the SCL Clock tLOW 160 -- -- ns HIGH Period of the SCL Clock tHIGH 60 -- -- ns Set-Up Time for a Repeated START Condition tSU;STA 60 -- -- ns Data Hold Time tHD;DAT 0 -- 70 ns Data Set-Up Time tSU;DAT 10 -- -- ns Set-Up Time for STOP Condition tSU;STO 160 -- -- ns Rising Time of both SDA and SCL Signals tr 10 -- 80 ns Falling Time of both SDA and SCL Signals tf 10 -- 80 ns SDA and SCL Output Low Sink Current IOL SDA or SCL Voltage = 0.4V 2 -- -- mA Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Design Guaranteed.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Typical Application Circuit RT5045AH7, J7 PVIN4PVIN E1, E2PVIN1 PVIN D1, D2LX1 CH1, 4A B1FB1 0.47µH VSEL1B6 VSEL0B5 SDAA3 SCLA2 PGND 10µF LX4CH4, 2A J8 FB4 0.47µH H6, J6 22µF J5 PGND4 C1, C2PGND1 10µF x 2 22µF x 2 H8 PVIN5PVIN J1PVIN2 PVIN H1LX2 CH2, 1A F1FB2 0.47µH 10µF LX5CH5, 1A E8 FB5 0.47µH G8 22µF F8 PGND5 G1PGND2 10µF 22µF D7,D8 PVIN6PVIN H3, J3PVIN3 PVIN H4, J4LX3 CH3, 1A J2FB3 0.47µH 10µF x 2 LX6CH6, 3.5A A8 FB6 0.47µH C7, C8 22µF x 2 B7, B8 PGND6 H5PGND3 10µF 22µF PORA7 PORSELB4 2.2k2.2k100k AVIN A5AVDD AVIN 2.2µF A4, A6AGND A1LDO LDO, 0.2A 4.7µF B2, B3, E7, F2, F7, G2, G7, H2

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 2. POWER_GOOD_REG Description : Power good information register. When Voltage Rails achieve 90% of VID target, the relative bit will set to 1. Table 3. CH1_CFG_REG Description : CH1 config register. Set CH1 current limited, VID change slew rate, PWM frequency.

7 Reserved Reserved bit

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 4. CH1_SEL_REG Description : CH1 VID setting register. CH1 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 5. CH2_CFG_REG Description : CH2 config register. Set CH2 current limited, VID change slew rate, PWM frequency.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 6. CH2_SEL_REG Description : CH2 VID setting register. CH2 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 7. CH3_CFG_REG Description : CH3 config register. Set CH3 current limited, VID change slew rate, PWM frequency.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 8. CH3_SEL_REG Description : CH3 VID setting register. CH3 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 9. CH4_CFG_REG Description : CH4 config register. Set CH4 current limited, VID change slew rate, PWM frequency.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 10. CH4_SEL_REG Description : CH4 VID setting register. CH4 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 11. CH5_CFG_REG Description : CH5 config register. Set CH5 current limited, VID change slew rate, PWM frequency.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 12. CH5_SEL_REG Description : CH5 VID setting register. CH5 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 13. CH6_CFG_REG Description : CH6 config register. Set CH6 current limited, VID change slew rate, PWM frequency.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 14. CH6_SEL_REG Description : CH6 VID setting register. CH5 VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 15. LDO_SEL_REG Description : LDO VID setting register. LDO VID setting and power on/off status and control.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 16. DCDCCTRL0_REG Description : DCDC high/low power mode control register.

7 CH1_ EN 0 : Disable

6 CH2_ EN 0 : Disable

5 CH3_ EN 0 : Disable

4 CH4_ EN 0 : Disable

3 CH5_ EN 0 : Disable

2 CH6_ EN 0 : Disable

1 LDO_ EN 0 : Disable

0 Reserved Reserved bit

7 CH1_ ALIVE 0 : When Sleep bit = 1 , CH1 turn off

6 CH2_ ALIVE 0 : When Sleep bit = 1 , CH2 turn off

5 CH3_ ALIVE 0 : When Sleep bit = 1 , CH3 turn off

4 CH4_ ALIVE 0 : When Sleep bit = 1 , CH4 turn off

3 CH5_ ALIVE 0 : When Sleep bit = 1 , CH5 turn off

2 CH6_ ALIVE 0 : When Sleep bit = 1 , CH6 turn off

1 LDO_ ALIVE 0 : When Sleep bit = 1 , LDO turn off

0 SLEEP 0 : Exit sleep mode

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 18. DCDCCTRL1_REG Description : DCDC PSKIP/PWM mode control register. 7 CH1_PWM CH1_PWM[7] = 0 : PSKIP mode. 6 CH2_ PWM CH2_PWM[6] = 0 : PSKIP mode. 5 CH3_ PWM CH3_PWM[5] = 0 : PSKIP mode. 4 CH4_ PWM CH4_PWM[4] = 0 : PSKIP mode. 3 CH5_ PWM CH5_PWM[3] = 0 : PSKIP mode. 2 CH6_ PWM CH6_PWM[2] = 0 : PSKIP mode. Table 19. DISCHARGE_REG Description : Discharge enable register.

7 CH1_DIS CH1_DIS[7] = 0 : discharge path disable

6 CH2_DIS CH2_DIS[6] = 0 : discharge path disable

5 CH3_DIS CH3_DIS[5] = 0 : discharge path disable

4 CH4_DIS CH4_DIS[4] = 0 : discharge path disable

3 CH5_DIS CH5_DIS[3] = 0 : discharge path disable

2 CH6_DIS CH6_DIS[2] = 0 : discharge path disable

1 LDO_DIS LDO_DIS[1] = 0 : discharge path disable

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 20. POR_OPTION_REG Description : POR_OPTION select register. POR_OPTION_SEL[1:0] = 01, reserved. Table 21. DCDCTRL2_REG Description : DCDC high/low power mode control register. 7 CH1_LPM CH1_LPM[7] = 0 : active high power mode. CH1_LPM[7] = 1 : active low power mode. 6 CH2_LPM CH2_LPM[6] = 0 : active high power mode. CH2_LPM[6] = 1 : active low power mode. 5 CH3_LPM CH3_LPM[5] = 0 : active high power mode. CH3_LPM[5] = 1 : active low power mode. 4 CH4_LPM CH4_LPM[4] = 0 : active high power mode. CH4_LPM[4] = 1 : active low power mode. 3 CH5_LPM CH5_LPM[3] = 0 : active high power mode. CH5_LPM[3] = 1 : active low power mode. 2 CH6_LPM CH6_LPM[2] = 0 : active high power mode. CH6_LPM[2] = 1 : active low power mode. 1 LDO_LPM LDO_LPM[1] = 0 : active high power mode. LDO_LPM[1] = 1 : active low power mode.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 25. LDO Wake-up_time Table 26. PRODUCT_ID_REG Description : Product ID number register.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 27. MANUFACTURER_ID_REG Description : Manufacturer ID number register. Table 28. REVISION_NUMBER_REG Description : Revision number register.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Typical Operating Characteristics CH1 Efficiency vs. Output Current 100 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) Efficiency (%) VOUT = 2.5V VIN = 3.3V VIN = 5V CH2 Efficiency vs. OutputCurrent 100 Output Current (A) Efficiency (%) VOUT = 1.35V VIN = 3.3V VIN = 5V CH3 Efficiency vs. Output Current 100 Output Current (A) Efficiency (%) VOUT = 1.8V VIN = 3.3V VIN = 5V CH4 Efficiency vs. Load Current 100 Load Current (A) Efficiency (%) VOUT = 1V VIN = 3.3V VIN = 5V CH5 Efficiency vs. Output Current 100 Output Current (A) Efficiency (%) VOUT = 1V VIN = 3.3V VIN = 5V CH6 Efficiency vs. Output Current 100 0.5 1 1.5 2 2.5 3 3.5 Output Current (A) Efficiency (%) VOUT = 1V VIN = 3.3V VIN = 5V

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 CH1 Output Voltage vs. Output Current 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) Output Voltage (V) VOUT = 2.5V VIN = 3.3V VIN = 5V CH2 Output Voltage vs. Output Current 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 0 0.2 0.4 0.6 0.8 1 Output Current (A) Output Voltage (V) VOUT = 1.35V VIN = 3.3V VIN = 5V CH3 Output Voltage vs. Output Current 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 0 0.2 0.4 0.6 0.8 1 Output Current (A) Output Voltage (V) VOUT = 1.8V VIN = 3.3V VIN = 5V CH4 Output Voltage vs. Output Current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 Output Current (A) Output Voltage (V) VOUT = 1V VIN = 3.3V VIN = 5V CH5 Output Voltage vs. Output Current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.2 0.4 0.6 0.8 1 Output Current (A) Output Voltage (V) VOUT = 1V VIN = 3.3V VIN = 5V CH6 Output Voltage vs. Output Current 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0 0.5 1 1.5 2 2.5 3 3.5 4 Output Current (A) Output Voltage (V) VOUT = 1V VIN = 3.3V VIN = 5V

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com CH1 Output Voltage vs. Input Voltage 2.45 2.46 2.47 2.48 2.49 2.50 2.51 2.52 2.53 2.54 2.55 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 2.5V IOUT = 1A IOUT = 2A IOUT = 4A CH2 Output Voltage vs. Input Voltage 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 1.35V IOUT = 0.5A IOUT = 1A CH3 Output Voltage vs. Input Voltage 1.75 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 1.8V IOUT = 0.5A IOUT = 1A CH4 Output Voltage vs. Input Voltage 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 1V IOUT = 2A IOUT = 1A CH5 Output Voltage vs. Input Voltage 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 1V IOUT = 0.5A IOUT = 1A IOUT = 0.25A CH6 Output Voltage vs. Input Voltage 0.990 0.993 0.995 0.998 1.000 1.003 1.005 1.008 1.010 2.5 3 3.5 4 4.5 5 5.5 Input Voltage (V) Output Voltage (V) VOUT = 1V IOUT = 2A IOUT = 1A

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5045A-00 March 2015 VIN = 3.3V, VOUT = 2.5V, IOUT = 2A to 4A VOUT (50mV/Div) IOUT (1A/Div) Time (100s/Div) CH1 Load Transient Response VOUT (10mV/Div) IOUT (500mA/Div) Time (200s/Div) CH2 Load Transient Response VIN = 3.3V, VOUT = 1.35V, IOUT = 0.5A to 1A VOUT (20mV/Div) IOUT (500mA/Div) Time (200s/Div) CH3 Load Transient Response VIN = 3.3V, VOUT = 1.8V, IOUT = 0.5A to 1A VIN = 3.3V, VOUT = 1V, IOUT = 1A to 2A VOUT (20mV/Div) IOUT (1A/Div) Time (200s/Div) CH4 Load Transient Response VIN = 3.3V, VOUT = 1V, IOUT = 0.5A to 1A VOUT (20mV/Div) IOUT (500mA/Div) Time (200s/Div) CH5 Load Transient Response VIN = 3.3V, VOUT = 1V, IOUT = 1.5A to 3.5A VOUT (20mV/Div) IOUT (2A/Div) Time (400s/Div) CH6 Load Transient Response

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com CH1 Output Voltage vs. Temperature 2.48 2.49 2.50 2.51 2.52 2.53 2.54 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 2.5V, IOUT = 0A VIN = 3.3V VIN = 3V CH2 Output Voltage vs. Temperature 1.30 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.40 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 1.35V, IOUT = 0A VIN = 3.3V VIN = 2.9V CH3 Output Voltage vs. Temperature 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 1.85 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 1.8V, IOUT = 0A VIN = 3.3V VIN = 2.9V CH4 Output Voltage vs. Temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 1V, IOUT = 0A VIN = 3.3V VIN = 2.9V CH5 Output Voltage vs. Temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 1V, IOUT = 0A VIN = 3.3V VIN = 2.9V CH6 Output Voltage vs. Temperature 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VOUT = 1V, IOUT = 0A VIN = 3.3V VIN = 2.9V

Application Information

The RT5045A provides six synchronous Buck regulators and one LDO to satisfy the entire power system of SSD. This device can communicate with processors through I 2C interface for programming the voltage, monitoring the status, or in/out the power saving mode. Table 29 lists the power rails provided by the RT5045A. Table 29. Detail of Power Rails small and keeps very low output voltage ripple. when one power rail occurs under voltage protection. drop and recovery when the faults disabled.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. RT5045A sharing a single bank of bulk input capacitors. Where IINtr is the total input transient current required. efficiency of the Buck at IOUT(MAX). Figure 3. The Location of Bulk Input Capacitance

1.21 I LC

used, put a reasonable value 50nH due to PCB layout. voltage sag is the equivalent series inductance (ESL). capacitor can only provide low capacitance value. in Table 30 lists the power rails provide by the RT5045A. of AVDD is 3.8V, else the threshold voltage is 2.8V.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 31. POR_OPTION Value Setting Condition than 100mV than VPORTH, the POR falls right away. Figure 4. I2C Read and Write Stream and Timing Diagram

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 8. For example : Power On/Off Sequence and Sleep off / Wake up Sequence with Different POR_OPTION The relations quiescent current and LPM current of each channel table are shown as below.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. difference between junction and ambient temperatu re. temperature on the maximum power dissipation. Figure 9. Derating Curve of Maximum Power used to minimize via impedance. directly to the pins without using vias. traces, using wide and short traces instead.  Place the bypass capacitor close to AVDD. LX3、LX4、LX5、LX6 to minimize trace inductance.

Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS5045A-00 March 2015 www.richtek.com Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max. A 0.500 0.600 0.020 0.024 A1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 D 3.540 3.640 0.139 0.143 D1 3.200 0.126 E 3.140 3.240 0.124 0.128 E1 2.800 0.110 e 0.400 0.016 52B WL-CSP 3.19x3.59 Package (BSC) Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications witho ut notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should ver ify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent righ ts of Richtek or its subsidiaries.

Product Information

RT5045A specifications and overview.

Summary

Power Management Unit Total Power Solution for SSD

Description

Power Management Unit Total Power Solution for SSD

Source title RT5045A Datasheet(PDF) - Richtek Technology Corporation

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