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INTEGRATED FAST ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS DATASHEET Rev. 1.2

01 July 2005

Track ID: JATR-1076-21 RTL8100E

Integrated Fast Ethernet Controller for PCI Express ii Track ID: JATR-1076-21 Rev. 1.2 COPYRIGHT ©2005 Realtek Semiconductor Corp. All rights reserve d. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without wa rranty of any kind, neither expressed nor implied, including, but not limited t o, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Cor poration. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the software engin eer’s reference and provides detailed programming information. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the producti on of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.

REVISION HISTORY

Revision Release Date Summary 1.0 2005/03/24 First release. 1.1 2005/06/28 Changed Figure 1, Pin Assignments, Page 3. Changed Table 4, Transceiver Interface, Page 5. Removed SPI flash related items. Removed Lead-free package information. Added ‘Green package’ information on page 3 and on page 23. Added ‘Exposed pad size’ information on page 23. 1.2 2005/07/01 Corrected error in Table 21, Ordering Information, page 23.

Integrated Fast Ethernet Controller for PCI Express iii Track ID: JATR-1076-21 Rev. 1.2 Table of Contents

Integrated Fast Ethernet Controller for PCI Express 1 Track ID: JATR-1076-21 Rev. 1.2 1. General Description The Realtek RTL8100E Fast Ethe rnet controller combines a IEEE 802.3 10/100Base-T compliant Media Access Controller (MAC), PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8100E offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP ( 10Mbps only) cable. Functions such as Crossover Detection & Auto-Correction, polarity correction, adaptive e qualization, cross-talk can cellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds. The device supports the PCI Express 1.0a bus interface for host communications with power management and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-c onfigure related bits of the PCI power management registers in PCI configuration space. Advanced Configuration Power management In terface (ACPI)—power mana gement for modern operating systems that are capable of Operati ng System-directed Power Management (OSPM)—is supported to achieve the most efficient power mana gement possible. PCI Message Signaled Interrupt (MSI) is also supported. In addition to the ACPI feature, remo te wake-up (including AMD Magic Packet ™ , Re-LinkOk, and Microsoft® Wake-up frame) is supported in both AC PI and APM (Advanced Power Management) only auxiliary exists), the auxiliar y power source must be able to provide the needed power for the RTL8100E. The RTL8100E is fully compliant with Microsoft ® NDIS5 (IP, TCP, UDP) Checksum and Segmentation Task-offload features, and suppor ts IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above f eatures contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server. The device also features next -generation inte r-connect PCI Express technology. PCI Express is a high-bandwidth, low pin count, serial , interconnect technol ogy that offers significant improvements in performance over conventional PCI and also maintains software co mpatibility with existing PCI infrastructure. The RTL8100E is suitable for multiple market segm ents and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.

Integrated Fast Ethernet Controller for PCI Express 2 Track ID: JATR-1076-21 Rev. 1.2 2. Features „ Integrated 10/100 transceiver „ Auto-Negotiation with Next Page capability „ Supports PCI Express™ 1.0a „ Supports pair swap/polarity/skew correction „ Crossover Detection & Auto-Correction „ Wake-on-LAN and remote wake-up support „ Microsoft® NDIS5 Checksum Offload (IP, TCP, UDP) and Largesend Offload support „ Supports Full Duplex flow control (IEEE 802.3x) „ Fully compliant with IEEE 802.3, IEEE 802.3u, IEEE 802.3ab „ Supports IEEE 802.1P Layer 2 Priority Encoding „ Supports IEEE 802.1Q VLAN tagging „ Serial EEPROM „ Transmit/Receive on-chip buffer support „ Supports power down/link down power saving „ Supports PCI Message Signaled Interrupt (MSI) „ 64-pin QFN package 3. System Applications „ Fast Ethernet on Motherboard, Notebook, or Embedded system

Figure 1. Pin Assignments ‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.

Table 1. Power Management/Isolation LANWAKEB O/D 19 Power Management Event: Open drain, active low. Used to reactivate the PCI Express slot’s main power rails and reference clocks. PCI Express input as long as the Isolate pin is asserted. Table 2. PCI Express Interface REFCLK_N I 27 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm. HSON O 30 PCI Express Transmit Differential Pair. HSIN I 24 PCI Express Receive Differential Pair. PCI Express Reset Signal: Active low. the de-assertion of the PERSTB. Table 3. EEPROM EESK O 48 Serial data clock. EEDI: Output to serial data input pin of EEPROM. AUX: Input pin to detect if Aux. Power exists or not on initial power-on. assumes that no Aux. Power exists. EEDO I 45 Input from serial data output pin of EEPROM. EECS O 44 EECS: EEPROM chip select.

Table 4. Transceiver Interface pair in 10Base-T and 100Base-TX. pair in 10Base-T and 100Base-TX. Table 5. Clock CKXTAL1 I 60 Input of 25MHz clock reference. CKXTAL2 O 61 Output of 25MHz clock reference. Table 6. Regulator & Reference VCTRL15 O 63 Regulator Control. V oltage control to external 1.5V power transistor. VCTRL18 O 1 Regulator Control. V oltage control to external 1.8V power transistor. RSET I 64 Reference. External resistor reference. Table 7. LEDs Note 1: During power down mode, the LED signals are logic high. default value of the (LEDS1, LEDS0) = (1, 1).

Table 8. Power & Ground VDD33 Power 16, 37, 46, 53 Digital 3.3V power supply. 43, 49, 52, 58 Digital 1.5V power supply. A VDD18 Power 5, 8, 11, 14 Analog 1.8V power supply. EVDD18 Power 22, 28 Analog 1.8V power supply. A VDD33 Power 2, 59 Analog 3.3V power supply. EGND Power 25, 31 Analog Ground. Note 2: Refer to the most updated schematic circuit for correct configuration. Table 9. NC (Not Connected) Pins

Integrated Fast Ethernet Controller for PCI Express 7 Track ID: JATR-1076-21 Rev. 1.2 6. Functional Description 6.1. PCI Express Bus Interface The RTL8100E is compliant with PCI Express Base Specification Revision 1.0a, and runs at a 2.5GHz signaling rate with X1 link width, i.e., one transmit and one receiv e differential pair. The RTL8100E supports four types of PCI Express messages: inte rrupt messages, error messages, power management messages, and hot-plug messages. To ease PCB layout c onstraints, PCI Express lane polarity reversal and link reversal are also supported. 6.1.1. PCI Express Transmitter The RTL8100E’s PCI Express block receives digital da ta from the Ethernet interface and performs data scrambling with Linear Feedback Shift Register (L FSR) and 8B/10B coding tec hnology into 10-bit code groups. Data scrambling is used to reduce the possibili ty of electrical resona nce on the link, and 8B/10B coding technology is used to benefit embedded clocki ng, error detection, and DC balance by adding an overhead to the system through the addition of 2 extr a bits. The data code gr oups are passed through its serializer for packet framing. The generated 2.5Gbps serial data is transmitted onto the PCB trace to its upstream device via a differential driver. 6.1.2. PCI Express Receiver The RTL8100E’s PCI Express block receives 2.5Gbps se rial data from its upst ream device to generate parallel data. The receiver’s PLL circuits are re-synchronized to main tain bit and symbol lock. Through 8B/10B decoding technology and data descrambling, the original digital data is recovered and passed to the RTL8100E’s internal Ethernet MAC to be transmitted onto the Ethernet media. 6.2. LED Functions The RTL8100E supports three LED signals in four different configurable operation modes. The following sections describe the various LED actions. 6.2.1. Link Monitor The Link Monitor senses link integrity, such as LINK10, LINK100, LINK10/100, LINK10/ACT, or LINK100/ACT. Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected, the link LED pin is driven high, indicating that no network connection exists.

Figure 4. Tx/Rx LED

operating properly. When this LED is high for extended periods, it indicates that a link problem exists. Figure 5. LINK/ACT LED

Integrated Fast Ethernet Controller for PCI Express 11 Track ID: JATR-1076-21 Rev. 1.2 6.3. PHY Transceiver 6.3.1. PHY Transmitter Based on state-of-the-art DSP t echnology and mixed-mode signal processing technology, the RTL8100E operates at 10/100Mbps over standard CAT.5 UTP cable (100Mbps), and CAT.3 UTP cable (10Mbps). MII (100Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MA C, clocked at 25MHz (TXC), are converted into 5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3 encoder, then to the D/A converter and transmitted onto the media. MII (10Mbps) Mode The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into 10Mbps serial data. The 10Mbps serial data is convert ed into a Manchester-encoded data stream and is transmitted onto the media by the D/A converter. 6.3.2. PHY Receiver MII (100Mbps) Mode The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing recovery, MLT3 and NRZI decoder, descrambler, 4B /5B decoder, and is then presented to the MII interface in 4-bit-wide nibbles at a clock speed of 25MHz. MII (10Mbps) Mode The received differential signal is converted into a Manchester-encoded st ream first. Next, the stream is processed with a Manchester decoder and is de-seria lized into 4-bit-wide nibbles. The 4-bit nibbles are presented to the MII interface at a clock speed of 2.5MHz.

the EEPROM using bit-bang accesses via the 9346CR Re gister, or using PCI VPD (Vital Product Data). The interface consists of EESK, EECS, EEDO, and EEDI. The correct EEPROM (i.e. 93C46/93C56) must be used in order to ensure proper LAN function. Table 10. EEPROM Interface EECS 93C46/93C56 chip select. EESK EEPROM serial data clock. Input data bus/Input pin to detect whether Aux. Power exists on initial power-on. not pulled high to Aux. Power, the RTL8100E assumes that no Aux. Power exists.

Integrated Fast Ethernet Controller for PCI Express 13 Track ID: JATR-1076-21 Rev. 1.2 6.5. Power Management The RTL8100E is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Mana gement (Rev 1.1), PCI Express Active State Power Management (ASPM) , and Network Device Class Power Management Reference Specification (V1.0a), such as to support an Operating System-directed Power Management (OSPM) environment. The RTL8100E can monitor the network for a Wake up Frame, a Magic Packet, or a Re-LinkOk, and notify the system via a PCI Express Power Management Event (PME) Message, Beacon, or LANWAKEB pin when such a packet or event occurs. Th en the system can be restored to a normal state to process incoming jobs. When the RTL8100E is in power down mode (D1 ~ D3):

  • The Rx state machine is stopped. The RTL8100E monitors the network for wakeup events such as a Magic Packet, Wakeup Frame, and/or Re-LinkOk, in order to wake up the system. When in power down mode, the RTL8100E will not reflect the status of any incoming packets in the ISR register and will not receive any packets into the Rx on-chip buffer.
  • The on-chip buffer status and packets that have already been received into the Rx on-chip buffer before entering power down mode are held by the RTL8100E.
  • Transmission is stopped. PCI Express transactions are stopped. The Tx on-chip buffer is held.
  • After being restored to D0 state, the RTL8100E transmits data that was not moved into the Tx on-chip buffer during power down mode. Packets that were not transmitted completely last time are re-transmitted. The D3cold_support_PME bit (bit15, PMC register) a nd the Aux_I_b2:0 bits (bit8 :6, PMC register) in PCI configuration space depend on the existence of Aux power (bit15, PMC) = 1. If EEPROM D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s. Example: If EEPROM D3c_support_PME = 1:
  • If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 F7, then PCI PMC = C2 F7)
  • If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 F7, then PCI PMC = 02 76) In the above case, if wakeup support is desired when main power is off, it is suggested that the EEPROM PMC be set to C2 F7 (Realtek EEPROM default value). If EEPROM D3c_support_PME = 0:
  • If aux. power exists, then PMC in PCI config space is the same as EEPROM PMC (if EEPROM PMC = C2 77, then PCI PMC = C2 77)
  • If aux. power is absent, then PMC in PCI config space is the same as EEPROM PMC except the above 4 bits are all 0’s (if EEPROM PMC = C2 77, then PCI PMC = 02 76) In the above case, if wakeup support is not desired wh en main power is off, it is suggested that the EEPROM PMC be set to 02 76.

Integrated Fast Ethernet Controller for PCI Express 14 Track ID: JATR-1076-21 Rev. 1.2 Link Wakeup occurs only when the following conditions are met:

  • The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state. Magic Packet Wakeup occurs only when the following conditions are met:
  • The destination address of the received Magic Packet is acceptable to the RTL8100E, e.g., a broadcast, multicast, or unicast packet addressed to the current RTL8100E adapter.
  • The received Magic Packet does not contain a CRC error.
  • The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the corresponding wake-up method (message, beacon, or LANWAKEB) can be asserted in the current power state.
  • The Magic Packet pattern matches, i.e. 6 * FFh + MISC (can be none) + 16 * DID (Destination ID) in any part of a valid Ethernet packet. A Wakeup Frame event occurs only when the following conditions are met:
  • The destination address of the received Wakeup Frame is acceptable to the RTL8100E, e.g., a broadcast, multicast, or unicast address to the current RTL8100E adapter.
  • The received Wakeup Frame does not contain a CRC error.
  • The PMEn bit (CONFIG1#0) is set to 1.
  • The 16-bit CRC A of the received Wakeup Frame matches the 16-bit CRC of the sample Wakeup Frame pattern given by the local machine’s OS. Or, the RTL8100E is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. Note: 16-bit CRC: The RTL8100E supports two norma l wakeup frames (covering 64 mask bytes from offset 0 to 63 of any incoming network packet) and three long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). The corresponding wake-up method (message, beacon, or LANWAKEB) is asserted only when the following conditions are met:
  • The PMEn bit (bit0, CONFIG1) is set to 1.
  • The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
  • The RTL8100E may assert the corresponding wake-up method (message, beacon, or LANWAKEB) in the current power state or in isolation state, depending on the PME_Support (bit15-11) setting of the PMC register in PCI Configuration Space.
  • A Magic Packet, LinkUp, or Wakeup Frame has been received.
  • Writing a 1 to the PME_Status (bit15) of the PMCSR register in the PCI Configuration Space clears this bit and causes the RTL8100E to stop asserting the corresponding wake-up method (message, beacon, or LANWAKEB) (if enabled).

Integrated Fast Ethernet Controller for PCI Express 15 Track ID: JATR-1076-21 Rev. 1.2 When the RTL8100E is in power dow n mode, e.g., D1-D3, the IO and MEM accesses to the RTL8100E are disabled. After a PERSTB assertion, the device’s pow er state is restored to D0 automatically if the original power state was D3 cold. There is almost no hardware delay at the device’s power state transition. When in ACPI mode, the device does not support PME (Power Management Enable) from D0 (this is the Realtek default setting of the PMC register auto -loaded from EEPROM). The setting may be changed from the EEPROM, if required. 6.6. Vital Product Data (VPD) Bit 31 of the Vital Product Data (VPD) capability st ructure in the RTL8100E’s PCI Configuration Space is used to issue VPD read/write commands and is also a flag used to indicate whether the transfer of data between the VPD data register and the 93C46/93C56 has completed or not. Write VPD register: (write data to the 93C46/93C56) Set the flag bit to 1 at the same time the VPD address is written to write VPD data to EEPROM. When the flag bit is reset to 0 by the RTL8100E, the VPD data (4 bytes per VPD access) has been transferred from the VPD data register to EEPROM. Read VPD register: (read data from the 93C46/93C56) Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM. When the flag bit is set to 1 by the RTL8100E, the VPD data (4 bytes per VPD access) has been transferred from EEPROM to the VPD data register. Note1: Refer to the PCI 2.2 Specifications for further information. Note2: The VPD address must be a DWORD-aligned address as defined in the PCI 2.2 Specifications. VPD data is always consecutive 4-byte data starting from the VPD address specified. Note3: Realtek reserves offset 40h to 7Fh in EEPROM, mainly for VPD data to be stored. Note4: The VPD function of the RTL8100E is designed to be able to access the full range of the 93C46/93C56 EEPROM.

Table 11. Absolute Maximum Ratings

  • Refer to the most updated schematic circuit for correct configuration.

Table 12. Recommended Operating Conditions

  • Refer to the most updated schematic circuit for correct configuration.

Table 13. Crystal Requirements fundamental mode, AT-cut type.

Table 14. Thermal Characteristics Table 15. DC Characteristics

  • Refer to the most updated schematic circuit for correct configuration.

Figure 6. Serial EEPROM Interface Timing Table 16. EEPROM Access Timing Parameters

Table 17. Differential Transmitter Parameters which requires the two communicating ports be modulated such that they never exceed a total of 600 ppm difference.

Table 18. Differential Receiver Parameters Note: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter. Table 19. REFCLK Parameters The crossing point must meet the absolute and relative crossing point specifications simultaneously. Note3: The nominal single-ended swing for each clock is 0 to 0.7V with a nominal frequency of 100MHz ±300 PPM. Note4: The reference clocks may support spread spectrum clocking. The minimum clock period cannot be violated.

Figure 10. REFCLK V cross Range Table 20. Auxiliary Signal Timing Parameters

3.3 Vaux

Figure 11. Auxiliary Signal Timing

Table 21. Ordering Information Note: See page 3 for package ID information. Industrial Park, Hsinchu, 300, Taiwan, R.O.C.