R7510A RICHTEK | Alldatasheet
Document overview
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Technical content
Features
zzzzz VDD Under Voltage Lockout Protection zzzzz Output Over Voltage Protections (OVP) for 3.3V, 5V and 12V zzzzz Output Under Voltage Protections (UVP) for 3.3V and 5V zzzzz Open-Drain Power Good (PGO) and Fault Protection (FPOB) Outputs zzzzz 300ms Power Good Delay Time zzzzz 38ms PSONB Remote ON/OFF De-bounce Time zzzzz 55μμμμμs OVP and 73μμμμμs UVP Noise Deglitch Times zzzzz 3.5ms PSONB Turn-off Delay Time zzzzz Two-Threshold PGI Input with 73μμμμμs Noise Deglitch Time zzzzz 75ms UVP Blanking Time during Start-up zzzzz Low Cost and Component Count zzzzz RoHS Compliant and Halogen Free Pin Configuration (TOP VIEW) DIP-8
Ordering Information
R7510AGN : Product Number YMDNN : Date Code Note : Richtek products are : \ RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes. R7510A Package Type N : DIP-8 Lead Plating System G : Green (Halogen Free and Pb Free)
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©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. PGI PGO +5VSB PS ON/OFF PGO PSONB GND FPOB V33 VDD R7510A +3.3VIS +12VIS +12V +3.3V +5V +5VIS +5VSB 4 5 Pin No. Pin Name Pin Description 1 PGI Power Good Signal Input Pin. This pin senses partial voltage of the system input voltage. 2 GND Ground Pin of the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to system ground plane with the lowest impedance. 3 FPOB Fault Protection Output Pin. This pin is pulled low when PSONB = L and no protections happened. 4 PSONB Remote ON/OFF Control Input Pin. This pin is designed with a 38ms (typical) De-bounce time to avoid input voltage bounce. 5 V33 3.3V OVP and UVP Detection Input Pin. 6 V5 5V OVP and UVP Detection Input Pin. 7 VDD Supply Voltage and 12V OVP Detection Input Pin. Connect a noise decoupling capacitor between this pin and GND. 8 PGO Open-Drain Power Good Output Pin. When all output voltages are in their regulation ranges, the PGO voltage goes high. Functional Pin Description Typical Application Circuit
©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram PGO VDD GND PSONB FPOB clr 38ms Debounce R S Q OV PGI V33 Under- Voltage Lockout VDD 300ms Rising Delay clr 73µs Deglitch clr 73µs Deglitch 3.5ms Rising Delay -1.2V / 1.8V Bandgap and Regulator Shutdown UVLO VDDVREG VREF 1.2V VREF 1.2V UV OV UV OV UVP clr 55µs Deglitch Oscillator CLK VTH_PGIH = 1.2V 75ms Rising Delay clr OVP Disable Shutdown Fault Shutdown Shutdown UVLO -VTH_PGIL = 0.95V VDD
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©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Descriptions VDD Under Voltage Lockout Protection The R7510A automatically initializes upon receipt of power. The Under Voltage Lockout (UVLO) function continually monitors the bias voltage at VDD pin. When the supply voltage (V DD) exceeds its rising UVLO threshold (3.6V typical), the IC is enabled to work. When the VDD voltage is under the UVLO voltage threshold (UVLO = H), the PGO voltage is pulled low to indicate the output voltages are not ready and the FPOB pin keeps high impedance to disable the primary-side PWM controller. The supply voltage must be below the absolute maximum rating for safety. Output Under Voltage Protection and PGI Input The R7510A provides under voltage protection for the 3.3V IC Blanking Time Start Condition Stop Condition ∞ VPGI < 0.95V V PGI > 0.95V R7510A 75ms VPGI > 0.95V end of 75ms and 5V outputs. The UVP continuously monitors the voltage on V33 and V5. When an under-voltage (UV) protection condition appears at one of the monitored pins for more than 73μs (typical) deglitch time, the PGO voltage goes low to indicate one of the output voltages is out of regulation. Meanwhile the FPOB also becomes high impedance to disable the primary-side PWM controller and protects the power supply system. The UVP protection condition is latched until PSONB is toggled from low to high or VDD restarts. The UVP protection can be disabled by the PGI signal. During PSONB start-up or AC power-on, a UVP blanking signal disables the UVP detections to prevent wrong UVP. The blanking time is shown in the following table: The UVP protection is disabled when the PGI voltage keeps below the lower PGI voltage threshold 0.95V (typical). After the start-up is completed, the IC enters normal-mode operation. The UVP will be disabled when the PGI voltage falls below the lower voltage threshold 0.95V (typical). This function is designed to keep PWM switching and discharge the high-voltage charge in the bulk capacitors during AC power-off. Output Over Voltage Protection The R7510A has an output Over Voltage Protection (OVP) function, which monitors the 3.3V, 5V and 12V output voltages, to prevent power system and loads from damages during one or more output OV condition(s). The OVP starts monitoring the voltages on V33, V5 and VDD at end of the PSONB de-bounce time. When an Over Voltage (OV) condition appears at one of the monitored pins for more than the 55 μs (typical) deglitch time, the PGO voltage goes low to indicate one of the output voltages is out of regulation. Meanwhile the FPOB also becomes high impedance to disable the primary-side PWM controller and protects the power supply system. The OVP condition is latched until PSONB is toggled from low to high or VDD restarts. PSONB De-bounce R7510A provides a remote ON/OFF control input pin (PSONB) for PC power supply applications. A built-in 38ms (typical) de-bounce circuit performs rising and falling edge noise de-bounce functions to identify valid PSONB input signals. The PSONB also has a TTL logic-compliant input voltage threshold and a hysteresis design against input noise. FPOB and PGO Outputs The FPOB and PGO are all open-drain output pins. The PGO voltage, pulled high by an external resistor connected to the 5V output, indicates the status of the outputs. The PGO keeps at low state, when VDD voltage<UVLO threshold, PSONB = H, PGI voltage<1.2V or one of the faults, including UVP and OVP occurs. In general, the FPOB pin is used to enable the primary- side PWM controller via an opto-coupler. An external series resistor is used to limit the current flowing through the opto-coupler and FPOB pin. The FPOB keeps high impedance, when VDD voltage<UVLO threshold, PSONB = H or one of the faults, including UVP and OVP occurs.
©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Function Table Note: X = Don't care FPOB = "L" means fault isn't latched FPOB = "H" means fault is latched PGO = "L" means fault PGO = "H" means No fault Input Signals Events Output Signals PGI PSONB UV Detected OV Detected FPOB PGO VPGI < 0.95V L No No L L VPGI < 0.95V L No Yes H L VPGI < 0.95V L Yes No L L VPGI < 0.95V L Yes Yes H L VPGI > 0.95V L No Yes H L VPGI > 0.95V L Yes No H L VPGI > 0.95V L Yes Yes H L VPGI > 1.2V L No No L H X H X X H L
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©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. (2) PS ON/OFF and OVP tDb1 PGO VOUT VPGI VFPOB POSNB VDD PS OFF OVP tg1+tDELAY1 tg2 tDb1 tDb1+3.5ms tDb1 tDb1 PS ON PS ON PS ON tg1+tDELAY1 1.2V 0.95V tDELAY3 UVP Blanking Time tDELAY3 UVP Blanking Time tg1+tDELAY1 PS OFF tDELAY3 UVP Blanking Time tDb1 Timing Diagram (1) AC Power ON/OFF tDb1 PGO Vout VPGI VFPOB POSNB VDD tg1 + tDelay1 tg1 + tDelay1 tDb1 + 3.5ms 1.2V AC OFF AC ON Enable UVP/OCP Enable UVP/OCP PS OFF tDb1 0.95V tDelay3tDelay3 UVP/OCP Blanking Time UVLO Th. Disable UVP/OCP UVP/OCP Blanking Time tg1 Note : PSONB = L AC Power-OFF AC Power-ON PSONB = H. Note : PSONB = L PSONB = H PSONB = L OVP Latch PSONB = H PSONB = L.
©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. (3) UVP PGO VOUT PGI VFPOB POSNB VDD UVP tg1+tDELAY1 tg3 PS ON tg1+tDELAY1 1.2V 0.8V tDELAY3 UVP Blanking Time UVP Th. PS OFF PS ON tDELAY3 UVP Blanking Time tDb1 tDb1 Note : PSONB = L UVP Latch PSONB = H PSONB = L.
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©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Electrical Characteristics
Parameter Symbol Test Conditions Min Typ Max Unit VDD Supply Current and Under Voltage Lockout (UVLO) VDD Supply Voltage Range V DD T A = −40ºC to 85ºC 4 -- 15 V VPSONB = 5V -- 0.5 1 mA VDD Supply Current I DD VPSONB = 0V -- -- 3 mA Rising UVLO Voltage Threshold V TH_UVLOR V DD rising 3.2 3.4 3.6 V Falling UVLO Voltage Threshold V TH_UVLOF V DD falling 2.8 3 3.2 V Over Voltage Protection Section (OVP) 3.7 3.9 4.1 V33 Over Voltage Threshold V TH_V33OV TA = −40ºC to 85ºC 3.66 3.9 4.14 V 5.7 6.1 6.2 V5 Over Voltage Threshold V TH_V5OV TA = −40ºC to 85ºC 5.64 6.1 6.26 V 12.9 13.4 13.9 VDD Over Voltage Threshold V TH_V12OV TA = −40ºC to 85ºC 12.76 13.4 14.04 V Under Voltage Protection (UVP) 2 2.2 2.4 V33 Under Voltage Threshold V TH_V33UV TA = −40ºC to 85ºC 1.97 2.2 2.43 V Recommended Operating Conditions (Note 4) Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3) (VDD = 5V, T A = 25°C, unless otherwise specified)
©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit 3.3 3.5 3.7 V5 Under Voltage Threshold V TH_V5UV TA = −40ºC to 85ºC 3.26 3.5 3.74 V V33 Pin Input Resistance -- 150 -- k Ω V5 Pin Input Resistance -- 300 -- k Ω PGO and FPOB Outputs PGO Leakage Current I LK_PGO VPGO = 5V, the internal NMOS is off -- -- 5 μA PGO Low-level Output Voltage V OL_PGO I SINK = 10mA -- 0.23 0.3 V PGO Rising Time t R_PGO Pull-up Resistance = 1k Ω -- -- 100 ns FPOB Leakage Current I LK_FPOB VFPOB = 5V, PSONB = Open -- -- 5 μA FPOB Low-level Output Voltage VOL_FPOB I SINK = 10mA -- 0.2 0.3 V PGI and PSONB Input Higher PGI Voltage Threshold V TH_PGIH (Note 5) 1.16 1.2 1.24 V Lower PGI Voltage Threshold V TH_PGIL (Note 6) 0.9 0.95 1 V PGI Input Current V PGI = 1.2V -- -- 1 μA PSONB Input Pull-up Resistor R PU_PSONB -- 26 -- k Ω PSONB Input Pull-up Voltage V PU_PSONB -- 4.5 -- V PSONB High-level Input Voltage VIH_PSONB 1.8 -- -- V PSONB Low-level Input Voltage VIL_PSONB -- -- 1.2 V Timing Characteristics PSONB De-bounce Time t Db1 26 38 50 ms PGI to PGO Deglitch Time t g1 Rising V PGI > 1.2V 46 73 100 μs PGI to PGO Delay Time t DELAY1 Rising V PGI > 1.2V 200 300 400 ms OVP Deglitch Time t g2 V V33/V5/VDD rising 35 55 75 μs UVP Deglitch Time t g3 V V33/V5/V12 falling 46 73 100 μs PSONB Turn-Off Delay Time t DELAY2 from PSONB goes low to FPOB goes high 2 + tDb1 3.5 + tDb1 5 + tDb1 ms VPGI < 0.95V Disable UVP Power-On Blanking Time t DELAY3 VPGI > 0.95V 50 75 100 ms
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©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. The PGO is allowed to indicate the output statuses when PGI voltage rises above this voltage threshold; otherwise the PGO is held at low state. Note 6. This voltage threshold is used to start the UVP blanking time (75ms, when V PGI > 0.95V) and then enable the UVP during power-on. During normal operation, if the PGI voltage is below the threshold, the UVP is disabled.
©Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics VDD Supply Current vs. Junction Temperature 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 -50 -25 0 25 50 75 100 125 Junction Temperature VDD Supply Current (mA ) (°C) VPSONB = 0V PGI Voltage Threshold vs. Junction Temperature 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 -50 -25 0 25 50 75 100 125 Junction Temperature PGI Voltage Threshold (V) (°C) PSONB De-bounce Time vs. Junction Temperature -50 -25 0 25 50 75 100 125 Junction Temperature PSONB De-bounce Time (ms) (°C) Falling&Rising UVLO Voltage Threshold vs. Junction Temperature 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 -50 -25 0 25 50 75 100 125 Junction Temperature UVLO Voltage Threshold (V ) (°C) Rising Falling
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Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension J A B E C I D L F Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 9.068 9.627 0.357 0.379 B 6.198 6.604 0.244 0.260 C 3.556 4.318 0.140 0.170 D 0.356 0.559 0.014 0.022 E 1.397 1.651 0.055 0.065 F 2.337 2.743 0.092 0.108 I 3.048 3.556 0.120 0.140 J 7.366 8.255 0.290 0.325 L 0.381 0.015 8-Lead DIP Plastic Package