PSVFBGA AMKOR | Alldatasheet

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Technical content

Features: Reliability: www.amkor.com

  • 10-15 mm body sizes tooled per product table. Additional sizes based on demand
  • Top package I/O interface 0.65 mm pitch accommodating 104 to 160 pin counts
  • High I/O 0.50 mm pitch interface is qualified
  • Fine pitch 0.50 mm bottom package footprints with 0.40 mm pitch in qualification
  • Established package on package infrastructure (over 5 years of development with leading OEM, EMS and equipment providers)
  • Wafer thinning / handling < 100 µm
  • Consistent product performance and reliability
  • P ackage configurations compliant with JEDEC standards
  • Package pre-stacking support and services available based on demand
  • Bottom PSvfBGA and top FBGA / Stacked CSP packages are well established in high volume production
  • Stacked package heights of 1.2 mm to 1.6 mm available in a variety of configurations. (See Stack Up table below) Amkor assures reliable performance by continuously monitoring key indices: Package Level:
  • Moisture Resistance Testing JEDEC Level 3 @260 °C x 4 reflows
  • Additional Test Data at [(30 °C/85%RH/96hrs)+260]x 3 or x4
  • Package dimensions 14 x 14 mm, 352 I/O
  • Temp Cycle -55/+125 °C, 1000 cycles
  • Temp/Humidity 85 °C/85%RH/1000 hours
  • High Temp Storage 150 °C, 1000 hours
  • HAST 130 °C, 85% RH, 96 hours Board Level:
  • Thermal Cycle -40/+125 °C, 1000 cycles Package Stackable Very Thin Fine Pitch BGA (PSvfBGA): After 3 years of development in package stacking technology and infra- structure, Amkor launched the multiple award winning PSvfBGA (base PoP) platform during the 4th quarter of 2004. The next two years saw many new milestones, from publication of JEDEC mechanical and elec- trical standards to a range of new customers and applications adopting PoP. By the end of 2006 PSvfBGA became the fastest growing new product in Amkor's history, reflecting the broad industry benefits of PoP and Amkor's leadership position. The next few years promise to provide many new challenges and applications for PoP, as handheld multimedia applications continue to demand higher processing power and memory storage capacities. Amkor is committed to maintain strong development and production capabilities to ensure we are forefront in meeting next generation PoP requirements. Amkor has expanded our comprehensive PoP family and aligned the roadmap across the supply chain to ensure that PoP will continue to scale with the industry's miniaturization, higher density and perform- ance enhancement requirements. In 2006 Amkor's PoP family ramped products with 2 die stacked in the PSvfBGA platform. Stacking multiple die in the bottom package allows customers to increase performance and provide further system miniatur- ization by combining analog+digital or logic+memory devices. Applications: PoP packages are designed for products requiring efficient memory architectures including multiple buses and increased memory density & performance, while reducing mounted area. Portable electronic products such as mobile phones (baseband or applications processor+combo memory), digital cameras (image processor+memory), PDAs, portable players (audio / graphics processor+memory), gaming and other mobile applications can benefit from the combination of stacked pack- age and small footprint offered by Amkor's industry leading PoP family. Broad Benefits as an Enabling Technology: PoP offers OEMs and EMS providers a platform to cost effectively expand options for logic+memory 3D integration with the following benefits:
  • Greatly expands device options by simplifying the business logistics of stacking
  • Integration controlled at the system level to best match stacked combinations with system requirements
  • JEDEC standards ensure broad component availability
  • Improving time to market and sourcing flexibility
  • Eliminates margin stacking and expands technology reuse
  • Helps manage the huge cost impacts associated with increasing demand for multi-media processing and memory
  • Logic device transitions to flip chip in the bottom package enables further PoP size and height reductions DS586C Rev Date: 03’07 VISIT AMKOR TECHNOLOGY ONLINE FOR LOCATIONS AND TO VIEW THE MOST CURRENT PRODUCT INFORMATION . LAMINATE FBGA + PSvfBGA Symbol Unit Min Max Nom A1 (mounted, 0.5 pitch) mm 0.160 0.260 0.210 A2 (4L laminate) mm 0.260 0.340 0.300 B1 (stacked, 0.65 pitch), single die mm 0.270 0.330 0.300 B2 (stacked, 0.65 pitch), 2+0 die mm 0.320 0.380 0.350 B3 (2L laminate) mm 0.100 0.160 0.130 B4 (mold cap) mm 0.370 0.430 0.400 Overall Pkg height mm 1.310 1.470 1.400 PoP Overall Stack Up Table Package on Package (PoP) Family

With respect to the information in this document, Amkor makes no guarantee or warranty of its accuracy or that the use of such information will not infringe upon the intellectual rights of third parties. Amkor shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it and no patent or other license is implied hereby. This document does not in any way extend or modify Amkor’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Amkor reserves the right to make changes in its product and specifications at any time and withou t notice. www.amkor.com Process Highlights Die thickness (max) 75 µm ti 125 µm Bond pad pitch (min) 40 µm (In-line) Marking Laser Wafer thinning 200 & 300 mm wafers Standard Materials Package substrate -Conductor Copper -Dielectric Thin core FR5 or equivalent Die attach adhesive Conductive or non conductive Encapsulant Epoxy mold compound Solder ball Eutectic SnPb / Pb free Test Services Program Generation / Conversion Product Engineering Wafer sort

256 Pin x 20 MHz test system available

Footprint- top (B) Footprint - bottom (C) Package size (A)0.27mm Max die size (D) (E) LAMINATE data sheet PSvfBGA Top View AB C DE Body Package Interconnect Bottom Package Package Interconnect ball Typical Wirecount Size (mm) Matrix Ball Count Ball Count Die Size (mm) center to package edge (mm) for given package size 10 15 104 300 <5.50 0.450 320 11 16 112 350 <6.00 0.625 360 12 18 128 400 <7.50 0.475 420 13 19 136 450 <8.00 0.650 460 14 21 152 550 <9.00 0.500 520 15 22 160 700 <10.00 0.675 600

  • Dimensions are in line with JEDEC JC-11 standards for PoP packages in development
  • Assuming 2 perimeter rows of interconnects at 0.65 mm pitch
  • Assuming 4 perimeter rows of BGA balls to motherboard at 0.50 mm pitch Package on Package (P0P) Family Contact Amkor for Daisy chain sample availability, the latest PSvfBGA capabilities, and for full review of PSvfBGA, PoP technology and roadmaps.