PSOC4XX8-BLE4.2

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Features

■ 48-MHz ARM Cortex-M0 CPU with single-cycle multiply and DMA ■ Up to 256 KB of flash with Read Accelerator ■ Up to 32 KB of SRAM BLE Radio and Subsystem ■ BLE 4.2 support ■ 2.4-GHz RF transceiver with 50-Ω antenna drive ■ Digital PHY ■ Link-Layer engine supporting master and slave modes ■ RF output power: –18 dBm to +3 dBm ■ RX sensitivity: –92 dBm ■ RX current: 18.7 mA ■ TX current: 16.5 mA at 0 dBm ■ RSSI: 1-dB resolution Programmable Analog ■ Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes, and ADC input buffering capability. Can operate in Deep Sleep mode. ■ 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging ■ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ■ Two low-power comparators that operate in Deep Sleep mode Programmable Digital ■ Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data path ■ Cypress-provided peripheral component library, user-defined state machines, and Verilog input Power Management ■ Active mode: 1.7 mA at 3-MHz flash program execution ■ Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO) on ■ Hibernate mode: 150 nA with RAM retention ■ Stop mode: 60 nA Capacitive Sensing ■ Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and liquid tolerance ■ Cypress-supplied software component makes capacitive sensing design easy ■ Automatic hardware tuning algorithm (SmartSense™) Segment LCD Drive ■ LCD drive supported on all pins (common or segment) ■ Operates in Deep Sleep mode with four bits per pin memory Serial Communication ■ Two independent run-time reconfigurable serial communi- cation blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality Timing and Pulse-Width Modulation ■ Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks ■ Center-aligned, Edge, and Pseudo-random modes ■ Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 36 Programmable GPIOs ■ 7m m × 7m m 5 6 - p i n Q F N p a c k a g e ■ 76-ball CSP package ■ Any GPIO pin can be CapSense, LCD, analog, or digital ■ Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable PSoC Creator™ Design Environment ■ Integrated Design Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) ■ API components for all fixed-function and programmable peripherals Industry-Standard Tool Compatibility ■ After schematic entry, development can be done with ARM-based industry-standard development tools

duction page for Bluetooth® Low Energy (BLE) Products . access to all GPIOs of the device.

4 BLE 256KB device, two crystals for the antenna matching

access to all GPIOs of the device.

1. Drag and drop component icons to build your hardware
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Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents

Figure 2. Block Diagram connections are required to fully support debugging. device with the new firmware that enables debugging. BLE 4.2 allows the customer to make.

48 MHz

2.4 GHz

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 5 of 47 Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in PSoC 4XX8 BLE 4.2 is part of the 32-bit MCU subsystem, which is optimiz ed for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher-performance processors such as Cortex-M3 and M4. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) bloc k with 32 interrupt inputs and a wakeup interrupt controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to the main processor to be switched off when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes an SWD interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC 4XX8 BLE 4.2 has four break-point (address) comparators and two watchpoint (data) comparators. Flash The PSoC 4XX8 BLE 4.2 device has a flash module with either

128 KB or 256 KB of flash memory, tightly coupled to the CPU to

improve average access times from the flash block. The flash block is designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. Maximum erase and program time is 20 ms per row (256 bytes). This also applies to the emulated EEPROM. SRAM SRAM memory is retained during Hibernate. SROM The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are accessed through supervisory calls (SVC) and enable in-system programming of the flash memory. DMA A DMA engine, with eight channels, is provided that can do 32-bit transfers and has chainable ping-pong descriptors. System Resources Power System The power system is described in detail in the section Power on page 16. It provides an assurance that the voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset (POR), for example) until voltage levels are as required or generate resets (brownout detect (BOD)) or interrupts when the power supply reaches a particular program- mable level between 1.8 and 4.5 V (low voltage detect (LVD)). PSoC 4XX8 BLE 4.2 operates with a single external supply (1.71 to 5.5 V without radio, and 1.9 V to 5.5 V with radio). The device has five different power modes; transitions between these modes are managed by the power system. PSoC 4XX8 BLE 4.2 provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Refer to the Technical Reference Manual for more details. Clock System The PSoC 4XX8 BLE 4.2 clock system is responsible for providing clocks to all subsyste ms that requir e clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC 4XX8 BLE 4.2 consists of the internal main oscillator (IMO), the internal low-speed oscillator (ILO), the 24-MHz external crystal oscillator (ECO) and the 32-kHz watch crystal oscillator (WCO). In addition, an external clock may be supplied from a pin. IMO Clock Source The IMO is the primary source of internal clocking in PSoC 4XX8 BLE 4.2. It is trimmed during te sting to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. The IMO tolerance with Cypress-provided calibration settings is ±2%. ILO Clock Source The ILO is a very low-power oscillator, which is primarily used to generate clocks for the peripheral operation in the Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. External Crystal Oscillator (ECO) The ECO is used as the active clock for the BLE subsystem to meet the ±50-ppm clock accuracy of the Bluetooth 4.2 Specification. PSoC 4XX8 BLE 4.2 includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO clock can also be used as a system clock. Watch Crystal Oscillator (WCO) The WCO is used as the sleep clock for the BLE subsystem to meet the ±500-ppm clock accuracy for the Bluetooth 4.2 Specification. The sleep clock provides an accurate sleep timing and enables wakeup at the specified advertisement and connection intervals. The WCO output can be used to realize the real-time clock (RTC) function in firmware. Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows the watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. With the WCO and firmware, an accurate real-time clock (within the bounds of the 32-kHz crystal accuracy) can be realized.

Figure 3. PSoC 4XX8 BLE 4.2 MCU Clocking Architecture divided clock signals, which c an be used by peripheral blocks. internal pull-up resistor that is always enabled. Specifications,” on page 26 for details. 1.9-V minimum supply (the range varies from 1.9 V to 5.5 V).

1 Msps whether it is for a single channel or distributed over

out-of-range values in software. SAR operating range is 1.71 to 5.5 V. Figure 4. SAR ADC System Diagram without requiring external buffering. calibration and linearization. by a comparator-switch event.

through the UDBs for communication and control. Figure 5. UDB Array network directly or after synchronization. clocked with the same source as the PLDs inside the UDB array. used to register other inputs (see Figure 6). Figure 6. Port Interface

3 DSI Signals ,

1 I/O Signal

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 9 of 47 Fixed-Function Digital Timer/Counter/PWM Block The timer/counter/PWM block cons ists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow the use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. Serial Communication Blocks (SCB) PSoC 4XX8 BLE 4.2 has two SCBs, each of which can implement an I 2C, UART, or SPI interface. I2C Mode : The hardware I 2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce the interrupt overhead and latency for the CPU. It also supports EzI 2C that creates a mailbox address range in the memory of PSoC 4XX8 BLE 4.2 and effectively reduces the I2C communication to reading from and writing to an array in the memory. In addition, the block supports an 8-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I 2C peripheral is compatible with I 2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. SCB1 is fully compliant with Standard mode (100 kHz), Fast mode (400 kHz), and Fast-Mode Plus (1 MHz) I 2C signaling specifications when routed to GPIO pins P5[0] and P5[1], except for hot-swap capability during I 2C active communication. The remaining GPIOs do not meet the hot-swap specification (V DD off; draw < 10-µA current) for Fast mode and Fast-Mode Plus, IOL Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 VDD) for Fast mode and Fast-Mode Plus, and minimum fall time spec for Fast mode and Fast-Mode Plus. ■ GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the I 2C system. ■ The GPIO pins P5.0 and P5.1 are over-voltage tolerant but cannot be hot-swapped or powered up independent of the rest of the I 2C system ■ Fast-Mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. ■ Fast-mode and Fast-Mode Plus specify minimum Fall times, which are not met with the GPIO cell; the Slow-Strong mode can help meet this spec depending on the bus load. UART Mode : This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based UART in the system, if required. SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and supports an EzSPI mode in which the data interchange is reduced to reading and writing an array in memory. GPIO PSoC 4XX8 BLE 4.2 has 36 GPIOs. The GPIO block implements the following: ■ Eight drive strength modes: ❐ Analog input mode (input and output buffers disabled) ❐ Input only ❐ Weak pull-up with strong pull-down ❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down ❐ Open drain with strong pull-up ❐ Strong pull-up with strong pull-down ❐ Weak pull-up with weak pull-down ■ Input threshold select (CMOS or LVTTL) ■ Pins 0 and 1 of Port 5 are overvoltage-tolerant pins ■ Individual control of input and output buffer enabling/disabling in addition to drive-strength modes ■ Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes) ■ Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multi- plexing complexity (these sig nals do not go through the DSI network). DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network. Data output and pin-state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC 4XX8 BLE 4.2).

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 10 of 47 Special-Function Peripherals LCD Segment Drive PSoC 4XX8 BLE 4.2 has an LCD controller, which can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. The digital correlation method modulates the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. The PWM method drives the panel with PWM signals to effec- tively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep mode, refreshing a small display buffer (four bits; one 32-bit register per port). CapSense CapSense is supported on all pins in PSoC 4XX8 BLE 4.2 through a CapSense Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A Component is provided for the CapSense block to make it easy for the user. The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Liquid tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. The CapSense block has two IDACs which can be used for general purposes if CapSense is not being used (both IDACs are available in that case) or if CapSense is used without liquid tolerance (one IDAC is available).

pins support CSD CapSense and analog mux bus connections. Table 1. PSoC 4XX8 BLE 4.2 Pin List (QFN Package)

4 XRES RESET Reset, active LOW

9 VSSD GROUND Digital ground

11 GANT1 GROUND Antenna shielding ground

12 ANT ANTENNA Antenna pin

13 GANT2 GROUND Antenna shielding ground

16 XTAL24I CLOCK 24-MHz crystal or external clock input

17 XTAL24O CLOCK 24-MHz crystal

55 VSSA GROUND Analog ground

56 VCCD POWER Regulated 1.8-V supply, connect to 1.3-µF capacitor.

57 EPAD GROUND Ground paddle for the QFN package

Table 2. PSoC 4XX8 BLE 4.2 Pin List (WLCSP Package) Table 1. PSoC 4XX8 BLE 4.2 Pin List (QFN Package) (continued)

Table 2. PSoC 4XX8 BLE 4.2 Pin List (WLCSP Package) (continued)

switches that routes GPIOs to the resources inside the device. Table 3. HSIOM Port Settings

0 Firmware-controlled GPIO

1 Output is firmware-controlled, but Output Enable (OE)

2 Both output and OE are controlled from DSI.

3 Output is controlled from DSI, but OE is

4 Pin is a CSD sense pin

5 Pin is a CSD shield pin

6 Pin is connected to AMUXA

7 Pin is connected to AMUXB

8 Pin-specific Active function #0

9 Pin-specific Active function #1

10 Pin-specific Active function #2

11 Reserved

12 Pin is an LCD common pin

13 Pin is an LCD segment pin

14 Pin-specific Deep-Sleep function #0

15 Pin-specific Deep-Sleep function #1

Table 3. HSIOM Port Settings (continued)

The selection of peripheral function for different GPIO pins is given in Table 4. Table 4. Port Pin Connections

shown in Table 1). A typical system application connection diagram is shown in Figure 7. Figure 7. System Application Connection Diagram device continues to function down to 1.71 V without RF. simulated to design and obtain optimal bypassing. VCCD 1.3-µF ceramic capacitor at the VCCD pin. with a 1-µF to 10-µF capacitor.

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 17 of 47 Development Support The PSoC 4XX8 BLE 4.2 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit www.cypress.com/go/psoc4ble to find out more. Documentation A suite of documentation supports the PSoC 4XX8 BLE 4.2 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software User Guide : A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component Datasheets : The flexibility of PSoC allows the creation of new peripherals (Components) long after the device has gone into production. Component datasheets provide all of the information needed to select and use a particular Component, including a functional description, API documen- tation, example code, and AC/DC specifications. Application Notes: PSoC application notes discuss a particular application of PSoC in depth; examples include creating standard and custom BLE profiles. Application notes often include example projects in addition to the application note document. Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete de scription of all PSoC registers. The TRM is available in the Documentation section at www.cypress.com/psoc4. Online In addition to print documentation, the Cypress PSoC forums connect you with fellow PSoC users and experts in PSoC from around the world, 24 hours a day, 7 days a week. Tools With industry standard cores, programming, and debugging interfaces, the PSoC 4XX8 BLE 4.2 family is part of a devel- opment tool eco system. Visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits.

1. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Table 5. Absolute Maximum Ratings[1] Table 6. DC Specifications

3 MHz

Table 6. DC Specifications (continued)

Table 7. AC Specifications

1. V IH must not exceed VDDD + 0.2 V.

Table 8. GPIO DC Specifications Table 9. GPIO AC Specifications

Table 9. GPIO AC Specifications (continued) Table 10. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Table 11. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Table 12. XRES DC Specifications

Table 13. XRES AC Specifications Table 14. Opamp Specifications

Table 14. Opamp Specifications (continued)

1. ULP LCOMP operating conditions:

Table 15. Comparator DC Specifications[3]

Table 15. Comparator DC Specifications[3] (continued)

1. ULP LCOMP operating conditions:

Table 16. Comparator AC Specifications[4] Table 17. Temperature Sensor Specifications Table 18. SAR ADC DC Specifications

Table 19. SAR ADC AC Specifications Table 20. CSD Block Specifications

Table 21. Timer DC Specifications Table 22. Timer AC Specifications Table 23. Counter DC Specifications Table 24. Counter AC Specifications Table 25. PWM DC Specifications

Table 26. PWM AC Specifications Table 27. Fixed I2C DC Specifications Table 28. Fixed I2C AC Specifications Table 29. LCD Direct Drive DC Specifications

50 Hz at 25 °C

LCD system operating current. Table 30. LCD Direct Drive AC Specifications Table 31. Fixed UART DC Specifications

Table 32. Fixed UART AC Specifications Table 33. Fixed SPI DC Specifications Table 34. Fixed SPI AC Specifications Table 35. Fixed SPI Master Mode AC Specifications MISO valid before Sclock capturing edge. Table 36. Fixed SPI Slave Mode AC Specifications Table 37. Flash DC Specifications

1. It can take as much as 20 milliseconds to write to flash. Du ring this time, the device should not be reset, or flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Table 38. Flash AC Specifications Table 39. POR DC Specifications Table 40. POR AC Specifications Table 41. Brown-Out Detect Table 42. Hibernate Reset

Table 43. Voltage Monitor DC Specifications Table 44. Voltage Monitor AC Specifications Table 45. SWD Interface Specifications Table 46. IMO DC Specifications

Table 47. IMO AC Specifications

48 MHz ––± 2% With API-called

Table 48. ILO DC Specifications Table 49. ILO AC Specifications Table 50. External Clock Specifications Table 51. UDB AC Specifications

Table 52. BLE Subsystem

Table 52. BLE Subsystem (continued)

Table 53. ECO Specifications

Table 54. WCO Specifications

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 37 of 47

Ordering Information

The PSoC 4XX8 BLE 4.2 part numbers and features are listed in Table 55. Table 55. PSoC 4XXX8_BLE Part Numbers 1, 2, …, 9, A,B, …, Z) unless stated otherwise. Max CPU Speed (MHz) BLE sub-system Flash (KB) SRAM (KB) UDB Op-amp CapSense TMG (Gestures) Direct LCD Drive 12-bit SAR ADC LP Comparators TCPWM Blocks SCB Blocks PWMs (using UDBs) I2S (using UDB) GPIO PSoC 4 BLE256K: CY8C41XX CY8C4128LQI-BL543 24 √ 256 32 - 2 - - - 806 Ksps - 4 2 NA 36 QFN CY8C4128FNI-BL543 24 √ 256 32 - 2 - - - 806 Ksps - 4 2 36 CSP CY8C4128LQI-BL573 24 √ 256 32 - 2 - - - 806 Ksps 2 4 2 36 QFN CY8C4128FNI-BL573 24 √ 256 32 - 2 - - - 806 Ksps 2 4 2 36 CSP CY8C4128LQI-BL553 24 √ 256 32 - 2 √ - - 806 Ksps 2 4 2 36 QFN CY8C4128FNI-BL553 24 √ 256 32 - 2 √ - - 806 Ksps 2 4 2 36 CSP CY8C4128LQI-BL563 24 √ 256 32 - 2 - - √ 806 Ksps 2 4 2 36 QFN CY8C4128FNI-BL563 24 √ 256 32 - 2 - - √ 806 Ksps 2 4 2 36 CSP CY8C4128LQI-BL583 24 √ 256 32 - 2 √ - √ 806 Ksps 2 4 2 36 QFN CY8C4128FNI-BL583 24 √ 256 32 - 2 √ - √ 806 Ksps 2 4 2 36 CSP CY8C4128LQI-BL593 24 √ 256 32 - 2 √√√ 806 Ksps 2 4 2 36 QFN CY8C4128FNI-BL593 24 √ 256 32 - 2 √√√ 806 Ksps 2 4 2 36 CSP PSoC 4 BLE256K: CY8C42xx CY8C4248LQI-BL543 48 √ 256 32 - 2 - - - 1 Msps - 4 2 - - 36 QFN CY8C4248FNI-BL543 48 √ 256 32 - 2 - - - 1 Msps - 4 2 - - 36 CSP CY8C4248LQI-BL573 48 √ 256 32 4 4 - - - 1 Msps 2 4 2 4 √ 36 QFN CY8C4248FNI-BL573 48 √ 256 32 4 4 - - - 1 Msps 2 4 2 4 √ 36 CSP CY8C4248LQI-BL553 48 √ 256 32 4 4 √ - - 1 M s p s242 4 √ 36 QFN CY8C4248FNI-BL553 48 √ 256 32 4 4 √ - - 1 M s p s242 4 √ 36 CSP CY8C4248LQI-BL563 48 √ 256 32 4 4 - - √ 1 M s p s242 4 √ 36 QFN CY8C4248FNI-BL563 48 √ 256 32 4 4 - - √ 1 M s p s242 4 √ 36 CSP CY8C4248LQI-BL583 48 √ 256 32 4 4 √ - √ 1 M s p s242 4 √ 36 QFN CY8C4248FNI-BL583 48 √ 256 32 4 4 √ - √ 1 M s p s242 4 √ 36 CSP CY8C4248FLI-BL583 48 √ 256 32 4 4 √ - √ 1 M s p s242 4 √ 36 Thin CSP CY8C4248LQQ-BL583 48 √ 256 32 4 4 √ - √ 1 M s p s242 4 √ 36 QFN CY8C4248FNQ-BL583 48 √ 256 32 4 4 √ - √ 1 M s p s242 4 √ 36 CSP CY8C4248LQI-BL593 48 √ 256 32 4 4 √√√ 1 M s p s242 4 √ 36 QFN CY8C4248FNI-BL593 48 √ 256 32 4 4 √√√ 1 M s p s242 4 √ 36 CSP

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 38 of 47 Ordering Code Definitions The Field Values are listed in the following table: Architecture Cypress Prefix Family within Architecture Speed Grade Flash Capacity Package Code Temperature Range Attributes Code 4: P S o C 4 4: 4 8M H z 8 : 256 KB LQ : QFN I : Industrial Example CY8C 4 A E DCBF B L X Y Z - 2 : 4200 Family CY8 C BLXYZ: Attributes Field Description Values Meaning CY8C Cypress Prefix

4 Architecture 4 PSoC 4

A Family within architecture 1 4100-BLE Family 2 4200-BLE Family B CPU Speed 2 24 MHz 4 48 MHz C Flash Capacity 8, 7 256, 128 KB FN WLCSP LQ QFN FL Thin CSP F Temperature Range I Industrial BLXYZ Attributes Code BL500-BL599 BL5 indicates Bluetooth LE 4.2 support

Table 56. Package Characteristics Table 57. Solder Reflow Peak Temperature Table 58. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Table 59. Package Details

Figure 8. 56-Pin QFN 7 × 7 × 0.6 mm The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.

1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. ALL DIMENSIONS ARE IN MILLIMETERS

Figure 10. 76-Ball WLCSP Package Outline Figure 11. 76-Ball Thin WLCSP Package Outline

1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. "e" REPRESENTS THE SOLDER BALL GRID PITCH. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

1. ALL DIMENSIONS ARE IN MILLIMETERS.

0.40 BSC

3.20 BSC

4.04 BSC

3.87 BSC

METALIZED MARK, INDENTATION OR OTHER MEANS.

Table 60. Acronyms Used in this Document capabilities, no analog. See GPIO. Table 60. Acronyms Used in this Document (continued)

Table 61. Units of Measure

PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 46 of 47

Revision History

Description Title: PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 002-09848 Revision ECN Orig. of Change Submission Date Description of Change ** 5009233 WKA 12/02/2015 Initial release *A 5132452 WKA 02/10/2016 Updated typ value for SID13. Updated Conditions for SID141A, SID145, SID150, and SID154. Updated max values for Timer, Counter, and PWM specifications. *B 5302481 MARW 06/09/2016 Updated GATT features and Security Manager features. Updated SAR ADC System diagram. Updated C3 and C4 values in Figure 5. Updated values for SID56, SID380A, and SID380B. Added 76-ball thin CSP package and ordering details.

Document Number: 002-09848 Rev. *B Revised June 9, 2016 Page 47 of 47 PRELIMINARY PSoC® 4: PSoC 4XX8 BLE 4.2 Family Datasheet © Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. 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