PS9402-V

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22 fo 1 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. Preliminary Data Sheet PS9402

2.5 A OUTPUT CURRENT, HIGH CMR, IGBT, POWER MOS FET GATE DRIVE, 16-PIN SSOP PHOTOCOUPLER

DESCRIPTION

The PS9402 is an optically coupled isolator containing a GaAlAs LED on the input side and a photo diode, a signal processing circuit and a power output transistor on the output side on one chip. The PS9402 is designed specifically for high common mode transient immunity (CMR), high output current and high switching speed. The PS9402 includes desaturation detection and active miller clamping functions. The PS9402 is suitable for driving IGBTs and Power MOS FETs. The PS9402 is in a 16-pin plastic SSOP (Shrink Small Outline Package). And the PS9402 is able to high-density (surface) mounting.

FEATURES

• Long creepage distance (8 mm MIN.)
• Large peak output current (2.5 A MAX., 2.0 A MIN.)
• High speed switching (tPLH, tPHL = 200 ns MAX.)
• UVLO (Under Voltage Lock Out) protection with hysteresis
• Desaturation detection
• Miller clamping
• High common mode transient immunity (|CMH|, |CML| = 25 kV//uni03BCs MIN.)
• Embossed tape product: PS9402-E3: 850 pcs/reel
• Pb-Free product
• Safety standards
• UL approved: No. E72422
• CSA approved: No. CA 101391 (CA5A, CAN/CSA-C22.2 60065, 60950)
• DIN EN60747-5-2 (VDE0884 Part2) approved: No. 40024069 (Option)

APPLICATIONS

• IGBT, Power MOS FET Gate Driver
• Industrial inverter
• Uninterruptible Power Supply (UPS) R08DS0014EJ0100 Rev.1.00 Jun 22, 2012 VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE PIN CONNECTION (Top View) <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 2 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 PACKAGE DIMENSIONS (UNIT: mm) 0.2±0.15 10.36±0.4 0.64 MIN. 7.49+0.5 –0.1 3.5±0.2 0.71±0.3 10.31±0.5 1.270.46±0.1 0.25 M PHOTOCOUPLER CONSTRUCTION ).NIM( tinU retemaraP mm 8 ecnatsiD riA Outer Creepage Distance 8 mm mm 4.0 ecnatsiD noitalosI A Business Par tner of Renesas Electronics Corporation.

22 fo 3 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 BLOCK DIAGRAM (UNIT: mm) UVLO DESAT SHIELD SHIELD CLAMP VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE IF UVLO (VCC2 − VEE) DESAT (Pin 14: DESAT pin input) FAULT (Pin 3: FAULT pin output) VO OFF Not Active ( > VUVLO+) Not active High Low ON Not Active ( > VUVLO+) Low ( < VDESATth) High High ON Not Active ( > VUVLO+) High ( > VDESATth) Low (FAULT) Low ON Active ( < VUVLO–) Not Active High Low OFF Active ( < VUVLO–) Not Active High Low <R> <R> <R> <R> <R> <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 4 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 MARKING EXAMPLE 9402 R NT231 No. 1 pin Mark Type Number Assembly Lot Year Assembled (Last 1 Digit) 2 31TN Rank Code In-house Code (T: Pb-Free) Week Assembled Company Initial

ORDERING INFORMATION

Part Number Order Number Solder Plating Specification Packing Style Safety Standard Approval Application Part Number*1 PS9402 PS9402-AX Pb-Free 10 pcs (Tape 10 pcs cut) Standard products PS9402 PS9402-E3 PS9402-E3-AX (Ni/Pd/Au) Embossed Tape 850 (UL and CSA pcs/reel Approved) PS9402-V PS9402-V-AX 10 pcs (Tape 10 pcs cut) DIN EN60747-5-2 PS9402-V-E3 PS9402-V-E3-AX Embossed Tape 850 (VDE0884 Part2) pcs/reel Approved )noitpO( Note: *1. For the application of the Safety Standard, following part number should be used. <R> <R> <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 5 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified) Parameter Symbol Ratings Unit Forward Current *1 IF 25 mA Peak Transient Forward Current (Pulse Width < 1 /uni03BC s) IF (TRAN) 1.0 A V egatloV esreveR R 5 V Input Supply Voltage VCC1 0 to 5.5 V Input IC Power Dissipation *2 PI 80 mW High Level Peak Output Current *3 IOH (PEAK) 2.5 A Low Level Peak Output Current *3 IOL (PEAK) 2.5 A FAULT Output Current IFAULT 8 mA FAULT Pin Voltage VFAULT 0 to VCC1 V Total Output Supply Voltage (VCC2 − VEE) 0 to 33 V Negative Output Supply Voltage (VE − VEE) 0 to 15 V V egatloV tuptuO O 0 to VCC2 V Peak Clamping Sinking Current IClamp 1.7 A Miller Clamping Pin Voltage VClamp 0 to VCC2 V DESAT Voltage VDESAT VE to VE + 10 V Output IC Power Dissipation *4 PO 300 mW Isolation Voltage *5 BV 5 000 Vr.m.s. Operating Ambient Temperature TA −40 to +110 °C Storage Temperature Tstg −55 to +125 °C Notes: *1. Reduced to 0.52 mA/°C at TA = 85°C or more. *2. Reduced to 1.6 mW/°C at TA = 75°C or more. *3. Maximum pulse width = 10 /uni03BC s, Maximum duty cycle = 0.2% *4. Reduced to 5.5 mW/°C at TA = 70°C or more. *5. AC voltage for 1 minute at TA = 25°C, RH = 60% between input and output. Pins 1-8 shorted together, 9-16 shorted together. RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN. MAX. Unit Total Output Supply Voltage (VCC2 − VEE) 15 30 V Negative Output Supply Voltage (VE − VEE) 0 15 V Positive Output Supply Voltage (VCC2 − VE) 15 30 − (VE − VEE) V Forward Current (ON) IF (ON) 8 12 mA Forward Voltage (OFF) VF (OFF) −2 0.8 V Operating Ambient Temperature TA −40 110 °C <R> <R> <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 6 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 ELECTRICAL CHARACTERISTICS (DC) (at RECOMMENDED OPERATING CONDITIONS, VEE = VE = GND, unless otherwise specified) Parameter Symbol Conditions MIN. TYP. *1 MAX. Unit FAULT Logic Low Output Voltage VFAULTL IFAULT = 1.1 mA, VCC1 = 5.5 V 0.1 V FAULT Logic High Output Current IFAULTH VFAULT = 5.5 V, VCC1 = 5.5 V, TA = 25°C 0.5 /uni03BC A High Level Output Current IOH VO = (VCC2 − 4 V) *2 −0.5 −1.5 A Low Level Output Current IOL VO = (VEE + 2.5 V) *2 0.5 1.5 A V O = (VEE + 15 V) *3 2.0 Low Level Output Current During Fault Condition IOLF VO – VEE = 14 V 90 140 230 mA High Level Output Voltage VOH IO = 100 mA *4 VCC2 − 3.0 VCC2 − 1.3 V I O = −650 /uni03BC A *4 VCC2 − 2.5 VCC2 − 0.8 Low Level Output Voltage VOL IO V 5.0 51.0 Am 001 = Clamp Pin Threshold Voltage VtClamp V 0.2 Clamp Low Level Sinking Current ICL VtClamp = VEE + 2.5 V 0.35 1.5 A High Level Supply Current ICC2H IO Am 3 2 Am 0 = Low Level Supply Current ICC2L IO Am 3 2 Am 0 = Blanking Capacitor Charging Current ICHG VDESAT = 2 V −0.13 −0.24 −0.33 mA Blanking Capacitor Discharging Current IDSCHG VDESAT Am 03 01 V 7 = DESAT Threshold VDESATth VCC2 − VE > VUVLO−, VO < 5 V 6.0 6.9 7.5 V UVLO Threshold VUVLO+ VO V 5.31 6.21 0.11 V 5 > V UVLO− VO 3.21 3.11 8.9 V 5 < UVLO Hysteresis UVLOHYS (VUVLO+) − (VUVLO−) 0.4 1.3 V Threshold Input Current (L □ H) IFLH IO = 0 mA, VO > 5 V 1.5 5 mA Threshold Input Voltage (H □ L) VFHL IO = 0 mA, VO < 5 V 0.8 V Input Forward Voltage VF IF = 10 mA, TA = 25°C 1.2 1.56 1.8 V Input Reverse Current IR VR = 3 V, TA = 25°C 10 /uni03BC A Input Capacitance CIN f = 1 MHz, VF = 0 V 30 pF Notes: *1. Typical values at TA = 25°C. *2. Maximum pulse width = 50 /uni03BC s, Maximum duty cycle = 0.5% *3. Maximum pulse width = 10 /uni03BC s, Maximum duty cycle = 0.2% *4. VOH is measured with the DC load current in this testing (Maximum pulse width = 1 ms, Maximum duty cycle = 20%). <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 7 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 SWITCHING CHARACTERISTICS (AC) (at RECOMMENDED OPERATING CONDITIONS, VEE = VE = GND, unless otherwise specified) Parameter Symbol Conditions MIN. TYP. *1 MAX. Unit Propagation Delay Time (L □ H) tPLH Rg = 10 /uni03A9 , Cg = 10 nF, 50 90 200 ns Propagation Delay Time (H □ L) tPHL sn 002 011 05 ,zHk 01 = f Pulse Width Distortion (PWD) |tPHL−tPLH| Duty Cycle = 50% *2, 20 100 ns Propagation Delay Time (Difference Between Any Two Products) tPHL−tPLH IF = 10 mA, VCC2 = 30 V −100 100 ns t emiT esiR r sn 05 t emiT llaF f sn 05 Common Mode Transient Immunity at High Level Output *3 CMH TA = 25°C, IF = 10 mA, VCC2 = 30 V, VCM = 1.5 kV, CDESAT = 100 pF, RF = 2.1 k/uni03A9 , VCC1 = 5 V 25 kV//uni03BC s Common Mode Transient Immunity at Low Level Output *4 CML TA = 25°C, VF = 0 V, VCC2 = 30 V, VCM = 1.5 kV, RF = 2.1 k/uni03A9 , VCC1 = 5 V −25 kV//uni03BC s DESAT Sense to 90% VO Delay tDESAT (90%) CDESAT = 100 pF, RF = 2.1 k/uni03A9 , 250 500 ns DESAT Sense to 10% VO Delay tDESAT (10%) Rg = 10 /uni03A9 , Cg = 10 nF VCC2 = 30 V 1.5 2 3 /uni03BC s DESAT Sense to Low Level FAULT Signal Delay tDESAT (FAULT) sn 008 004 DESAT Sense to DESAT Low Propagation Delay tDESAT (LOW) sn 052 DESAT Input Mute *5 tDESAT (MUTE) 5 /uni03BC s RESET to High Level FAULT VCC1 = 5.5 V 0.3 1.2 3.0 /uni03BC s Signal Delay tRESET (FAULT) VCC1 = 3.3 V 0.5 1.5 4.0 /uni03BC s Notes: *1. Typical values at TA = 25°C. *2. This load condition is equivalent to the IGBT load at 1 200 V/150 A. *3. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 2.1 kΩ pull-up resistor is needed in fault detection mode. *4. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode *5. During muting DESAT, even if LED (IF) input occurs, IGBT operates turn-off and Vo state is kept to low. After unmuting this DESAT, when LED is turned on, Vo/FAULT becomes high state (with automatic reset). <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 8 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TEST CIRCUIT 1 VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VFAULTL IF IF VOH VCC2 IOH VCC2 VOL VCC2 VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE IFAULTH IOL VCC2 VCC1 IF2 VCC1 VO

0.1 Fμ VO

0.1 Fμ 0.1 Fμ 0.1 Fμ Fig. 1 VFAULTL Test Circuit Fig. 3 IOH Test Circuit Fig. 5 VOH V 6 .giFtiucriC tseT OL Test Circuit Fig. 4 IOL Test Circuit Fig. 2 IFAULTH Test Circuit <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 9 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TEST CIRCUIT 2 VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE IF IF ICL VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE IF ICC2H ICC2L ICHG 2 V VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE IDSCHG 7 V 2.5 V VDESAT VCC2 VCC2 VCC2 VCC2 VCC V2 CC2 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ Fig. 7 ICC2H Test Circuit Fig. 9 ICHG Test Circuit Fig. 11 ICL V 21 .giFtiucriC tseT DESAT Test Circuit Fig. 10 IDSCHG Test Circuit Fig. 8 ICC2L Test Circuit <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 01 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TEST CIRCUIT 3 VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE IF VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE IF VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE IF 10 Ω 10 nF IF VOUT FAULT VDESET 90% 10% 50% 50% 50% tDESET (LOW) tDESET (MUTE) tDESET (10%) tDESET (90%) tRESET (FAULT) tDESET (FAULT) VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE IF 2.1 kΩ 10 Ω 10 nF 100 pF tPHLtPLH IF VOUT 90% 50% 10% tr tf VCC2 VCC2 VCC2 VCC2 VDESAT VCC1 = 5 V 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ Fig. 13 VUVLO Test Circuit Fig. 15 tPLH/tPHL Test Circuit Fig. 17 tPLH/tPHL Test Wave Forms Fig. 18 tDESAT Test Wave Forms Fig. 14 IFLH Test Circuit Fig. 17 tDESAT Test Circuit <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 11 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TEST CIRCUIT 4 VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE 10 Ω 10 nF + − SCOPE VS VCC1 Fault VS Cathode Anode Anode Cathode VE VLED Desat VCC2 VEE VO Vclamp VEE 10 Ω 10 nF + − SCOPE 2.1 kΩ SCOPE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE 10 Ω 10 nF − + 2.1 kΩ SCOPE VS VCC1 Fault VS Cathode Anode Anode Cathode V E VLED Desat VCC2 VEE VO Vclamp VEE 10 Ω 10 nF − + VOH VOL 1 V 15 V 1 500 V VCM 0 V VO (CMH: IF = 10 mA) VO (CML: IF = 0 mA) tr tf 90% 10% GND OPEN 0.8 V 2 V 1 500 V VCM 0 V VFAULT (CMH: IF = 10 mA, DESAT) VFAULT (CML: IF = 0 mA, DESAT) tr tf 90% 10% VCC2 VCC2 VCC1 VCC2 100 pF VCC1 VCC2 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ Fig. 19 CMH Test Circuit (LED1 ON) Fig. 21 CMH Test Circuit (LED2 ON) Fig. 23 CMH, CML Test Wave Forms (LED1 ON, OFF) Fig. 24 CMH, CML Test Wave Forms (LED2 ON, OFF) Fig. 22 CML Test Circuit (LED2 OFF) Fig. 20 CML Test Circuit (LED1 OFF) <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 21 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TYPICAL CHARACTERISTICS (TA = 25° C, unless otherwise specified) Ambient Temperature TA (°C) Output IC Power Dissipation PO (mW) OUTPUT IC POWER DISSIPATION vs. AMBIENT TEMPERATURE 100 150 200 250 300 350 400 Ambient Temperature TA (°C) Threshold Input Current IFLH (mA) THRESHOLD INPUT CURRENT vs. AMBIENT TEMPERATURE VCC2 = 30 V, VEE = GND, VO > 5 V −40 −20 0 20 40 60 80 100 Forward Current IF (mA) Output Voltage VO (V) OUTPUT VOLTAGE vs. FORWARD CURRENT VCC = 30 V, VEE = GND 10 2 43 5 Ambient Temperature TA (°C) Input IC Power Dissipation PI (mW) INPUT IC POWER DISSIPATION vs. AMBIENT TEMPERATURE 250 50 75 100 1250 120 100 250 50 75 100 125 High Level Output Voltage – Output Supply Voltage VOH – VCC 2 (V) High Level Output Current IOH (A) HIGH LEVEL OUTPUT VOLTAGE – OUTPUT SUPPLY VOLTAGE vs. HIGH LEVEL OUTPUT CURRENT 0.0 −5.0 −4.0 −3.0 −2.0 −1.0 VCC = 30 V, VEE = GND, IF = 10 mA −40°C TA = 110°C 25°C Forward Voltage VF (V) Forward Current IF (mA) FORWARD CURRENT vs. FORWARD VOLTAGE 1.0 0.01 0.1 1.0 100 TA = +100°C +85°C +50°C +25°C 0°C −40°C Remark The graphs indicate nominal characteristics. <R> A Business Par tner of Renesas Electronics Corporation.

22 fo 31 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 Output Supply Voltage VCC2 (V) PROPAGATION DELAY TIME, PULSE WIDTH DISTORTION vs. OUTPUT SUPPLY VOLTAGE Propagation Delay Time tPHL, tPLH (ns), Pulse Width Distortion (PWD) tPHL – tPLH (ns) Propagation Delay Time tPHL, tPLH (ns), Pulse Width Distortion (PWD) tPHL – tPLH (ns) 15 20 25 30 VEE = GND, IF = 10 mA, Rg = 10 Ω, Cg = 10 nF, f = 10 kHz, Duty cycle = 50% 200 150 100 tPHL PWD tPLH PROPAGATION DELAY TIME, PULSE WIDTH DISTORTION vs. LOAD CAPACITANCE Load Capacitance Cg (nF) 0 10 20 30 40 50 VCC2 = 30 V, VEE = GND, IF = 10 mA, Rg = 10 Ω, f = 10 kHz, Duty cycle = 50% tPHL tPLH PWD PROPAGATION DELAY TIME, PULSE WIDTH DISTORTION vs. LOAD RESISTANCE VCC2 = 30 V, VEE = GND, IF = 10 mA, Cg = 10 nF, f = 10 kHz, Duty cycle = 50% tPHL PWD tPLH Load Resistance Rg (Ω) Propagation Delay Time tPHL, tPLH (ns), Pulse Width Distortion (PWD) tPHL – tPLH (ns) Propagation Delay Time tPHL, tPLH (ns), Pulse Width Distortion (PWD) tPHL – tPLH (ns) PROPAGATION DELAY TIME, PULSE WIDTH DISTORTION vs. AMBIENT TEMPERATUREAmbient Temperature TA (°C) 0−40 −20 20 40 60 80 VCC2 = 30 V, VEE = GND, IF = 10 mA, Rg = 10 Ω, Cg = 10 nF, f = 10 kHz, Duty cycle = 50% tPHL tPLH 100 PWD 200 150 100 0 10 20 30 40 50 200 150 100 200 150 100 Low Level Output Current IOL (A) Low Level Output Voltage VOL (V) LOW LEVEL OUTPUT VOLTAGE vs. LOW LEVEL OUTPUT CURRENT 0.0 5.0 4.0 3.0 2.0 1.0 VCC = 30 V, VEE = GND, IF = 0 mA −40°C 25°CTA = 110°C Forward Current IF (mA) PROPAGATION DELAY TIME, PULSE WIDTH DISTORTION vs. FORWARD CURRENT Propagation Delay Time tPHL, tPLH (ns), Pulse Width Distortion (PWD) tPHL – tPLH (ns) 7 10 13 16 VCC2 = 30 V, VEE = GND, Rg = 10 Ω, Cg = 10 nF, f = 10 kHz, Duty cycle = 50% 200 150 100 tPHL PWD tPLH Remark The graphs indicate nominal characteristics. A Business Par tner of Renesas Electronics Corporation.

22 fo 41 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 Ambient Temperature TA (°C) High Level Output Voltage – Output Supply Voltage VOH – VCC2 (V) HIGH LEVEL OUTPUT VOLTAGE – OUTPUT SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 0.0 −3.0 −2.5 −2.0 −1.5 −1.0 −0.5 100 −20 0 20 40 8060−40 100 VCC2 = 30 V, VEE = GND, IF = 10 mA Ambient Temperature TA (°C) High Level Output Current IOH (A) HIGH LEVEL OUTPUT CURRENT vs. AMBIENT TEMPERATURE Ambient Temperature TA (°C) Low Level Output Voltage VOL (V) LOW LEVEL OUTPUT VOLTAGE vs. AMBIENT TEMPERATURE 0.5 0.1 0.2 0.3 0.4 V CC2 = 30 V, VEE = GND, IF = 10 mA, IO = 100 mA Ambient Temperature TA (°C) Low Level Output Current IOL (A) LOW LEVEL OUTPUT CURRENT vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 100 VCC2 = 30 V, VEE = GND, IF = 10 mA −20 0 20 40 8060−40 100 V CC2 = 30 V, VEE = GND, IF = 10 mA –100 mA IO = –650 A VO = VCC2 −4 V VO = VEE +15 V VEE +2.5 V VCC2 −15 V μ Ambient Temperature TA (°C) HIGH LEVEL SUPPLY CURRENT, LOW LEVEL SUPPLY CURRENT vs. AMBIENT TEMPERATURE High Level Supply Current ICCH (mA), Low Level Supply Current ICCL (mA) −20 0 20 40 8060−40 3.0 2.5 2.0 1.5 1.0 0.5 100 VCC2 = 30 V, VEE = GND, VO = OPEN ICC2H (IF = 10 mA) ICC2L (IF = 0 mA) Output Supply Voltage VCC2 (V) HIGH LEVEL SUPPLY CURRENT, LOW LEVEL SUPPLY CURRENT vs. OUTPUT SUPPLY VOLTAGE High Level Supply Current ICCH (mA), Low Level Supply Current ICCL (mA) 030251 25 VEE = GND, VO = OPEN ICC2H (IF = 10 mA) ICC2L (IF = 0 mA) 3.0 2.5 2.0 1.5 1.0 0.5 Remark The graphs indicate nominal characteristics. A Business Par tner of Renesas Electronics Corporation.

22 fo 51 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 Ambient Temperature TA (°C) Blanking Capacitor Discharging Current IDSCHG (mA) BLANKING CAPACITOR DISCHARGING CURRENT vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 100 VCC2 = 30 V, VEE = VE = GND, IF = 0 mA, VDESAT = 7 V Ambient Temperature TA (°C) DESAT Threshold VDESATth (V) DESAT THRESHOLD vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 100 7.5 6.0 6.3 6.9 6.6 7.2 VEE = VE = GND, VCC2 > VUVLO−, VO < 5 V, IF = 10 mA Ambient Temperature TA (°C) DESAT Sense to 90% VO Delay tDESAT (90%) (ns) −20 0 20 40 8060−40 100 500 100 300 200 400 DESAT SENSE TO 90% VO DELAY vs. AMBIENT TEMPERATURE VEE = VE = GND, Rg = 10 Ω, Cg = 10 nF, RF = 2.1 kΩ, CDESAT = 100 pF, VCC1 = 5 V VCC2 = 30 V 15 V Ambient Temperature TA (°C) DESAT Sense to 10% VO Delay tDESAT (10%) ( s) −20 0 20 40 8060−40 100 3.0 0.0 1.0 0.5 2.0 1.5 2.5 DESAT SENSE TO 10% VO DELAY vs. AMBIENT TEMPERATURE VCC1 = 5 V, VEE = VE = GND, Rg = 10 Ω, Cg = 10 nF, RF = 2.1 kΩ, CDESAT = 100 pF VCC2 = 30 V 15 V μ Ambient Temperature TA (°C) Clamp Low Level Sinking Current ICL (A) CLAMP LOW LEVEL SINKING CURRENT vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 100 VCC2 = 30 V, VEE = VE = GND, VtClamp = 2.5 V Ambient Temperature TA (°C) Blanking Capacitor Charging Current ICHG (mA) BLANKING CAPACITOR CHARGING CURRENT vs. AMBIENT TEMPERATURE −20 0 20 40 8060−40 100 −0.10 −0.35 −0.30 −0.20 −0.25 −0.15 VCC2 = 30 V, VEE = VE = GND, IF = 10 mA, VDESAT = 2 V Remark The graphs indicate nominal characteristics. A Business Par tner of Renesas Electronics Corporation.

22 fo 61 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 IF = 10 mA, VEE = GND OUTPUT VOLTAGE vs. SUPPLY VOLTAGE Supply Voltage VCC2 – VEE (V) Output Voltage VO (V) 0 5 10 15 20 UVLOHYS VUVLO+VUVLO− (12.6 V)(11.3 V) Load Resistance Rg (Ω) Power Consumption Per Cycle ESW ( J) 20 40300 10 50 POWER CONSUMPTION PER CYCLE vs. LOAD RESISTANCE Qg = 1 000 nC Qg = 100 nC Qg = 500 nC μ Load Resistance Rg (Ω) DESAT Sense to 10% VO Delay tDESAT (10%) ( s) 20 403010 50 3.0 0.0 1.0 0.5 2.0 1.5 2.5 DESAT SENSE TO 10% VO DELAY vs. LOAD RESISTANCE VCC1 = 5 V, VEE = VE = GND, Cg = 10 nF, RF = 2.1 kΩ, CDESAT = 100 pF VCC2 = 30 V 15 V Load Capacitance Cg (nF) DESAT Sense to 10% VO Delay tDESAT (10%) ( s) 20 403010 50 12.0 0.0 6.0 3.0 9.0 DESAT SENSE TO 10% VO DELAY vs. LOAD CAPACITANCE VCC1 = 5 V, VEE = VE = GND, RF = 2.1 kΩ, Rg = 10 Ω, CDESAT = 100 pF VCC2 = 30 V 15 V μμ Remark The graphs indicate nominal characteristics. A Business Par tner of Renesas Electronics Corporation.

22 fo 71 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 TAPING SPECIFICATIONS (UNIT: mm) Packing: 850 pcs/reel 2.0±0.5 R 1.0 13.0±0.2φ 3.5φ 21.0±0.8φ 330±2.0φ 100±1.0φ 4.5±0.1 3.8±0.1 0.35 10.8±0.1 4.0±0.1 2.0±0.1 11.5±0.1 1.75±0.1 φ1.55±0.1 24±0.3 16±0.1 10.9±0.1 2.0±0.5 23.9 to 27.4 Outer edge of flange 29.5±1.0 25.5±1.0 φ1.5+0.1 PS9402-E3Tape Direction Outline and Dimensions (Tape) Outline and Dimensions (Reel)

22 fo 81 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 RECOMMENDED MOUNT PAD DIMENSIONS (UNIT: mm) Part Number PS9402 Lead Bending A lead bending type (Gull-wing) for surface mount 9.85 B 1.27 C 0.96 D 1.65 D CB A <R>

22 fo 91 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 NOTES ON HANDLING 1. Recommended soldering conditions (1) Infrared reflow soldering 062 erutarepmet wolfer kaeP • °C or below (package surface temperature)

• Time of peak reflow temperature 10 seconds or less
• Time of temperature higher than 220°C 60 seconds or less
• Time to preheat temperature from 120 to 180°C 120±30 s eerhT swolfer fo rebmuN • xulf ehT( enirolhc fo tnuoma llams gniniatnoc xulf nisoR xulF • with a maximum chlorine content of 0.2 Wt% is recommended.) 120±30 s (preheating) 220°C 180°C Package Surface Temperature T (°C) Time (s) Recommended Temperature Profile of Infrared Reflow (heating) to 10 s to 60 s 260°C MAX. 120°C (2) Wave soldering
• Temperature 260°C or below (molten solder temperature)
• Time 10 seconds or less
• Preheating conditions 120°C or below (package surface temperature)
• Number of times One (Allowed to be dipped in solder including plastic mold portion.)
• Flux Rosin flux containing small amount of chlorine (The flux with a maximum chlorine content of 0.2 Wt% is recommended.) (3) Soldering by Soldering Iron
• Peak Temperature (lead part temperature) 350°C or below ssel ro sdnoces 3 )snip hcae( emiT • a htiw xulf ehT( enirolhc fo tnuoma llams gniniatnoc xulf nisoR xulF • maximum chlorine content of 0.2 Wt% is recommended.) (a) Soldering of leads should be made at the point 1.5 to 2.0 mm from the root of the lead (4) Cautions
• Fluxes Avoid removing the residual flux with freon-based and chlorine-based cleaning solvent. 2. Cautions regarding noise Be aware that when voltage is applied suddenly between the photocoupler’s input and output at startup, the output transistor may enter the on state, even if the voltage is within the absolute maximum ratings.

22 fo 02 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 USAGE CAUTIONS 1. This product is weak for static electricity by designed with high-speed integrated circuit so protect against static electricity when handling. 2. Board designing (1) By-pass capacitor of more than 0.1 /uni03BCF is used between VCC and GND near device. Also, ensure that the distance between the leads of the photocoupler and capacitor is no more than 10 mm. (2) When designing the printed wiring board, ensure that the pattern of the IGBT collectors/emitters is not too close to the input block pattern of the photocoupler. If the pattern is too close to the input block and coupling occurs, a sudden fluctuation in the voltage on the IGBT output side might affect the photocoupler’s LED input, leading to malfunction or degradation of characteristics. (If the pattern needs to be close to the input block, to prevent the LED from lighting during the off state due to the abovementioned coupling, design the input-side circuit so that the bias of the LED is reversed, within the range of the recommended operating conditions, and be sure to thoroughly evaluate operation.) 3. Make sure the rise/fall time of the forward current is 0.5 /uni03BCs or less. 4. In order to avoid malfunctions, make sure the rise/fall slope of the VCC2 is 3 V//uni03BCs or less. 5. Avoid storage at a high temperature and high humidity. <R> <R>

22 fo 12 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 SPECIFICATION OF VDE MARKS LICENSE DOCUMENT tinU .cepS lobmyS retemaraP Climatic test class (IEC 60068- 12/011/04 )1-86006 NE NID/1 Dielectric strength maximum operating isolation voltage Test voltage (partial discharge test, procedure a for type test and random test) Upr = 1.6 × UIORM., Pd < 5 pC UIORM Upr 1 130 1 808 Vpeak Vpeak Test voltage (partial discharge test, procedure b for all devices) Upr = 1.875 × UIORM., Pd < 5 pC Upr 2 119 Vpeak U egatlovrevo elbissimrep tsehgiH TR 8 000 Vpeak 2 )1 traP 0110EDV 1-46606 NE NID( noitullop fo eergeD Comparative tracking index (IEC 60112/DIN EN 60112 (VDE 0303 Part 11)) CTI 175 Material group (DIN EN 60664 a III )1 traP 0110EDV 1- T egnar erutarepmet egarotS stg –55 to +125 °C T egnar erutarepmet gnitarepO A –40 to +110 °C Isolation resistance, minimum value VIO = 500 V dc at TA = 25°C VIO = 500 V dc at TA MAX. at least 100°C Ris MIN. Ris MIN. 1012 1011 /uni03A9 /uni03A9 Safety maximum ratings (maximum permissible in case of fault, see thermal derating curve) Package temperature Current (input current IF, Psi = 0) Power (output or total power dissipation) Isolation resistance VIO = 500 V dc at TA = Tsi Tsi Isi Psi Ris MIN. 175 400 700 109 mA mW /uni03A9 <R>

22 fo 22 egaP 00.1.veR 0010JE4100SD80R Jun 22, 2012 Caution GaAs Products This product uses gallium arsenide (GaAs). GaAs vapor and powder are hazardous to human health if inhaled or ingested, so please observe the following points.

• Follow related laws and ordinances when disposing of the product. If there are no applicable laws and/or ordinances, dispose of the product as recommended below. 1. Commission a disposal company able to (with a license to) collect, transport and dispose of materials that contain arsenic and other such industrial waste materials. 2. Exclude the product from general industrial waste and household garbage, and ensure that the product is controlled (as industrial waste subject to special control) up until final disposal.
• Do not burn, destroy, cut, crush, or chemically dissolve the product.
• Do not lick the product or in any way allow it to enter the mouth.

All trademarks and registered trademarks are the property of their respective owners. C - 1 Rev. Date Page Summary

0.01 May 09, 2011 − First edition issued

1.00 Jun 22, 2012 Throughout Prelimi nary Data Sheet - > Data Sheet

Throughout Safety standards approved p.3 Modification of BLOCK DIAGRAM p.4 Modification of MARKING EXAMPLE p.5 Modification of ABSOLUTE MAXIMUM RATINGS p.6 Modification of ELECTRICAL CHARACTERISTICS (DC) p.7 Modification of SWITCHING CHARACTERISTICS (AC) pp.8 to 11 Modification of TEST CIRCUIT pp.12 to 16 Addition of TYPICAL CHARACTERISTICS p.18 Addition of RECOMMENDED MOUNT PAD DIMENSIONS p.20 Modification of USAGE CAUTIONS p.21 Addition of SPECIFICATION OF VDE MARKS LICENSE DOCUMENT