CY25200_12 CYPRESS | Alldatasheet
Document overview
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Technical content
Datasheet sections
Features
■ Wide Operating Output (SSCLK) Frequency Range ❐ 3 to 200 MHz ■ Programmable Spread Spectrum with Nominal 31.5 kHz modulation Frequency ■ Center Spread: ±0.25% to ±2.5% ■ Down Spread: –0.5% to –5.0% ■ Input Frequency Range ❐ External crystal: 8 to 30 MHz fundamental crystals ❐ External reference: 8 to 166 MHz clock ■ Integrated Phase-Locked Loop (PLL) ■ Programmable Crystal Load Capacitor Tuning Array ■ Low Cycle-to-Cycle Jitter ■ 3.3 V Operation with 2.5 V Output Clock Drive Option ■ Spread Spectrum On and Off Function ■ Power Down or Output Enable Function ■ Output Frequency Select Option ■ Field-Programmable ■ Package: 16 Pin TSSOP
Description
The CY25200 is a programmable clock generator with spread spectrum capability. Spread s pectrum modulates the output clock frequency over a small range, spreading the energy and reducing the energy peak. This is a powerful technique to reduce EMI in a variety of applications. It uses either an external reference clock or a crystal for an input. It also uses a PLL to generate a spread spectrum output clock that can be a different frequency than the input. Up to six output clocks are available and up to two of them can be REFCLKs (copies of the input clock, without spread). The CY25200 is highly configur able. Programmable variables include the input and output frequencies, spread percentage, center spread or down spread, and control pin functions. The oscillator pin capacitance can also be programmed to match the load capacitance requirement (C L)of the crystal, eliminating the need for external capacitors. Available features include Output Enable, Power Down, Spread On/Off, Frequency Select, and the option to power some output clocks at 2.5 V. Cypress’ web-based CyberClocks Online software is used to configure the device. Programmability enables fast prototyping, which is particularly useful when doing EMC testing and determining the optimal spread settings. Divider PLL SSCLK3 Q P VCO SSCLK2 SSCLK4 SSCLK5/REFOUT/CP2 SSCLK6/REFOUT/CP3 Bank 1 Divider Bank 2 Output Select SSCLK1 Matrix VDDLAVSSAVDD VSS VSSLVDD CP0 CP1 2 35 13 11 6 41 0 XIN/CLKIN OSC. XOUT CXIN CXOUT Logic Block Diagram [+] Feedback
Figure 1. Pin Diagram today’s high speed digital electronic systems. smaller or larger spread % amounts, if required.
- Pins are programmed to be any of the following control signals: OE: Output Enable, OE = 1, all the SSCLK outputs are enabled; PD#: Power down, PD# = 0, all the
CLKSEL: SSCLK Output Frequency Select.See Control Pins (CP0, CP1, CP2 and CP3) for control pins programming options. Table 1. Pin Summary
updates, and eliminates issues with old and out of date inventory. CY3672 programmer with the CY3695 socket adapter. www.cyberclocksonline.com website. Table 2. Fixed Function Pins Table 3. Multi-Function Pins
■ CLKSEL (Clock select): frequency select for all SSCLK outputs. three-stated and the part enters a low power state. not available on CP2 or CP3. The pinout for the above example is shown in Figure 2. Figure 2. Example Pin Diagram frequencies that are derived of f of a common PLL frequency.
66.666 MHz are both derived from a PLL frequency of 400 MHz,
two different but related frequencies as explained above. (pin 15) are used as output clocks. feature eliminates the need for external crystal load capacitors. frequency. SSCLK[1:4] are fixed function output clocks (SSCLK).
2.5 V output drive option, th e maximum output frequency on
–5.0% down spread. The granularity is 0.25%. Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout Table 4. Using Clock Select, CLKSEL Control Pin
14.318 MHz XOUT
Document Number: 38-07633 Rev. *H Page 8 of 15 Informational Graphs The informational graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5 Fnominal 0 20 40 60 80 100 120 140 160 180 200 Time (us) Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 Time (us) Fnominal 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 0 20 40 60 80 100 120 140 160 180 200 Time (us) Fnominal 68.5 67.5 66.5 65.5 64.5 63.5 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 0 20 40 60 80 100 120 140 160 180 200 Time (us) Fnominal 67.5 66.5 65.5 64.5 [+] Feedback
Document Number: 38-07633 Rev. *H Page 9 of 15 Absolute Maximum Rating Storage Temperature (non-condensing) ... –55 C to +125 C (per MIL-STD-883, Method 3015) Recommended Crystal Specifications Parameter Description Comments Min Typ Max Unit FNOM Nominal Crystal Frequency Parallel resonance, fundamental mode, AT cut 8– 3 0 M H z CLNOM Nominal Load Capacitance Internal load caps 6 – 30 pF R1 Equivalent Series Resistance (ESR) Fundamental mode – – 25 R3/R1 Ratio of Third Overtone Mode ESR to Fundamental Mode ESR Ratio used because typical R1 values are much less than the maximum specification 3– – DL Crystal Drive Level No external series resistor assumed – 0.5 2 mW Recommended Operating Conditions Parameter Description Min Typ Max Unit VDD Operating Voltage 3.135 3.3 3.465 V VDDLHI Operating Voltage 3.135 3.3 3.465 V VDDLLO Operating Voltage 2.375 2.5 2.625 V TAC Ambient Commercial Temp 0 – 70 C CLOAD Maximum Load Capacitance VDD/VDDL = 3.3 V – – 15 pF CLOAD Maximum Load Capacitance VDDL = 2.5 V – – 15 pF FSSCLK-HighVoltage SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL = 3.3 V 3 – 200 MHz FSSCLK-LowVoltage SSCLK1/2/3/4 when VDD = AVDD = 3.3 V and VDDL = 2.5 V 3 – 166 MHz REFOUT REFOUT when VDD = AVDD = 3.3 V and VDDL = 3.3 V or 2.5 V 8 – 166 MHz fREF1 Clock Input 8 – 166 MHz fREF2 Crystal Input 8 – 30 MHz tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms Parameter[2] Name Description Min Typ Max Unit IOH3.3 Output High Current V OH = VDD – 0.5 V, VDD/VDDL = 3.3 V 12 24 – mA IOL3.3 Output Low Current V OL = 0.5 V, VDD/VDDL = 3.3 V 12 24 – mA IOH2.5 Output High Current V OH = VDDL – 0.5 V, VDDL = 2.5 V 8 16 – mA IOL2.5 Output Low Current V OL = 0.5 V, VDDL = 2.5 V 8 16 – mA VIH Input High Voltage CMOS levels, 70% of V DD 0.7 – 1.0 V DD VIL Input Low Voltage CMOS levels, 30% of V DD 0– 0 . 3 V DD IVDD [3] Supply Current AV DD/VDD Current – – 33 mA IVDDL2.5 [3] Supply Current V DDL Current (VDDL = 2.625 V) – – 20 mA IVDDL3.3 [3] Supply Current V DDL Current (VDDL = 3.465 V) – – 26 mA IDDS Power Down Current V DD = VDDL = AVDD = 3.465 V – – 50 A IOHZ IOLZ Output Leakage V DD = VDDL = AVDD = 3.465 V – – 10 A Notes 2. Not 100% tested, guaranteed by design. 3. I VDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks. [+] Feedback
Document Number: 38-07633 Rev. *H Page 10 of 15 Parameter Description Condition Min Typ Max Unit DC Output Duty Cycle SSCLK, Measured at V DD/2 45 50 55 % Output Duty Cycle REFCLK, Measured at V DD/2 Duty Cycle of CLKIN = 50%. 40 50 60 % SR1 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, V DD = VDDL = 3.3 V 0.6 – 2.0 V/ns SR2 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 100 MHz, VDD = VDDL = 3.3 V 0.8 – 3.5 V/ns SR3 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, V DD = VDDL = 2.5 V 0.5 – 2.2 V/ns SR4 Rising/Falling Edge Slew Rate SSCLK1/2/3/4 100 MHz, VDD = VDDL = 2.5 V 0.6 – 3.0 V/ns SR5 Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, V DD = VDDL = 3.3 V 0.6 – 1.9 V/ns SR6 Rising/Falling Edge Slew Rate SSCLK5/6 100 MHz, VDD = VDDL = 3.3 V 1.0 – 2.9 V/ns TCCJ1 Cycle-to-Cycle Jitter SSCLK1/2/3/4 CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V –– 1 1 0 p s CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 170 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 140 ps CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 290 ps TCCJ2 Cycle-to-Cycle Jitter SSCLK5/6=REFOUT CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 100 ps CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 120 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 180 ps CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3 V – – 180 ps TCCJ3 Cycle-to-Cycle Jitter SSCLK1/2/3/4 CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V –– 1 1 0 p s CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V – – 170 ps CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V – – 190 ps CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread and SSCLK5/6 = REFOUT, VDD = 3.3 V, VDDL = 2.5 V – – 330 ps TSTP Power Down Time Time from falling edge on PD# to stopped outputs (Asynchronous) – 150 300 ns TOE1 Output Disable Time Time from falling edge on OE to stopped outputs (Asynchronous) – 150 300 ns TOE2 Output Enable Time Time from risi ng edge on OE to outputs at a valid frequency (Asynchronous) – 150 300 ns FMOD Spread Spectrum Modulation Frequency SSCLK1/2/3/4/5/6 30.0 31.5 33.0 kHz TPU1 Power Up Time, Crystal is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) –35 m s TPU2 Power Up Time, Reference clock is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) –23 m s TSKEW [4] Clock Skew Output to output skew between related clock outputs. Measured at VDD/2. – – 250 ps Note 4. Skew and phase alignment is guaranteed within all SSCLK outputs and within both REFOUT outputs. All SSCLK outputs are related , and all REOUT outputs are related, but SSCLK and REFOUT outputs are not related to each other. [+] Feedback
Document Number: 38-07633 Rev. *H Page 11 of 15 Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configura- tions table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales Representative for more information. Possible Configurations Ordering Code Definitions
Ordering Information
Ordering Code Package Type Programming Operating Temperature Range CY25200KFZXC 16-Pin TSSOP (Pb-free) Field Commercial, 0 to 70 C CY25200KFZXCT 16-Pin TSSOP – Tape and Reel (Pb-free) Field Commercial, 0 to 70 C Programmer CY3672-USB Programmer for Field Programmable Devices N/A N/A CY3695 CY22050/CY22150/CY25200 Socket Adapter for CY3672-USB N/A N/A Ordering Code[5] Package Type Programming Operating Temperature Range CY25200K-ZXCxxxw 16-Pin TSSOP (Pb-fr ee) Factory Commercial, 0 to 70 C CY25200K-ZXCxxxwT 16-Pin TSSOP – Tape and Reel (Pb-free) Factory Commercial, 0 to 70 C T = Tape and Reel; blank = Tube Custom configuration code (factory programmed device only) Temperature: C or I or blank; C = commercial; I = industrial X = Pb-free package Package: Z = TSSOP; S or blank = SOIC Programming: F = field programmable; blank = factory programmed Device part number Company ID: CY = Cypress 25200KCY (Z) X (T) (F) (C) (–xxx) Table 5. 16-pin TSSOP Package Characteristics
- “xxx” denotes a specific device configur ation, and is referred to as the “dash number”. “w” denotes the configuration revision.
Figure 8. 16-pin TSSOP 4.40 mm Body ZZ16
Document Number: 38-07633 Rev. *H Page 13 of 15 Acronyms Document Conventions Units of Measure Acronym Description CMOS complementary metal oxide semiconductor EMC electro magnetic compatibility EMI electro magnetic interference FAE field application engineer OE output enable OSC oscillator PLL phase locked loop SSC Spread Spectrum Clock SSCG Spread Spectrum Clock Generator TSSOP thin shrunk small outline package Symbol Unit of Measure °C degree Celsius ohms k kilo ohms kHz kilo Hertz MHz Mega Hertz µA micro Amperes ms milli seconds mW milli Watts ns nano seconds % percent pF pico Farad ps picoseconds VV o l t s [+] Feedback
Document Number: 38-07633 Rev. *H Page 14 of 15 Document History Page Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07633 REV. ECN NO. Orig. of Change Submission Date Description of Change ** 204243 RGL See ECN New data sheet *A 220043 RGL See ECN Minor Change: Corrected letter a ssignment in the ordering info for Pb free. *B 267832 RGL See ECN Added Field Programmable Devices and Functionality *C 291094 RGL See ECN Added t SKEW spec. and footnote *D 1821908 DPF/AESA See ECN Corrected FSSCLK-Low Volt age specification on page 7 for SSCLK5/6 to SSCLK1/2/3/4, as SSCLK5/6 output does not operate at low voltage. Deleted Tccj4 on page 8 for the same reason as above *E 2442066 KVM/AESA See ECN Updated template. Added Note “Not recommended for new designs.” Added part number CY25200KZXC_XXXW, CY25200KZXC_XXXWT, CY25200KFZXC in ordering information table. Changed package name to ZZ16. *F 2758387 KVM/AESA 09/01/2009 Extensive text edits Replaced Benefits column on page 1 with Description Revised Table 2 and Table 3 for clarity Revised the Modulation Frequency paragraph to align with actual software options and to delete mention of custom frequencies Corrected 3.3V I OL and IOH values, Filled in missing units in AC Electrical table Revised T SKEW footnote for clarity Removed specific PD# and OE pin nos. from parameters TSTP, TOE1 and TOE2 Standardized timing parameter names to upper case Corrected part numbers in Ordering Information Table Removed part number CY25200FZXCT Added part number CY25200KFZXCT Replaced CY3672 and CY3672-PRG with CY3672-USB *G 2897246 KVM 03/22/10 Removed inactive parts from Ordering Information table. Added note regarding possible configurations in Ordering Information section. Removed Note 6. Added Possible Configurations table. Updated Package Drawing and Dimensions. *H 3103982 BASH 07/12/2010 Added Ordering Code Definitions. Updated Package Drawing and Dimensions. Added Acronyms and Units of Measure. Minor edits and updated in new template. [+] Feedback
Document Number: 38-07633 Rev. *H Revised December 7, 2010 Page 15 of 15 All products and company names mentioned in this document may be the trademarks of their respective holders. CY25200 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subj ect to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to t he materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at www.cypress.com/sales. Products Automotive cypress.co m/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress. com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cyp ress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 [+] Feedback