PLS167-33

PLS167-33 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 19

Technical content

f Fino | COM’L Pa | PLS167-33, PLSCE167H-33 Advanced PLS168-33, PLSCE168H-33 Micro 24-Pin TTL/CMOS Programmable Logic Sequencers Devices DISTINCTIVE CHARACTERISTICS = Field-programmable replacement for ™ User-programmable pin for asynchronous Sequential control logic flip-flop Preset/Output Enable ™ Advanced Mealy state machine/sequencer = Automatic “Hold” state via S-R flip-flops architecture ™ Security bit hides proprietary designs from ™ Programmable AND/programmable OR array competitors for flexibility ™ Supported by PALASM® software and ™ Full drive: 24 mA lou, three-state outputs standard PLD programmers ™ Dedicated hardware features to enhance © Available In 24-pin plastic SKINNYDIP® and testability 28-pin PLCC packages — Diagnostic Mode access to buried state register ag igh Ipot — Register Preload and Power-up Preset of all Fabricated with high-performance bipolar and electrically erasable CMOS technology tlip-flops GENERAL DESCRIPTION The PLS167 and PLS168 are field-programmable re-__in a high-speed, EE CMOS process; they offer signifi- 13 placements for sequential logic. The devicesfunctionas cant power improvement (loc of 100 mA) over compet Mealy state machines with a registered output. The PLS _ing parts. utilizes the familiar AND/OR PLA logic structure to im- . - plement sum-ot-product equations. Both arrays are The PLS devices are fully supported by industry-stan- user-programmable to implementtransition terms caus- _ 9ard CAD tools, including the PALASM design software ing changes in he internal state register or output regis Package. Device programming is accomplished by us- ter. The PLS167/8-33 devices are fabricated in Ad- ng standard PLD programmers. vanced Micro Devices’ advanced oxide-isolated bipolar process. The PLSCE167/8H-37 devices are fabricated eee SSS BLOCK DIAGRAM lo= hha (167) lo= ns (168) Y WM Mw YM Pi fable AND A: Programmable OR A\\ (48x Bs, 167) (48x 39, 148) pt ft tf Pea § Hea 8 HeAos | A A A wo td OE $2 $7 Qo - Qs (167) Po ~ Pr (167) Qo -Qs (168) Po —Ps (168) 14081-0014 PALASM and SKNNYDIP aw rogetored vademar of Advarcod Mice Devices. Paticaiony 608) Rew A Ard ‘Th pat is covered by varus U.S. an ovegn paris ord by vanced Hao Ons sts Dat Janay 900 3-21

CuK 1° 24D) Veo CLK 1° 241 vec bQ2 2 2 231s Qs 22) le 4Q3 20h uQ4 2b bO4 ane bs 201 ho ks 201) be 19D hs hfe 191 ho hO7 BO he bQ7 18h; bfe 7D hs Qo] 8 70 poe QQ 16) POE as 16 {) Ps a, 10 15 {) P, Qf] 10 15[] P2 ef} 11 141) Po sf} 11 14D py Gnp [| 12 13 f] Qs nb [f 12 131] Po 14081-0024 14081-0034 PLCC PLCC x x essed 23.., s232$8.,. ee Woes We Woe Wn We ee Mommmm us e 251] to +s . 25{] te

5 Te 24] bo kOe 24f]

bQ7 2a] ty, 47 23f] tro ne [Js 22{] nc nc [Js za{] no

4 Qs aif] he b (s at) ns

b 10 20f] his Q [Fro 20f] POE Q [fis 191] POE a Qi 191] Ps 12.13 14 15 16 17_ 18 j2 13 14 45 16 17 18 as ee ge 9 os ge ne

662 S8ea 14081-0044, é a9 gece 14081-0054

CLK Outputstate register clock GND Ground ! inputs to AND array P Programmable output/state register POE Programmable asynchronous function pin; Gefault is active-high Preset (all registers

90 HIGH), programmed is active-low

ORDERING INFORMATION

Commercial Products (Bipolar Only) AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: a. Family Type b. Device Number ©. Speed 4. Operating Conditions @. Package Type f. Optional Processing PLS 167 -37 NS a Famuyrvpe ————] L_ {. OPTIONAL PROCESSING PLS« Programmable Logic Sequencer Blank = Standard Processing b. DEVICE NUMBER 167 = 14x 48x6 PLS © RACKAGE TYPE NS = 24-Pin 300-mil Plastic 168 = 12x 48x 8 PLS SKINNYDIP (PD3024) ©. SPEED FN = 24-Pin Plastic Leaded we Chip Carrier (PL.028) S7 = 37 Miz tax JS = 24-Pin 300-mil Ceramic SKINNYDIP (CD 3024) 4. OPERATING CONDITIONS € = Commercial (0°C to +75°C) Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Valid Combinations Consult the local AMD sales office to confirm Piste7ar availability of specific valid combinations, to CNS, CFN, CJS check on newly released combinations, and to PLst68.a7 CEN, obtain additional data on AMD's standard military grade products. Note: Marked with MMI logo. SSS PLS167/168 3-23

Commercial Products (CMOS Only) AMD programmable logic products for commercial applications are available with soverat ‘ordering options. The order number {valid Pariser {s formed by a combination of: ‘8. Family Type b. Techriogy ©. Device Number d. Power @. Speed f. Package Type 9. Operating Conditions h. Optional Processing PLS CE 167 H -33 Pc . Fawtytyee ———_] L h. OPTIONAL PROCESSING PLS = Programmable Logic Sequencer Blank = Standard Processing b. TECHNOLOGY CE = CMOS Electrically Erasable 9. OPERATING CONDITIONS C = Commercial (0°C to +75°C) b. DEVICE NUMBER 167 = 14x48 x6 PLS 168 = 12x 48x8 PLS d. POWER H = Half Powor (100 mA toc) ©. SPEED “33 = 33 MHz fax 1. PACKAGE TYPE P = 24-Pin 300-mil Plastic SKINNYDIP (PD3024) 4) = 28-Pin Plastic Leaded Chip Carrier (PL 028) D = 24-Pin 300-mil Ceramic SKINNYDIP (CD3024) Valld Combinations The Valid Combinations table lists configurations planned obo cppoced est ontguations Consult the local AMD sales office to confirm a eee availablity of specific valid combinations te [ Puscetesnss | check on newly releasad combinations, and to PLSCE168H-33. obtain additional data on AMD's standard miftary grade products. Note: Marked with AMD logo. 3-24 PLS167/168

State Machine implementation Output Enable State machines contain conditional input logic, state _The Preset input can be converted to a three-state Out- memory and output generation logic. The PLS device is___put Enable function by an architecture bit. Expansion to built around a programmable AND/OR logic array which larger control functions can be accommodated by con- rogt serves as both conditional input and output generation —_necting several PLS devices to a control bus and selec- logic. Forty-eight product ortransition terms arefoundin __tively enabling them to each handle a segment of the the AND array. The AND array is driven from several control algorithm. This user-programmable option is sources: there are twelve tofourteen external inputs, six _ specified as an auxiliary equation in the design file or op- internal feedback signals fromthe buriedstate registers, _ tionally by use of a keyword. ig n ly {wototourprogammableregisters, andthe complement tyicat Operation term. The details of device operation may be illustrated by the The OR array drivesthe output registers, programmable simpie state transition indicated. The state register in- registers, buried state registers, andthe complementar- —_ially contains 010 and will become 001 alter the next ray term. The PLS device offers six to eightoutputregis- ioc. For this to occur, state bit O must be set, state bit 1 tors and six buried state registers. must be reset and state bit 2 must hold its value. The Architectural Detail transition term fragments listed produce this result. The renlectu < So and R; product terms detect the bit pattern for the [ Part Number [Pins] inputs | Fiip-Fiops | Outputs | current state (010) and produce a logic one. All other [pusie7 | 2aaf 14 | 12 | 6 | terms evaluate to a zero, producing the transition to [rsies [2a 2 [a a | state 001 State and Output Registers 2 st so LOGIC FUNCTION The state and output registers are both implemented PRESENT) with edge-triggered S-R type flipflops. If neither input is [ofsfo] PSrate (=) NEXT 13 active, the flip-flop will retain its contents when clocked. STATE This free “hold” state saves product terms. The registers oon Gre) may change only on the LOW-to-HIGH transition of the Ss clock pulse. There are four output registers, two outpul/ STATE REGISTER So = 82°s1°S0+... buried registers and six buried state registers on the SET 80 Ro=0 PLS167 device, and two additional output/buried regis- neest 3 s ters on the PLS168 device. Ho Oe malas Logic implementation All transition terms can include True, False, or Don't S20 Care states of the controlling variables. The OR array Ra=0 12805-004A merges one or more product terms to generate the de- Typical State Transition sired user logic functions for the output and next-state | registers. This sharing of OR-terms minimizesthe over- Security Bit alllogic required to implement complicated control{unc- security bitis provided on the PLS167/8 asa deterrent tions. to unauthorized copying of the array configuration pat- terns. Once programmed, this bit defeats readback of Complement Array Term the programmed pattern by a device programmer, Aninternal variable (C) known as the complement array _ securing proprietary designs from competitors. stale. This stot reduces the nonber at cicdkt ware, Onthe PLSCE167/8, programming and veriication are . Thi ; fequled for acondtienal“ese" anction’ The, comple. also defeated by the securiy bit The bit can only be ment array can also be used for illegal state recovery erased in soni wih the array during a erase or and designing modulo counters. enabilly. 'y Dit also prevents preloat obs- Initialization - ; Programming and Erasing Starting the state machine in a known state is facilitated The PLS167/8 can be programmed on standard logic by power-up preset circuitry which unconditionally loads Programmers. Approved programmers are listed in the “1” into each tlip-tlop during power-up or by using the Programmer Reference Guide. asynchronous Preset function. Synchronous transitions ne ‘i The PLSCE167/8 may be erased to reset a previously tothe initial state can be made by having an input be an co rrigured device back t0 its virgin state. Erasure is ORtermonallthe state register Sinputs, and ANDingits —_iromatically performedby the programming hardware complement with allot the R logic terms. Whenever this No special erase operation is tequred input is active the machine will synchronously change to : the state with all outputs high. A PLS167/168 3-25

DIP (PLCC) Pinout te 2 ot: — ~ ci aa RE RBEEAGEEE ER GEE Tice ne ft eee rn 0 4 pe = Sy fee SaCEESS era case rmean Teese saeenea ppg cfasea ova atoll eed tees msteeefi ames esses raeiii oo oe aaiimiiiin ull ot ee - i imi i a Ft Pee ne BB ini (ilidiiiini Hamagimaineeiit a i] Wet meee pein HFS ee emeabt - SSneS meas Bane Co = t. i Ha ¢ rar a Besar a SS seeeresesee =a —|

2 EES SH RSS Sete

ss Roo te 4 Seeunu wees oeeees ease: Hl| 2s HEEn HiBITGHHaniBTaiE ! SO a ia TT | ia Hil: RES Hi ia eT eget Fe Hiv ae ei easiness = . D> Pan Har fetid Caer eti sete | nent qt a Coat HBB i | Ge em aes ete? | tht ot} Pott CB | | paar SSHEOm CA fadtnt aad ad toni saialtmbari Gites Le, Et tt Hy Ca Bs a area gd aed tovsHdpstigd tees ceastatoste teseenstaiiiae 7 Sia] Po RGkS See aeel Hee Bt ia) vm rH RHEE ee Fe oa rt To Pat B a Hitt aE reatd i tesesttteessestesstowiasvii ies “iE Eerste IB -td HE ee se a Notes: 1. Alldisconnected AND gato inputs float to a logic “." =ioo 2. Alldisconnected OR gate inputs float oa logic "0." 14081-0078 3-26 PLS167/168

: im =

4 Y ose

+ PAPoTA ro hot nee = He oo , BP tee a ae oe IP Hi Het HS | el. EI 2 aii simi as 2B ae eae ,

5 Einai= i nau mil seer sa

D aiices HERE (eee cuits rH es isi PEELE ee naae iil “Be Her, jimiiil iil 7 a Hae manne ld) | | Sri 4 oe HH | ° > eect | HEH iat SHESrH PHA | is Hill ) oa ca ri [| 179 cab ote oe sseeae Hues a SET aati SH in wy HH ee rt Hue staat rot [| bag He | | “fe eee iii | ‘f Ht | ca ae ” ae init ned 4 ile, i oo sii SH itl Bie} I dae EEE iia] ny alice Hie la. ss Hae iaunaes 09 ail alii Het Peed [s, “ FEE rt Ly ee ca a ey iim bbb He FH ay ain piteste oH nee HH = Hee ‘a aL een Ht ee i} os a i go TT ee 2: ° MY HT bie eae a rts 7 rt aa ot ‘ a dea = irate HE Le 8 Li [1 Ho a HE Se aa B 4 au | nee Brie et gies: o 2 rH faenae eal HL HHH oH Hy a ty tH ++ Poy aaa H LH ree 0 = He Himiti ere iS i HH HH rt rit Het Hite L| He HH a — oo 3 cee rH [| tS aa aa cn ee Hunt : aici * jc “1 He ronan 167/168 _ us oat oa piss ati seh S: nected OF Note: disco nected 1. Aero z as

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65°C to +150°C. Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied 55°C to +125°C Operating in Free Air 0°C to +75°C Supply Voltage with Respect Supply Vott a tage (Vcc) with 0 Ground BS Vios7o¥ Respect to Ground 44.75 V 10 +5.25V DC Input Voltage 05 V10 +5.5V DC Output or VO Pin Operating Ranges define those limits between which the func- Vonage 05 Vt0455V tionality of the device is guaranteed. DC Output Current +16 mA Stresses above those listed under Absolute Maximum Rat- ‘ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabii ‘ty. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL Operating ranges unless otherwise Specified Parameter Symbol Parameter Description Test Conditions Vou Output HIGH Voltage lon=-3.2MA Vin = Visor Vie 24 v Voc = Min. Vow Output LOW Vottage lo =24mMA Vw = Vm or Vie v Vec = Min, Vine Input HIGH Voltage Guaranteed input Logical HIGH v Voltage for ail Inputs (Note 1) Ve Input LOW Voltage Guaranteed Input Logical LOW v Voltage for all Inputs (Note 1) [| input HIGH Current Wni=24V.Voo=Max.(Noto2) — [ [20 | ua | |__| impatowcunert [v= 04, Veo = Mae (Note) [J -250 Tua] | [Maxima input Gren [vn=SSVvocmmax | | as | ua] Off-State Output Leakage | Vour = 2.7 V, Voc = Max., HA Current HIGH Van = Vic or Vi (Note 2) loa Off-State Output Leakage | Vour = 0.4 V, Voc = Max. pA Current LOW Viv = Vit or Vii (Note 2) Output Short-Circuit Vout = 0.5 V, Vec = Max. (Note 3) ~30 | -130 Current Supply Current Viv= 0 V, Outputs Open (lour = 0 mA)| Voc = Max. Notes: 1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included. 2. VO pin leakage is the worst case of ln and lozt (or Ins and lozu). 3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second, Vour = 0.5 V has been chosen to avoid test problems caused by tester ground degradation, 3-28 PLS167-33, PLS168-33 (Com’!)

CAPACITANCE (Note 1) Parameter Symbol | Parameter Description Test Conditions Typ. Ta= 425°C, pF Output Capacitance Vour = 2.0V f=1MHz [ 3 | Note: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected, Sa ee SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol | Parameter Description Setup Time trom input or Feedback to Clock | Without Complement Array | 17 | | ns | |__tsc__| Setup Time from input or Feedback to Clock | with Complement Array | 30, | ns | [ty [Hors Time re] Asynchronous Preset to Output [ [35 ns} |_twew _| Asynchronous Preset With [of [rs | Aeyrcronous Preset Reoovey Tine a) 3 [tT Cock wath [ow ao os [tw | a 0 . External Feedback | Without Complement | 1/(ts + tco) Maximum Array Frequency Array a eo Lee [tre [Fe Oupu Dade [ete Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at intial characterization and at any time the design is modified where frequency may be affected. PLS167-33, PLS168-33 (Com'l) 3-29

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65°C to +150°C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied 55°C to +125°C ‘Operating in Free Air 0°C to +75°C Supply Voltage with Respect Supply Vol A fage (Voc) with to Ground O05 VI047.0V Respect to Ground +4.75 Vio +5.25V DC Input Voltage ~0.5V10 +7.0V i Operating Ranges define those limits between which the func- vous or VO Pin ~05V1047.0V tionality of the device is guaranteed, Static Discharge Voltage 2001 V Latchup Current (Ta = 0°C to +75°C) 100 mA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- ‘mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL Operating ranges unless otherwise Specified Parameter Symbol Parameter Description Test Conditions Vow Output HIGH Voltage lon=-3.2mMA Viv = Vinor Vit 24 Vv Vec = Min, Vow Output LOW Voltage l= 24mA Vin = Vin or Vi. v Vee = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH Vv Voltage for ail Inputs (Note 1) Va. Input LOW Voltage Guaranteed Input Logical LOW v Voltage for all Inputs (Note 1) | Im | _InputHIGH Leakage Current] Vw 2525 V, Voc = Max. (Note 2) [| 10 [aa | |__| input LOW Leakage current | Vnr=0V, Voo~ Max: (Note 2) [ [10 [a | Off-State Output Leakage | Vour = 5.25 V, Voc = Max., 10 | pA Current HIGH Vin = Vit or Vin (Note 2) Off-State Output Leakage | Vour = 0V, Voc = Max A Current LOW Viv= Vit or Vii (Note 2) Isc Output Short-Circuit Vout = 0.5 V, Voc = Max. (Note 3) -30 | ~130 Current lec ‘Supply Current Viv= 0 V, Outputs Open (lour = 0 mA)! Voc = Max. Notes: 1. These are absolute values with respect tothe device ground and all overshoots due to system and tester noise are included. 2. VO pin leakage is the worst case of lk. and lozt (or lei and loz). 5. Not more than one output should be tested ata time. Duration ofthe short-circull test should not exceed one second, Vou = 0.5V has been chosen to avoid test problems caused by toster ground degradation." 3-30 PLSCE167H-33, PLSCE168H-33 (Com'l)

a SSSSSSSSSSSSsSSSseseeseseseSSSSSSSSSSSSSS CAPACITANCE (Note 1) Parameter ‘Symbol Parameter Description Test Conditions Typ. ‘a= 25°C, Output Capacitance Vour = 2.0 V f= 1MHz [es | pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SSeS SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol | Parameter Description Setup Time from Input or Feedback to Clock | Without Complement Array [a7 { [ns | | _tsc___| Setup Time from Input or Feedback to Clock | With Complement Array [30] | as | [oe [retin Co [ies [evace Ovo [P38 [oe] Clock to Feedback (Note 3) [| 0 [ns | | tw | Asynchronous Preset to Output | | 15 | ns | [trea ___ | Asynchronous Preset Recovery Time [es | | ns | | mls Ow Cd Od | | tm | HIGH [io] [ns | External Feedback Core : its + too) [33 | __[mux | mplemen Maximum Internal Feedback | Array Wits + tor) [a7 [|e | ‘requenc; fee)” [amar Feodtacr| Wer [ws tea) [23 Li Complement Internal Feedback | Array U{tsc+ tor) [2s [| [mx | |_ trae | OE to Output Enable || 2 [ns | L_ tre _| OE to Output Disable | [0 [as | Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fax internal. 4, These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. a SSSSSSSSSSSSSSSSssssSSSSseee PLSCE167H-133, PLSCE168H-33 (Com'l) 3-34

Feedback Feedback (with (without Complement ‘Complement Array) Array) ts Cy tsc Clock vr Clock Ms too tco Output Vr Output Vr 12905-006A 12905-007A Registered Output (without Complement Array) Registered Output (with Complement Array) cLK ts+tcr 1 " i I 's i Clock Vr I Locic REGISTER I ! 1 ! t 12149-0258 | i Clock to Feedback (fyax Internal) Botta See Path at Right 12015-0218 twH lapw Clock " Preset Vr tw 12015-0118 VWYVY Output Vr Clock Width "" XXXM tara Clock Vr OE 12905-009A, tr tex Asynchronous Preset SSM LUV Output LL Vo. + 058K 12905-0084 SE to Output Disable/Enable Notes: 1. Vret5V 2, Input pulse amplitude 0 V to 3.0 V. 3. Input rise and tall times 2-5 ns typical 3-32 PLS167/1168

KEY TO SWITCHING WAVEFORMS. WAVEFORM —_— INPUTS. OUTPUTS Mast bo Will be Steady Steady ‘Change Changing fromHtoL from toL Change Changing from Lo H from L to H YOXXXX Don't Care; Changing, Any Change State Permitted Unknown DEE BSE Apply Line is High- Impedance “Off” State SWITCHING TEST CIRCUIT } St Ry Output Test Point , I . = = 12350-0198, [ specmeaon | ss | ce [om | me | measured ouput vate _| ZH: Open 15V ZL: Closed HZ: Open SpF H3Z:Vor-0.5V LZ: Closed LZ: Vo. +0.5V PLS167/168 3-33

The PLSCE167/8 is manufactured using AMD's ad- parts. As a resull, the device can be erased and vanced electrically erasable process. This technology _ reprogrammed —a feature which allows 100% testing at uses an EE cell to replace the fuse link used in bipolar the factory. Endurance Characteristics Years Max. Storage Temperature Min. Pattern Data Retention Time Years Max. Operating ‘Temperature (125°C) N Min, Reprogramming Cycles 100 Cycles Normal Programming Conditions TT INPUT/OUTPUT EQUIVALENT SCHEMATICS CMOS Typical Input Typical Output Voc Vec Preload Observability Circuitry ~ Circuitry Program/Verit Circuitry ity 1 10205-0068, 10205-0128 BIPOLAR Typical input Typical Output Yoo Yoo 40 2NOM Output > = Program/ —_ Preload/ Program/Verity arity Observability Circuitry Sc06.0108 chesy — Creuty = 10205-0114 —.T,_ ese 3-34 PLS167/168

(CMOS Only) {he preioad function allows the register to be loaded 5. Apply either Vawp or Va to all outputs. Use Vie to from the output pins. This feature aids functional testing Preload a LOW in the flip-flop; use Vip to preload a of sequential designs by allowing direct setting of output HIGH in the flop-flop. states. The procedure for preloading follows. 6. Pulse MCLK from Vit» to Vue to Vite. 1. Set OE to Viipto disable outputs. 7. Remove preload data from outputs. 2. With Mode pins LOW raise Vep to Vis. 8. Lower Vpp to Vip. 3. Use Mode pins to select Preload Output or Preload State. 9. Lower OE to Vip to enable the outputs. 4. Raise CLK to Vip. 10. Verify Vou/Von at all outputs. To verity state registers, use the observability mode. Parameter Symbot Parameter Description [Vis | Super-level input vokage [7925] 135 [v.78] v | [Ver | “Low evel input votage [0 [0 [os [vq Figh-evel input vohage [4050 Weest | VJ Oe dvidt Vii Rise Time Slew Rate | 10 [100 TVs | [avvat | Vins Fal Time Stew Rate [203.0 Pris] Mode Select Pins fo Tata To] [Li [aya To] x MP Vir TP Vin to Vpp \\ Ver Mode © Vor Vie to Ver CLK a ~~~ Vip ® foe Ver fon

0 SS on

E ° Oe eaten MCLK Vue 14081-0094 Output Register Preload Waveform 3-36 PLS167/168

(Bipolar Only) The observabitity function allows the state register to be 1. Apply Vi to pin 20. sent to the output pins. This feature aids functional test- . ing of sequential designs by allowing direct observation 2. Observe So-Ss on pins Qo-Qs, Po-Ps (167) or of the buried state register. The procedure for obser- Qz-Qs, Po-Ps (168). vability follows Parameter | Parameter Symbol_| Description per-levelinputvotage | 115 | 12 [125 [Vv | [toss [tay time Teo ts = Vy Pin 20 ‘osu var —----—— V Outputs on Vou 14081-0108 Observability Waveforms 3 a PLS167/168 3-37

OBSERVABILITY . {CMOS Only) The observabilty function allows the state registertobe 2. With Mode pins LOW raise Ver to Vin. Sent to the output pins. This feature aids functional test- , ing of sequential designs by allowing direct observation 3. Use Mode pins to select Observability. Of the buried state register. The procedure for obser g Lower OE to Vip to enable the state data to the vability follows. outputs. 1. Set OE to Vie o disable outputs. 5. Lower Vpp to Vip. Mode Select Pins | MDs [ MD: T MD2 [MDs | ——=— Vi Veep Vip Mode ° Vw Pre i Var to Ver OE Vip to ve

2 K ston XI

The power-up preset feature ensures that all flip-flops 1. The Vcc rise must be monotonic. will be preset to HIGH after the device has been pow- . ered up. This feature is valuable in simplifying state ma- 2: Following preset, the clock input must not be driven chine initialization. A timing diagram and parameter ta- from LOW to HIGH until all applicable input and feed- ble are shown below. Due to the synchronous operation back setup times are met. of the power-up preset and the wide range of ways Vcc can rise to its steady state, two conditions are required to ensure a valid power-up preset. These conditions are: | tee | Power-up Preset Time | i000 ns | [ts | __Input or Feedback Setup Time See Switching [tm | Clock Width LOW Characteristics nv Voc Power tee Output : EX Clock tm 12905-0134 Power-Up Preset Waveform PLS167/168 3-39

(Bipotar Only) The preload function allows the register to be loaded 5. Pulse pin 21 or pin 8/7 from Vip to Vie and back to trom the output pins, This feature aids functional! testing Vup. Pin 21 will preload output registers while pin of sequential designs by allowing direct setting of output 8/7(167/168) will preload buried state registers. 6. Remove ViwVine from output pins. 1. Raise Voc to 5.0V + 0.5 V. 7 pins by lowering PTE pin to Vi 2. Raise pin 19 to View 8 pin 1910 V ” 3. Disable output pins by raising P/OE pinto Vee. : a 4. Apply Vise/Vap as desired to all output pins. Parameter [Symon | roreeosocpson | tm | | | ne | _ Vir Low-levelinputvotage Tt os | Vue | Highrlevelinput voltage 2 50 55 TV | {to | Delaytime as [_dvedt | Visi Rise Time SlewRate 0 to 100 | ps | [ove | VaiFallTimeSiewRate TT 20 [3.0 [vas] PLS167 PLS168 [Priced Onin | Pulse | Pretedeafogiter | [ Prooodbeu | Fuse | Protededfogicwr | [CW [Qe-Os,PoPy P| rt Pepsf [| Do-Os Pinas [Ge Os, PoPr | [De Dy | Pinet | GOs. Po Ps | [De-ds ping [Sess LX Oey Trin? | sess] Pin 19 Vup PRE vur nd Ver [For Vin Pin 21 or 87 Vee 14081-008A_ Output Register Preload Wavelorm PLS167/168 3-35 @™ 9004697 0653005 800 mm