PLL102-108XI

PLL102-108 PLL | Alldatasheet

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Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 1

FEATURES

PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. Distributes one clock Input to one bank of ten differential outputs. Track spread spectrum clocking for EMI reduction. Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. Four independent programmable DDR skew chan- nels from –0.3ns to +0.4ns with step size ±100ps. Support 2-wire I2C serial bus interface. 2.5V Operating Voltage. Available in 48-Pin 300mil SSOP. DESCRIPTIONS The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVdd to ground. PIN CONFIGURATION BLOCK DIAGRAM PLL102-108 CLKT4 CLKT3 CLKC3 GND AGND AVDD VDD N/C SCLK VDD CLKC2 GND GND CLKT1 VDD CLKT0 CLKC0 GND GND CLKC4 VDD CLKT2 GND GND CLKC7 CLKT7 VDD SDATA N/C FB_INT VDD FB_OUTT N/C GND CLKC5 CLKT5 VDD CLKT6 CLKC6 GND VDD CLKC8 CLKT8 CLKC9 GND CLK_INT CLKC1 CLKT9 CLK_INT FB_INT Control Logic FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT6 CLKC6 AV DD AVDD -600~+800ps ±200ps step -300~+400ps ±100ps step -300~+400ps ±100ps step -300~+400ps ±100ps step -300~+400ps ±100ps step (0~2.5ns) +170ps step PLL Programmable Delay Channel Programmable Skew Channel

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 2 PIN DESCRIPTIONS Name Number Type

Description

4,11,15,21,28,34, 38,45 P 2.5V power supply. GND 1,7,8,18,24, 25,31,41,42,48 P Ground AVDD P Analog power supply (2.5V). AGND P Analog ground. CLKT(0:9) 3,5,10,20,22,46, 44,39,29,27 I “True” clocks of differential pair outputs. CLKC(0:9) 2,6,9,19,23,47, 43,40,30,26 I “Complementary” clocks of differential pair outputs. CLK_INT I Single-ended 3.3V tolerant input. N/C 14,32,36 Not connected. FB_OUTT O “True” feedback output. Dedicated for external feedback. It switches at the same frequency as the CLK_INT. FB_INT I “True” feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. SDATA B SCLK I Serial data input for serial interface port. Functionality INPUTS OUTPUTS AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT PLL State 2.5V (Nom) L H L H L On 2.5V (Nom) H L H L H On GND L H L H L Bypass/Off GND H L H L H Bypass/Off

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 3 I2C BUS CONFIGURATION SETTING Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Slave Re- ceiver/Transmitter Provides both slave write and readback functionality Data Transfer Rate Standard mode at 100kbits/s Data Protocol This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will termi- nate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD4) or a read condition (0xD5). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTE 0: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default 39,40 CLKT7, CLKC7 (1= active, 0=inactive) Bit 6 43,44 CLKT6, CLKC6 (1= active, 0=inactive) Bit 5 46,47 CLKT5, CLKC5 (1= active, 0=inactive) Bit 4 22,23 CLKT4, CLKC4 (1= active, 0=inactive) Bit 3 19,20 CLKT3, CLKC3 (1= active, 0=inactive) Bit 2 9,10 CLKT2, CLKC2 (1= active, 0=inactive) Bit 1 5,6 CLKT1, CLKC1 (1= active, 0=inactive) Bit 0 2,3 CLKT0, CLKC0 (1= active, 0=inactive)

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 4 TABLE 1: Output Signals SKEW Programming Summary: Bit<2:0> DDR Skew Setting (±±100ps/step) FBOUT Skew Setting (±±200ps/step) 111 +400ps +800ps 110 +300ps +600ps 101 +200ps +400ps 100 +100ps +200ps 011 Default Default 010 -100ps -200ps 001 -200ps -400ps 000 -300ps Setting applies to the following outputs: 1. DDRA: CLK0, CLK1, CLK5 2. DDRB: CLK7, CLK8, CLK9 3. DDRC: CLK2, CLK3, CLK4 4. DDRD: CLK6 -600ps Setting applies to the following out- puts: 1. FB_OUTT 2. BYTE 1: SKEW Register (1=Enable, 0=Disable) Bit Name Default 26,27 CLKT9, CLKC9 (1= active, 0=inactive) Bit 6 29,30 CLKT8, CLKC8 (1= active, 0=inactive) Bit 5 Bit <2> Bit 4 Bit <1> Bit 3 Skew DDRA Bit <0> These three bits will adjust timing of DDRA signals (CLK0, CLK1, CLK5) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1) Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 Skew DDRB Bit <0> These three bits will adjust timing of DDRB signals (CLK7, CLK8, CLK9) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1) 3. BYTE 2: SKEW Register (1=Enable, 0=Disable) Bit Name Default 1= disable, 0= enable Bit 6 FBOUT-SKEWEN 1= disable, 0= enable Bit 5 Bit <2> Bit 4 Bit <1> Bit 3 Skew DDRC Bit <0> These three bits will adjust timing of DDRC signals (CLK2, CLK3, CLK4) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1) Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 Skew DDRD Bit <0> These three bits will adjust timing of DDRD signals (CLK6) either positive or negative delay up to +400ps or –300ps with ±100ps per step. (see Table 1)

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 5 4. BYTE 3: Outputs Register (1=Enable, 0=Disable) Bit Name Default Bit <2> Bit 5 Bit <1> Bit 4 Skew FBOUT Bit <0> These three bits will adjust timing of FBOUTT signal either positive or negative delay up to +800ps or –600ps with ±200ps per step. (see Table 1) Bit 3 Bit <3> Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 Delay CLKINT Bit <0> These four bits will program the propagation delay from CLK_INT to the input of PLL within the range between 0ps and 2.5ns with 170ps step size. (see Table 2) TABLE 2: CLK_INT Delay Programming Summary: Bit<3:0> CLK_INT to CLK Delay 1111 +2,550 ps 1110 +2,380 ps 1101 +2,210 ps 1100 +2,040 ps 1011 +1,870 ps 1010 +1,700 ps 1001 +1,530 ps 1000 +1,360 ps 0111 +1,190 ps 0110 +1,020 ps 0101 +850 ps 0100 +680 ps 0011 +510 ps 0010 +340 ps 0001 +170 ps 0000 Default

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 6 TABLE 3: Output Drive Strength Programming Summary: Bit<2:0> Programming Setting 111 +40% 110 +30% 101 +20% 100 +10% 011 Default 010 -10% 001 -20% 000 -30% Setting applies to the following outputs 1. DDRA (CLK0, CLK1, CLK5) 2. DDRB (CLK7, CLK8, CLK9) 3. DDRC (CLK2, CLK3, CLK4) 4. DDRD (CLK6) 5. FBOUT 5. Byte 4: Buffer Drive Strength Control Register Bit Name Default Reserved. Bit 6 Reserved. Bit 5 Bit <2> Bit 4 Bit <1> Bit 3 DDRA Strength Bit <0> These three bits will program drive strength for CLK0, CLK1 and CLK5 output clocks (see Table 3). Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 DDRB Strength Bit <0> These three bits will program drive strength for CLK7, CLK8 and CLK9 output clocks (see Table 3). 6. Byte 5: Buffer Drive Strength Control Register Bit Name Default Reserved. Bit 6 Reserved. Bit 5 Bit <2> Bit 4 Bit <1> Bit 3 DDRC Strength Bit <0> These three bits will program drive strength for CLK2, CLK3 and CLK4 output clocks (see Table 3). Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 DDRD Strength Bit <0> These three bits will program drive strength for CLK6 output clock (see Table 3).

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 7 7. Byte 6: Buffer Drive Strength Control Register Bit Name Default Reserved. Bit 6 Reserved. Bit 5 Reserved. Bit 4 Reserved. Bit 3 Reserved. Bit 2 Bit <2> Bit 1 Bit <1> Bit 0 FBOUT Strength Bit <0> These three bits will program drive strength for FBOUTT output clock (see Table 3).

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 8 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage Range VCC -0.5 3.6 V Input Voltage Range VI -0.5 VCC+0.5 V Output Voltage Range VO -0.5 VCC+0.5 V Storage Temperature TS -65 150 Maximum power dissipation at TA = 550C in still air PW 0.7 W Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con- ditions above the operational limits noted in this specification is not implied. 2. Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IDD2.5 CL = 0 pF (Fclk=100Mhz) 250 mA Operating supply current IDDPD CL = 0 pF 100 uA High Impedance output current IOZ VDD=2.7V, VOUT=VDD or GND ±10 uA Input clamp voltage VIK Iin = -18mA -1.2 V Input Capacitance CIN VI = VDD or GND pF Output Capacitance COUT VO = VDD or GND pF VDD = Min to Max, IOH = -1mA VDD-0.1 V High level output voltage VOH VDD = 2.3V, IOH = -12mA 1.7 V VDD = Min to Max, IOL = 1mA 0.1 V Low level output voltage VOL VDD = 2.3V, IOL = 12mA 0.6 V Output differential-pair crossing voltage VOC (VDD/2)- 0.2 (VDD/ 2)+0.2 V

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 9 3. Recommended Operating Conditions PARAMETERS SYMBOL MIN. TYP. MAX. UNITS Output supply voltage VCC 2.3 2.5 2.7 V Analog Supply voltage ACC 2.3 2.5 2.7 V High level input voltage VIH 0.7 x VCC V Low level input voltage VIL 0.3 x VCC V Operating free-air temperature TA 4. Timing requirements SYMBOL PARAMETERS MIN. MAX. UNITS FCLK Input clock frequency 266 MHz DIN Input clock duty cycle TS Stabilization time after power up 0.1 ms 5. Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Low to high level propagation delay time TPLH CLK_INT to any output High to low level propagation delay time TPHL CLK_INT to any output ns 66MHz 120 Jitter (peak to peak) Tp-p 100/133/200/266MHz ps 66MHz 110 Jitter (cycle to cycle) Tcyc-cyc 100/133/200/266MHz ps Phase error t(phase error) -150 150 Output to output skew Toskew 100 Pulse skew Tpskew All differential input and output terminals are terminated with 120Ω/16pF 100 ps 66MHz to 100MHz 49.5 50.5 Duty Cycle DT 101MHz to 266MHz Rise time, Fall time tr, tf Load = 120Ω/16pF 650 800 950 ps

Programmable DDR Zero Delay Clock Driver 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/29/02 Page 10

PACKAGE INFORMATION

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-108 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP 0.008 - 0.016 (0.203 - 0.406) 0.620 - 0.630 (15.75 - 16.00) (0.254 - 0.406) 45 0 0.010 - 0.016 0.050 (1.27) MIN 30-60 0.015 (0.381) 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) 0.025 0.635 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.595 0.008 - 0.0135 0.203 - 0.343 48PIN SSOP