P66X-XXQC

PL660 PLL | Alldatasheet

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Technical content

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 1

DESCRIPTION

PhaseLink’s Analog Frequency Multipliers TM (AFMs) are the industry’s first “Balanced Oscillator” utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without using a phase-locked loop (PLL), in CMOS technology. PhaseLink’s patent pending PL66x family of AFM products can achieve up to 800 MHz differential PECL, LVDS, or single-ended CMOS output with little jitter or phase noise deterioration. PL66x-xx family of products utilize a low-power CMOS technology and are housed in GREEN / RoHS compliant 16-pin TSSOP and 3x3 QFN packages.

FEATURES

• Non-PLL frequency multiplication
• Input frequency from 30-200 MHz
• Output frequency from 60-800 MHz
• Low phase noise and jitter (equivalent to fundamental at the output frequency)
• Ultra-low jitter o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz) o RMS period jitter < 2.5 ps typ.
• Low phase noise o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz
• Low input frequency eliminates the need for expensive crystals
• Differential PECL/LVDS, or single-ended CMOS output
• Single 2.5V or 3.3V +/- 10% power supply
• Optional industrial temperature range (-40 °C to +85 °C)
• Available in 16-pin GREEN /RoHS compliant TSSOP, and 16-pin 3x3 QFN packages. Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3 rd overtone crystal)

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 2 O s c illa to r A m p lifie r O E Q Q B A R F r e q u e n c y X 2 X IN X O U T L 2 X F r e q u e n c y X 4 L 4 X O n ly r e q u ir e d in x 4 d e s ig n s R Figure 2: Block Diagram of AFM XO Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e. low jitter). Figure 3: Period Jitter Histogram at 212.5MHz Figure 4: Spectrum Analysis at 212.5MHz Analog Frequency Multiplier (2x), Analog Frequency Multiplier (2x), with 106.25 MHz crystal wit h sub-harmonics below –69 dBc OE LOGIC SELECTION OUTPUT OESEL OE Output State 0 (Default) Enabled 0 (Default) 1 Tri-state

0 Tri-state PECL

1 1 (Default) Enabled

0 Tri-state 0 (Default) 1 (Default) Enabled

0 (Default) Enabled LVDS or CMOS 1 1 Tri-state OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 3 PRODUCT SELECTOR GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Phase Noise at Frequency Offset From Carrier (dBc/ Hz) Part Number Input Frequency Range (MHz) Analog Frequency Multiplication Factor Output Frequency Range (MHz) Output Type Carrier Freq. (MHz)

10 Hz 100

PL660-08 30 - 80 4 120 - 320 PECL 155.52 -72 -100 -125 -132 -142 -147 -149 PL660-09 30 - 80 4 120 - 320 LVDS 155.52 -72 -100 - 125 -132 -142 -147 -149 PL663-07 30 - 80 2 60 - 160 CMOS 156.25 -75 -105 -130 -140 -145 -150 -150 PL663-08 30 - 80 2 60 - 160 PECL 156.25 -75 -105 -1 30 -140 -145 -150 -150 PL663-09 30 - 80 2 60 - 160 LVDS 156.25 -75 -105 -130 -140 -145 -150 -150 PL663-17 75 - 140 2 150 - 280 CMOS 212.5 -70 -100 - 130 -140 -145 -148 -148 PL663-18 75 - 140 2 150 - 280 PECL 212.5 -70 -100 -130 -140 -145 -148 -148 PL663-19 75 - 140 2 150 - 280 LVDS 212.5 -70 -100 - 130 -140 -145 -148 -148 PL663-28 140 - 160 2 280 - 320 PECL 311.04 -60 -92 -122 -140 -142 -146 -146 PL663-29 140 - 160 2 280 - 320 LVDS 311.04 -60 -92 -122 -140 -142 -146 -148 FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMAN CE RMS Period Jitte r (ps) Peak to Peak Period Jitter (ps) RMS Accumulated (L.T.) Jitter (ps) Phase Jitter (12 KHz- 20MHz) (ps) Spectral Specifications / Sub-harmonic Content (dBc) Frequency (MHz) Part Number Output Freq. (MHz) Carrier Freq. MHz (Fc) -75% (Fc) -50% (Fc) -25% (Fc) +25% (Fc) +50% (Fc) +75% (Fc) PL660-08 155.52 3 5 21 30 5 0.25 155.52 -66 -61 -67 -70 PL660-09 155.52 3 5 21 30 5 0.25 155.52 -66 -61 -67 -70 PL663-07 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-08 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-09 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-17 212.50 2.5 4 18 20 4 0.19 212. 50 -70 -75 PL663-18 212.50 2.5 4 18 20 4 0.19 212.50 -70 -75 PL663-19 212.50 2.5 4 18 20 4 0.19 212. 50 -70 -75 PL663-28 311.04 2.5 4 18 20 4 0.16 311.04 -65 -70 PL663-29 311.04 2.5 4 18 20 4 0.16 311. 04 -65 -70 Note: Wavecrest data 10,000 hits. No Filtering was used in Jitter Calculations. Agilent E5500 was used for phase jitter me asurements. Spectral specifications were obtained usin g Agilent E7401A.

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 4 BOARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATI ONS BOARD LAYOUT CONSIDERATIONS To minimize parasitic effects and improve performance, do the following:

• Place the crystal as close as possible to the IC.
• Make the board traces that are connected to the crystal pins symmetrical. The board trace symmetry is very important, as it reduces the negative parasitic effects to produce clean frequency multiplication with low jitter. CRYSTAL SPECIFICATIONS CL (xtal) ESR(R E) C0 C0/C1 Part Number Crystal Resonator Frequency (F XIN ) Mode Typical Max. Max. Max. PL660-08 PL660-09 25~75MHz Fundamental or 3rd overtone 5 pF 30 Ω 4.5 pF N.A. PL663-07 PL663-08 PL663-09 30~80MHz Fundamental or 3rd overtone 5 pF 30 Ω 4.5 pF N.A. PL663-17 PL663-18 PL663-19 75~140MHz Fundamental or 3rd overtone 5 pF 60 Ω 4.0 pF N.A. PL663-28 PL663-29 140~200MHz Fundamental or 3rd overtone 5 pF 60 Ω 4.0 pF N.A. Note: Non-specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a c rystal frequency adjustment. Request detailed crystal specifications from Ph aseLink.

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 5 EXTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION The required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” sof tware. You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value. For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink’s board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure: Figure 5: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE PCB side - Cinternal = Based on AFM Device - LWB1 = 2 nH, ( 2 places), Stray inductance - Cpad = 2.0 pF, Bond pad and its ESD circuitry - C stray = 1.0 pF, Stray capacitance - C11 = 0.4 pF, The following amplifier stage - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if used

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 6

• There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
• LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23.
• Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used.
• Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
• For 4X AFMs, repeat the same procedure in the L4X worksheet.
• See the examples below. DETERMINING STRAY L’s AND C’s IN A LAYOUT Figure 6: Diagram Representation of PL660-08 Board Layout Let’s take the PL660-08 (4x XO) for example, as shown in Figure 6. This takes a crystal input range of 30 to 80 MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz).

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 7 120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL660-0x in the L2X worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4X at 120 MHz. Results: L2X = 180 nH, L4X = 82 nH . 320 MHz AFM tuning: Repeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz. Results: L2X = 24 nH, L4X = 10 nH . Proceed and assemble the test units. Measuring 120 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 29.8x2 or 59.6 MHz. Measuring 320 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 78.0 x 2 =

156 MHz

In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust the Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz. Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray) Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray) Internal Capacitor Selection by Device Device Number Cinternal (pF) 2X 4X PL660-0X 34.125 16.500 PL663-0X 46.500 PL663-1X 14.625 PL663-2X 14.625

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 8 EXTERNAL COMPONENT VALUES – 3 RD OVERTONE RESISTOR SELECTIONS (R3rd) This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest “E12” resistor values versus frequency. PL660-08/09 PL663-07/08/09 PL663-017/18/19 PL663-28 /29 Freq. (MHz) R3rd (Ω) E12 Pick KΩ Freq. (MHz) R3rd (Ω) E12 Pick KΩ Freq. (MHz) R3rd (Ω) E12 Pick KΩ Freq. (MHz) R3rd (Ω) E24 Pick KΩ 24 12,396 12 30 9,917 10 75 2,125 2.2 140.0 915 0.91 26 11,442 12 32 9,297 10 77.5 2,056 2.2 142.0 902 0.91 28 10,625 10 34 8,750 8.2 80 1,992 2.2 144.0 890 0.91 32 9,297 10 38 7,829 8.2 85 1,875 1.8 148.0 866 0.91 76 3,914 3.9 140 1,138 1.2 192.0 647 0.62 194.0 639 0.62 196.0 630 0.62 198.0 622 0.62 200.0 614 0.62

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 9 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V DD 4.6 V Input Voltage, DC V I GND-0.5 V DD +0.5 V Output Voltage, DC V O GND-0.5 V DD +0.5 V Storage Temperature TS -55 +150 °C Industrial Ambient Operating Temperature T A_I -40 +85 °C Commercial Ambient Operating Temperature T A_C 0 +70 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended pe riods may cause permanent damage to the device and affect product reliability. These condi tions represent a stress rating only, and functiona l operations of the device at these or any other conditions above the operational limits noted in th is specification is not implied. PECL ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) I DD Fout = 212.5 MHz 58 65 75 mA Operating Supply Voltage V DD 2.25 3.63 V Output Clock Duty Cycle @ V DD – 1.3V 45 50 55 % Short Circuit Current ±50 mA Output High Voltage V OH RL = 50 Ω to V DD – 2V V DD – 1.025 V Output Low Voltage V OL R L = 50 Ω to V DD – 2V V DD – 1.620 V Clock Rise Time t r @20/80% 0.25 0.45 ns Clock Fall Time t f @80/20% 0.25 0.45 ns PECL Transistion Time Waveform OUT OUT 20% 80% tR tF DUTY CYCLE 45 - 55% 55 - 45% OUT OUT 50 Ω 50 Ω PECL Levels Test Circuit VDD 2.0V

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 10 LVDS ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) I DD Fout = 212.5 MHz 55 60 mA Operating Supply Voltage V DD 2.25 3.63 V Output Clock Duty Cycle @ 1.25V 45 50 55 % Output Differential Voltage V OD 247 355 454 mV V DD Magnitude Change ∆ V OD -50 50 mV Output High Voltage V OH 1.4 1.6 V Output Low Voltage V OL 0.9 1.1 V Offset Voltage V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆ V OS RL = 100 Ω (see figure) 0 3 25 mV Power-off Leakage I OXD V out = V DD or GND V DD = 0V ±1 ±10 µA Output Short Circuit Current I OSD -5.7 -8 mA Differential Clock Rise Time t r 0.2 0.5 0.7 ns Differential Clock Fall Time t f RL = 100 Ω CL = 10 pF (see figure) 0.2 0.5 0.7 ns OUT VDIFF RL = 100 Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit OUT LVDS Transistion Time Waveform OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF OUT OUT VOD VOS 50 Ω 50 Ω LVDS Levels Test Circuit

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 11 CMOS ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded Outputs I DD At 100MHz, load=15pF 32 40 mA Operating Supply Voltage V DD 2.25 3.63 V Output High Voltage (LVTTL) V OH3.3 IOH = -8.5mA, 3.3V Supplies 2.4 V Output Low Voltage (LVTTL) V OL3.3 IOL = 8.5mA, 3.3V Supplies 0.4 V Output High Voltage (LVCMOS) V OHC3.3 IOH = -4mA, 3.3V Supplies V DD – 0.4 V Output High Voltage V OH2.5 I OH = 1mA, 2.5V Supplies V DD – 0.2 V Output Low Voltage V OL2.5 IOL = 1mA, 2.5V Supplies 0.2 V Output drive current I OSD V OL = 0.4V, V OH = 2.4V (per output) 8.5 mA Output Clock Rise/Fall Time T r/ Tf 10% ~ 90% VDD with 10 pF load 1.2 1.6 ns Output Clock Duty Cycle Measured @ 50% V DD 45 50 55 % Short Circuit Current IS ±50 mA

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 12 BOARD DESIGN AND LAYOUT CONSIDERATIONS L2X and L4X: Reduce the PCB trace inductance to a minimum by placing L2X and L4X as physically close to their respective pins as possible. Also be sure to bypass each V DD connection especially taking care to place a 0.01 uF bypass at the V DD side of L2X and L4X (see recommended layout). Crystal Connections: Be sure to keep the ground plane under the crystal connections continuous so that th e stray capacitace is consistent on both crystal connection s. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection p ins of the IC. If you chose to use a series capacitance a nd/or inductor to fine tune the crystal frequency, be sur e to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout), even if one of the cap acitors will be a 0.01 uF and the other is used to tune the frequency. To further maintain a symmetrical balan ce on a crystal that may have more internal Cstray on one p in or the other, place capacitor pads (Cbal) on each crys tal lead to ground (see recommended layout). R3rd is only required if a 3 rd overtone crystal is used. V DD and GND: Bypass VDDANA and VDDBUF with separate bypass capacitors and if a V DD plane is used, feed each bypass cap with its own via. Be sure to conne ct any ground pin including the bypass caps with short via connection to the ground plane. OESEL: J1 is recommended so the same PCB layout can be used for both OESEL settings. PL660 (4x AFM) TSSOP Layout PL663 (2x AFM) TSSOP Layout

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 13 PACKAGE PIN DESCRIPTION AND ASSIGNMENT

15 GNDOSC

Q OSCOFFSEL 16 PL663-XX Q GNDBUF OE XOUT GNDOSC Q 1 2 3 4 0 91 XIN GNDANA DNC OESEL GNDBUF VDDBUF QBAR L2X VDDOSC VDDANA OE XOUT GNDOSC Q XIN VDDOSC L4X VDDANA VDDBUF QBAR L2X VDDOSC OESEL 1 2 3 4 0 91

6 OSCOFF

2x AFM Package Pin Out 4x AFM Package Pin Out PIN ASSIGNMENTS Name Pin # Type Product Description DNC 2X Do Not Connect. OSCOFFSEL 1 I 4X Set to “0” (GND) to turn off the oscillator when ou tputs are disabled (OE). Default (no connect) is OSC always on. GNDOSC 2 P 2X & 4X GND connection for oscillator. DNC 3 I 2X & 4X Do Not Connect. XIN 4 I 2X & 4X Input from crystal oscillator circu itry. XOUT 5 O 2X & 4X Output from crystal oscillator cir cuitry. OE 6 I 2X & 4X Output Enable input. See “OE LOGIC S ELECTION TABLE”. DNC 2X Do Not Connect. L4X 7 I 4X External inductor connection. The inductor is recom mended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasiti c effects and to maintain inductor Q. This inductor is used with 4x AFMs. GNDANA 2X GND connection. VDDOSC 8 P 4X VDD connection for oscillator circuitry. VDDOSC sho uld be separately decoupled from other VDDs whenever possible. GNDBUF 9 P 2X & 4X GND connection. Q 10 O 2X & 4X PECL/LVDS/CMOS output. QBAR 11 O 2X & 4X Complementary PECL/LVDS output or in-phase CMOS. VDDBUF 12 P 2X & 4X VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. 13 2X OESEL 14 I 4X Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no connection is applied, value will be set to default through in ternal pull-down resistor. 14 2X VDDANA 13 P 4X VDD connection for analog circuitry.VDDANA should b e separately decoupled from other VDDs whenever possible. VDDOSC 15 P 2X & 4X VDD connection for oscillator. VDD should be separa tely decoupled from other VDDs whenever possible. L2X 16 I 2X & 4X External inductor connection. The inductor is recom mended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasiti c effects and to maintain inductor Q. Note: 663-xx devices are 2x multipliers, and 660-xx devices are 4x multipliers.

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 14

PACKAGE INFORMATION

16 PIN TSSOP

C L A E H D e B

16 PIN TSSOP ( mm )

Symbol Min. Max. A - 1.20 A1 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 4.50 H 6.40 BSC L 0.45 0.75 e 0.65 BSC

16 PIN 3x3 QFN

Analog Frequency Multiplier PL660 and PL663 XO Families 47745 Fremont Blvd., Fremont, California 94538 TE L (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 15

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. The information furnished by Phaselink is believed to be accurate a nd reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : PhaseLink’s products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the President of PhaseL ink Corporation. To order parts, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL66X-XX X X X X Order Number Marking Package Option PL 66X -XXOC P66X -XX OC TSSOP – Tube PL66X-XXOC-R P66X-XX OC TSSOP – Tape and Reel PL66X-XXOCL P66X-XX OC TSSOP (GREEN) – Tube PL66X-XXOCL-R P66X-XX OC TSSOP (GREEN) – Tape and Reel PL66X-XXQC P66X-XX QC QFN – Tube PL66X-XXQC-R P66X-XX QC QFN – Tape and Reel PL66X-XXQCL P66X-XX QC QFN (GREEN) – Tube PL66X-XXQCL-R P66X-XX QC QFN (GREEN) – Tape and Reel PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE O=TSSOP Q= QFN 3x3 NONE= NORMAL PACKAGE L= GREEN PACKAGE NONE= TUBE R= TAPE AND REEL