PLDC20RA10-20WMB

PLDC20RA10 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Advanced-user programmable macrocell  CMOS EPROM technology for reprogrammability  Up to 20 input terms  10 programmable I/O macrocells  Output macrocell programmable as combinatorial or asynchronous D-type registered output  Product-term control of register clock, reset and set and output enable  Register preload and power-up reset  Four data product terms per output macrocell  Fast — Commercial tPD = 15 ns tCO = 15 ns tSU = 7 ns — Military tPD = 20 ns tCO = 20 ns tSU = 10 ns  Low power — ICC max - 80 mA (Commercial) — ICC max = 85 mA (Military)  High reliability — Proven EPROM technology — >2001V input protection — 100% programming and functional testing  Windowed DIP, windowed LCC, DIP , LCC, PLCC avail- able Functional Description The Cypress PLDC20RA10 is a high-performance, sec- ond-generation programmable logic device employing a flexi- ble macrocell structure that allows any individual output to be configured independently as a combinatorial output or as a fully asynchronous D-type registered output. The Cypress PLDC20RA10 provides lower-power operation with superior speed performance than functionally equivalent bipolar devices through the use of high-performance 0.8-mi- cron CMOS manufacturing technology. The PLDC20RA10 is packaged in a 24 pin 300-mil molded DIP , a 300-mil windowed cerDIP, and a 28-lead square lead- less chip carrier, providing up to 20 inputs and 10 outputs. When the windowed device is exposed to UV light, the 20RA10 is erased and can then be reprogrammed. Logic BlockDiagram 98 7 65 432 110 15 16 17 18 19 20 21 22 23 24 I I II II I I 4444444 VCC 1112 13 14 IVSS OE I I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 4 4 4 4 4 4 4 4 44 MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL 9 8 7 6 5 4 321 0 PL RA10 –1

Document #: 38-03012 Rev. ** Page 2 of 14 Macrocell Architecture Figure 1 illustrates the architecture of the 20RA10 macrocell. The cell dedicates three product terms for fully asynchronous control of the register set, reset, and clock functions, as well as, one term for control of the output enable function. The output enable product term output is ANDed with the input from pin 13 to allow either product term or hardwired external control of the output or a combination of control from both sources. If product-term-only control is selected, it is automat- ically chosen for all outputs since, for this case, the external output enable pin must be tied LOW. The active polarity of each output may be programmed independently for each out- put cell and is subsequently fixed. Figure 2 illustrates the out- put enable options available. When an I/O cell is configured as an output, combinatorial-only capability may be selected by forcing the set and reset product term outputs to be HIGH under all input conditions. This is achieved by programming all input term programming cells for these two product terms. Figure 3 illustrates the available out- put configuration options. An additional four uncommitted product terms are provided in each output macrocell as resources for creation of user-de- fined logic functions. Programmable I/O Because any of the ten I/O pins may be selected as an input, the device input configuration programmed by the user may vary from a total of nine programmable plus ten dedicated in- puts (a total of nineteen inputs) and one output down to a ten-input, ten-output configuration with all ten programmable I/O cells configured as outputs. Each input pin available in a given configuration is available as an input to the four control product terms and four uncommitted product terms of each programmable I/O macrocell that has been configured as an output. An I/O cell is programmed as an input by tying the output en- able pin (pin 13) HIGH or by programming the output enable product term to provide a LOW, thereby disabling the output buffer, for all possible input combinations. When utilizing the I/O macrocell as an output, the input path functions as a feedback path allowing the output signal to be fed back as an input to the product term array. When the output cell is configured as a registered output, this feedback path may be used to feed back the current output state to the device inputs to provide current state control of the next output state as required for state machine implementation. Preload and Power-Up Reset Functional testability of programmed devices is enhanced by inclusion of register preload capability, which allows the state of each register to be set by loading each register from an external source prior to exercising the device. Testing of com- plex state machine designs is simplified by the ability to load an arbitrary state without cycling through long test vector se- quences to reach the desired state. Recovery from illegal states can be verified by loading illegal states and observing recovery. Preload of a particular register is accomplished by impressing the desired state on the register output pin and lowering the signal level on the preload control pin (pin1) to a logic LOW level. If the specified preload set-up, hold and pulse width minimums have been observed, the desired state is loaded into the register. To insure predictable system initializa- tion, all registers are preset to a logic LOW state upon pow- er-up, thereby setting the active LOW outputs to a logic HIGH. Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the “no connect” (NC) pins Selection Guide Generic Part Number tPD ns tSU ns tCO ns tCC ns Com ‘l Mil Com ’l Mil Com ’l Mil Com ’l Mil 20RA10-15 15 7 15 80 20RA10-20 20 20 10 10 20 20 80 85 20RA10-25 25 15 25 85 20RA10-35 35 20 35 85 Pin Configurations LCC Top View STD PLCC/HLCC JEDEC PLCC/HLCCTop View Top View 4 3 2 282726 12131415161718 I/O I/O I/O I/O I/O I/O 11 121314 1516 1718 4 3 2 2827 26 I/O I/O I/O I/O I/O I/O PLDC20RA10 PLDC20RA10 NC I V I/O I/O 8I/O I/O V I I SS V I/O I/O CC CC 8I/O I/O V I I SS 1 1 PL RA10 –2 RA10 –3R A 1 0 –4 I I I I I I OE NC NC NC 25 11 121314 1516 1718 4 3 2 2827 26 I/O I/O I/O I/O I/O I/O PLDC20RA10 I I V I/O I/O CC 8I/O I/O V SS I I NC NC OE I NC PL I I3I I NC I I NC OE NC NC NC PL CG7C324 [1]

Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10

Document #: 38-03012 Rev. ** Page 5 of 14 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Ambient Temperature with Supply Voltage to Ground Potential DC Voltage Applied to Outputs (per MIL-STD-883, Method 3015) Operating Range Range Ambient Temperature VCC Commercial 0°C to +75°C 5V ± 10% Military[2] –55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range[3] Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., VIN =V IH or VIL IOH = –3.2 mA Com ’l 2.4 V IOH = –2 mA Mil VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 8 mA 0.5 V VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[4] 2.0 V VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[4] 0.8 V IIX Input Leakage Current VSS ≤ VIN ≤ VCC , VCC = Max –10 +10 µA IOZ Output Leakage Current VCC = Max., VSS ≤ VOUT ≤ VCC –40 +40 µA ISC Output Short Circuit Current[5] VCC = Max., VOUT = 0.5V[6] –30 –90 mA ICC1 Standby Power Supply CurrentVCC = Max., VIN = GND Outputs Open Com ’l 75 mA Mil 80 mA ICC2 Power Supply Current at Frequency[5] VCC = Max., Outputs Disabled (In High Z State) Device Operating at fMAX Com ’l 80 mA Mil 85 mA Capacitance[5] Parameter Description Test Conditions Max. Unit C IN Input Capacitance VIN = 2.0 V @ f = 1 MHz 10 pF C OUT Output Capacitance VOUT = 2.0 V @ f = 1 MHz 10 pF Notes: 2. T A is the “instant on” case temperature. 3. See the last page of this specification for Group A subgroup testing information. 4. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 5. Tested initially and after any design or process changes that may affect these parameters. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V OUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

Document #: 38-03012 Rev. ** Page 6 of 14 AC Test Loads and Waveforms (Commercial) RA10 –14 RA10 –15 90% 10% 3.0V GND 90% 10% ALL INPUT PULSES OUTPUT 50 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) (b) <5 n s <5 ns OUTPUT R1 457Ω (470Ω MIL) 270Ω (319Ω Mil) 170Ω Equivalent to: TH É VENIN EQUIVALENT(Commercial) 1.86V=Vthc R1 457Ω (470Ω MIL) 270Ω (319Ω Mil) OUTPUT 190Ω Equivalent to: TH É VENIN EQUIVALENT(Military) 2.02V=VthcRA10 –16 RA10 –17 Parameter V th Output Waveform Measurement Level tPXZ(–) 1.5V V OH 0.5V V X 0.5VtPXZ(+) 2.6V V OL V X tPZX(+) V thc 0.5VtPZX(–) V thc V OL 0.5VV X V OH RA10 –18 RA10 –19 RA10 –20 RA10 –21 V X 0.5V V X RA10 –22 V OH 0.5VV OL V X 0.5VV X V OH RA10 –23 RA10 –24 0.5V V OL RA10 –25 V X tER(–) tER(+) tEA(+) tEA(–) 1.5V 2.6V V thc V thc (c)

Document #: 38-03012 Rev. ** Page 7 of 14 Switching Characteristics Over the Operating Range[3, 7, 8] Parameter Description Commercial Military Unit tPD Input or Feedback to Non-Registered Output 15 20 20 25 35 ns tEA Input to Output Enable 15 20 20 30 35 ns tER Input to Output Disable 15 20 20 30 35 ns tPZX Pin 13 to Output Enable 12 15 15 20 25 ns tPXZ Pin 13 to Output Disable 12 15 15 20 25 ns tCO Clock to Output 15 20 20 25 35 ns tSU Input or Feedback Set-Up Time 7 10 10 15 20 ns tH Hold Time 3 5 3 5 5 ns tP Clock Period (tSU + tCO) 22 30 30 40 55 ns tWH Clock Width HIGH[5] 10 13 12 18 25 ns tWL Clock Width LOW[5] 10 13 12 18 25 ns fMAX Maximum Frequency (1/tP)[5] tS Input of Asynchronous Set to Registered Output 15 20 20 25 40 ns tR Input of Asynchronous Reset to Registered Output 15 20 20 25 40 ns tARW Asynchronous Reset Width [5] 15 20 20 25 25 ns tASW Asynchronous S-Width[5] 15 20 20 25 25 ns tAR Asynchronous Set/ Reset Recovery Time 10 12 12 15 20 ns tWP Preload Pulse Width 15 15 15 15 15 ns tSUP Preload Set-Up Time 15 15 15 15 15 ns tHP Preload Hold Time 15 15 15 15 15 ns Notes: 7. Part (a) of AC Test Loads was used for all parameters except tEA , tER , tPZX and tPXZ , which use part (b). 8. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH - 0.5 V for an enabled HIGH output or VOL +0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.

Document #: 38-03012 Rev. ** Page 8 of 14 Switching Waveform CP RESET ASYNCHRONOUS ASYNCHRONOUS OUTPUTS (HIGHASSERTED) SET OUTPUT ENABLE INPUTPIN INPUTS,REGISTERED FEEDBACK tAR tPD tCO tWH tWL tSU tER tEA tP RA10 –26 tH Preload Switching Waveform Asynchronous Reset Asynchronous Set tEA tER tHPtSUP tWP RA10 –27 PIN 13 OUTPUT ENABLE REGISTER OUTPUTS PIN 1 PRELOAD CLOCK RA10 –28 tR tARW ASYNCHRONOUS RESET OUTPUT RA10 –29 tS tASW ASYNCHRONOUS SET OUTPUT

Document #: 38-03012 Rev. ** Page 9 of 14 Functional Logic Diagram

Document #: 38-03012 Rev. ** Page 10 of 14 MILITARY SPECIFICATIONS Group A Subgroup Testing

Ordering Information

(ns) tSU (ns) tCO (ns) Ordering Code Package Name Package Type Operating Range 80 15 7 15 PLDC20RA10-15JC J64 28-Lead Plastic Leaded Chip CarrierCommercial PLDC20RA10-15PC P13 24-Lead (300-Mil) Molded DIP CG7C324-A15JC J64 28-Lead Plastic Leaded Chip Carrier 20 10 20 PLDC20RA10-20PC P13 24-Lead (300-Mil) Molded DIP CG7C324-A20JC J64 28-Lead Plastic Leaded Chip Carrier 85 20 10 20 PLDC20RA10-20DMB D14 24-Lead (300-Mil) CerDIP Military PLDC20RA10-20WMB W14 24-Lead (300-Mil) Windowed CerDIP 25 15 25 PLDC20RA10-25DMB D14 24-Lead (300-Mil) CerDIP PLDC20RA10-25WMB W14 24-Lead (300-Mil) Windowed CerDIP 35 20 35 PLDC20RA10-35DMB D14 24-Lead (300-Mil) CerDIP PLDC20RA10-35WMB W14 24-Lead (300-Mil) Windowed CerDIP DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Switching Characteristics Parameter Subgroups tPD 9, 10, 11 tPZX 9, 10, 11 tCO 9, 10, 11 tSU 9, 10, 11 tH 9, 10, 11 DC Characteristics Parameter Subgroups

Document #: 38-03012 Rev. ** Page 11 of 14 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 28-Lead Plastic Leaded Chip CarrierJ64 28-Square Leadless ChipCarrierL64 MIL-STD-1835 C-4 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C-4

Document #: 38-03012 Rev. ** Page 12 of 14 Package Diagrams (continued) 28-Pin Windowed Leaded Chip CarrierH64

Document #: 38-03012 Rev. ** Page 13 of 14 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams (continued) 24-Lead (300-Mil) Molded DIPP13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D- 9 Config.A

Document #: 38-03012 Rev. Page 14 of 14 Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Document Number: 38-03012 REV. ECN NO. Issue Date Orig. of Change Description of Change 106294 04/24/01 SZV Change from Spec number: 38-00073 to 38-03012