PLDC20G10B CYPRESS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 14

Technical content

Features

  • Fast — Commercial: t PD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: t PD = 20 ns, tCO = 15 ns, tS = 15 ns
  • L o w p o w e r —I CC max.: 70 mA, commercial —I CC max.: 100 mA, military
  • Commercial and military temperature range
  • User-programmable output cells — Selectable for registered or combinatorial operation — Output polarity control — Output enable source selectable from pin 13 or product term
  • Generic architecture to replace standard logic functions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8
  • Eight product terms and one OE product term per output
  • CMOS EPROM technology for reprogrammability
  • Highly reliable — Uses proven EPROM technology — Fully AC and DC tested — Security feature prevents logic pattern duplication — ±10% power supply voltage and higher noise immunity Functional Description Cypress PLD devices are high-speed electrically program- mable logic devices. These devices utilize the sum-of-products (AND-OR) structure providing users the ability to program custom logic functions for unique requirements. In an unprogrammed state the AND gates are connected via EPROM cells to both the true and complement of every input. By selectively programming the EPROM cells, AND gates may be connected to either the true or complement or disconnected from both true and complement inputs. Note: 1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The difference is in the location of the “no connect” or NC pins. Logic Block Diagram Pin Configurations 98 7 65 432 110 15 16 17 18 19 20 21 22 23 24 PROGRAMMABLE ANDARRAY I I II II I I CP/I OUTPUT CELL OUTPUT CELL OUTPUT CELL OE OE OE8 OE OUTPUT CELL OE OUTPUT CELL OE OUTPUT CELL OE OUTPUT CELL OE OUTPUT CELL V CC 1112 13 14 IVSS I/OE OUTPUT CELL OUTPUT CELL I I/O 9 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 4 3 2 282726 12131415161718 I I I I I NC 11 121314 1516 1718 432 2 8 2 7 2 6 I I I I I I NC I I V I/O I/O 8I/O I/O V I I SS I I CP/I V I/O I/O CC CC 8I/O I/O V I I SS 1 1 CP/I NC I I/O 2 I/O 3 I/O4 I/O5 I/O 6 I/O 7 NC I/OE NC PLDC20G10 PLDC20G10B 11 121314 1516 1718 4 3 2 2827 26 NC I I I I NC I I CP/I V I/O I/O CC 8I/O I/O I I 1VSS I NC I I/OE I/O 2 I/O3 I/O 4 I/O5 I/O 6 I/O7 NC JEDEC PLCC Top View STD PLCC Top View LCC Top View I/O2 I/O3 I/O4 I/O5 I/O 6 I/O 7 NC NC I/OE PLDC20G10 PLDC20G10B CG7C323–A CG7C323B–ANC [1]

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 2 of 14 Functional Description Cypress PLDC20G10 uses an advanced 0.8-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent advantage of being able to program and erase each cell enhances the reliability and testability of the circuit. This reduces the burden on the customer to test and to handle rejects. A preload function allows the registered outputs to be preset to any pattern during testing. Preload is important for testing the functionality of the Cypress PLD device. 20G10 Functional Description The PLDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8. Thus, the PLDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin devices. It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP . It provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the 20G10 is erased and then can be reprogrammed. The programmable output cell provides the capability of defining the architecture of each output individually. Each of the 10 output cells may be configured with registered or combi- natorial outputs, active HIGH or active LOW outputs, and product term or Pin 13 generated output enables. Three archi- tecture bits determine the conf igurations as shown in the Configuration Table and in Figures 1 through 8. A total of eight different configurations are possible, with the two most common shown in Figure 3 and Figure 5. The default or unpro- grammed state is registered/active/LOW/Pin 11 OE. The entire programmable output cell is shown in the next section. The architecture bit ‘C1’ controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is fed back to the array. This allows the creation of control-state machines by pr oviding the next state. The register is clocked by the signal from Pin 1. The register is initialized on power up to Q output LOW and Q output HIGH. In both the combinatorial and re gistered configurations, the source of the output enable signal can be individually chosen with architecture bit ‘C2’. The OE signal may be generated within the array, or from the external OE (Pin 13). The Pin 13 allows direct control of the outputs, hence having faster enable/disable times. Each output cell can be configured for output polarity. The output can be either active HIGH or active LOW. This option is controlled by architecture bit ‘C0’. Along with this increase in functional density, the Cypress PLDC20G10 provides lower-power operation through the use of CMOS technology and increased testability with a register preload feature. Selection Guide ICC (mA) t PD (ns) t S (ns) t CO (ns) Generic Part Number Com/Ind Mil Com/Ind Mil Com/Ind Mil Com/Ind Mil 20G10B–15 70 15 12 10 20G10B–20 70 100 20 20 12 15 12 15 20G10B–25 100 25 18 15 20G10–25 55 25 15 15 20G10–30 80 30 20 20 20G10–35 55 35 30 25 20G10–40 80 40 35 25

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 5 of 14 Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Ambient Temperature with DC Voltage Applied to Outputs DC Programming Voltage (per MIL-STD-883, Method 8015) Operating Range Range Ambient Temperature V CC Commercial 0 °C to +75°C 5V ±10% Military[3] –55°C to +125°C 5V ±10% Industrial –40 °C to +85°C5 V ±10% Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[4] Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage V CC = Min., VIN = VIH or VIL IOH = –3.2 mA Com’l/Ind 2.4 V IOH = –2 mA Military VOL Output LOW Voltage V CC = Min., VIN = VIH or VIL IOL = 24 mA Com’l/Ind 0.5 V IOL = 12 mA Military VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs [5] 2.0 V VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs [5] 0.8 V IIX Input Leakage Current V SS ≤ VIN ≤ VCC –10 +10 µA ISC Output Short Circuit Current V CC = Max., VOUT = 0.5V[6, 7] –90 mA ICC Power Supply Current 0 ≤ VIN ≤ VCC VCC = Max., IOUT = 0 mA Unprogrammed Device Com’l/Ind–15, –20 70 mA Com’l/Ind–25, –35 55 mA Military–20, –25 100 mA Military–30, –40 80 mA I OZ Output Leakage Current V CC = Max., VSS ≤ VOUT ≤ VCC –100 100 µA Capacitance[7] Parameter Description Test Conditions Max. Unit CIN Input Capacitance T A = 25°C, f = 1 MHz 10 pF COUT Output Capacitance V IN = 2.0V, VCC = 5.0V 10 pF Notes: 3. TA is the “instant on” case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. These are absolute values with respect to device ground. A ll overshoots due to system or tester noise are included. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters.

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 6 of 14 AC Test Loads and Waveforms (Commercial) OUTPUT INCLUDING JIG AND SCOPE OUTPUT 50pF 2.08V=Vthc OUTPUT 2.13V=V thm (a) (b) OUTPUT INCLUDING JIG AND SCOPE 5p F R1 238 Ω (319ΩMIL) R1 238Ω (319ΩMIL) R2 170Ω (236ΩMIL) R2 170Ω (236ΩMIL) Equivalent to: THÉVENIN EQUIVALENT (Commercial) Equiva lent to: THÉVENIN EQUIVALENT (Military/Industrial) 99Ω 136Ω Switching Characteristics Over Operating Range[3, 8, 9] Parameter Description Commercial Unit B–15 B–20 –25 –35 tPD Input or Feedback to Non-Registered Output 15 20 25 35 ns tEA Input to Output Enable 15 20 25 35 ns tER Input to Output Disable 15 20 25 35 ns tPZX Pin 11 to Output Enable 12 15 20 25 ns tPXZ Pin 11 to Output Disable 12 15 20 25 ns tCO Clock to Output 10 12 15 25 ns tS Input or Feedback Set-up Time 12 12 15 30 ns tH Hold Time 0 0 0 0 ns tP [10] Clock Period 22 24 30 55 ns tWH Clock High Time 8 10 12 17 ns tWL Clock Low Time 8 10 12 17 ns fMAX [11] Maximum Frequency 45.4 41.6 33.3 18.1 MHz Switching Characteristics Over Operating Range [3, 8, 9] Parameter Description Military/Industrial Unit B–20 B–25 –30 –40 tPD Input or Feedback to Non-Registered Output 20 25 30 40 ns tEA Input to Output Enable 20 25 30 40 ns tER Input to Output Disable 20 25 30 40 ns tPZX Pin 11 to Output Enable 17 20 25 25 ns tPXZ Pin 11 to Output Disable 17 20 25 25 ns tCO Clock to Output 15 15 20 25 ns tS Input or Feedback Set-Up Time 15 18 20 35 ns tH Hold Time 0 0 0 0 ns Notes: 8. Part (a) of AC Test Loads and Waveforms used for all parameters except tER, tPZX, and tPXZ. Part (b) of AC Test Loads and Waveforms used for tER, tPZX, and tPXZ. 9. The parameters t ER and tPXZ are measured as the delay from the input disable logic threshold transition to V OH – 0.5V for an enabled HIGH output or VOL + 0.5V for an enabled LOW input. 10. tP, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tP = tS + tCO. The minimum guaranteed period for registered data path operation (no feedback) can be calculated as the greater of (tWH + tWL) or (tS + tH). 11. fMAX, minimum guaranteed operating frequency, is that guaranteed for state machine operation and is calculated from fMAX = 1/(tS + tCO). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of 1/(tWH + tWL) or 1/(tS + tH).

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 7 of 14 tP [10] Clock Period 30 33 40 60 ns tWH Clock High Time 12 14 16 22 ns tWL Clock Low Time 12 14 16 22 ns fMAX [11] Maximum Frequency 33.3 30.3 25.0 16.6 MHz Switching Characteristics Over Operating Range (continued)[3, 8, 9] Parameter Description Military/Industrial Unit B–20 B–25 –30 –40 Switching Waveform t EAtPD INPUTS I/O, tH REGISTERED FEEDBACK CP REGISTERED OUTPUTS COMBINATORIAL OUTPUTS tS tPXZ tER tCO tW tW OE tP tPZX

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 8 of 14 Functional Logic Diagram 16 20 24 28 32 36 40 OE 1284 OE

  • •• OE
  • •• OE
  • •• OE
  • •• OE
  • •• OE
  • •• OE
  • •• OE
  • •• OE
  • •• OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL OUTPUT CELL

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 9 of 14 MILITARY SPECIFICATIONS Group A Subgroup Testing

Ordering Information

(ns) tS (ns) tCO (ns) ICC (mA) Ordering Code Package Name Package Type Operating Range 15 12 10 70 PLDC20G10B–15PC P13 24-Lead (300-Mil) Molded DIP Commercial PLDC20G10B–15WC W14 24-Lead (300-Mil) Windowed CerDIP 20 15 15 100 PLDC20G10B–20DMB D14 24-Lead (300-Mil) CerDIP Military 25 15 15 55 PLDC20G10–25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PLDC20G10–25PC/PI P13 24-Lead (300-Mil) Molded DIP Commercial/ Industrial PLDC20G10–25WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial 30 20 20 80 PLDC20G10–30DMB D14 24-Lead (300-Mil) CerDIP Military PLDC20G10–30LMB L64 28-Square Leadless Chip Carrier PLDC20G10–30WMB W14 24-Lead (300-Mil) Windowed CerDIP 35 30 25 55 PLDC20G10–35JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PLDC20G10–35PC P13 24-Lead (300-Mil) Molded DIP DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Switching Characteristics Parameter Subgroups tPD 9, 10, 11 tPZX 9, 10, 11 tCO 9, 10, 11 tS 9, 10, 11 tH 9, 10, 11

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 10 of 14 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 51-80031-** 28-Lead Plastic Leaded Chip Carrier J64 51-85001-*A

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 11 of 14 Package Diagrams (continued) 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 51-80051-**

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 12 of 14 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 51-80077-**

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Package Diagrams (continued) 51-85013-*B 24-Lead (300-Mil) PDIP P13 51-80086-** 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A

USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document #: 38-03010 Rev. *A Page 14 of 14 Document History Page Document Title: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Document Number: 38-03010 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106292 04/25/01 SZV Change from Spec number: 38-00019 to 38-03010 *A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”