PL580-69OC

PL580-68 PLL | Alldatasheet

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Technical content

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1

FEATURES

Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies. Low phase noise output (@ 1MHz frequency offset -140dBc/Hz for 320.0MHz, -131dBC/Hz for 622.08MHz 20MHz-40MHz crystal input. 320MHz-640MHz output. Available in PECL, or LVDS outputs. No external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages.

DESCRIPTION

The PL580-6X is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and PECL or LVDS outputs, covering a wide frequency output range up to 640MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The PL580-6X is designed to address the demanding requirements of high performance applications such as SONET, GPS, Video, etc. BLOCK DIAGRAM PACKAGE PIN ASSIGNMENT Note1: ^ Denotes internal pull up resistor. Phase Detector Charge Pump Loop Filter VCO (FXiNx16) VCO Divider XTAL OSC QBAR OE XIN XOUT Q VCON VARICAP Performance Tuner Output Divider PL580-6X VDDANA XIN XOUT SEL2^ OE_CTRL VCON GNDANA LP SEL0^ GNDBUF SEL1^ GNDBUF QBAR VDDBUF Q LM PL580-6X GNDBUF VDDBUF Q QBAR XIN DNC DNC VDDANA DNC XOUT OE_CTRL VCON LP GNDANA LM GNDBUF

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2 OUTPUT ENABLE LOGICAL LEVELS Part # OE State 0 (Default) Output enabled PLL580-68 (PECL) Tri-state Tri-state PLL580-69 (LVDS) 1 (Default) Output enabled PIN DESCRIPTIONS Name TSSOP Pin number 3x3mm QFN Pin number Type P VDD for analog Circuitry. XIN I Crystal input pin. (See Crystal Specifications on page 4). XOUT O Crystal output pin. (See Crystal Specifications on page 4). DNC Do Not Connect OE_CTRL I Output enable control pin. (See OE_CTRL Logic Levels above). VCON I Voltage control input. GNDANA P Ground for analog circuitry. LP LM Tuning inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between LP and adjacent LM pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. GNDBUF P GND connection for output buffer circuitry. Q O PECL or LVDS output. VDDBUF P VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. QBAR O Complementary PECL, LVDS output. GNDBUF P GND connection for output buffer circuitry. DNC Do Not Connect DNC Do Not Connect

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3 FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency VCO Max* VCO Min* Fin x 16 All Other Combinations Reserved All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values for your application. In addition, the chart below could be used as a reference for quick inductor value selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance enhancement of your custom board design, please follow the following instruction: Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side.

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Parallel Fundamental Mode MHz at VCON = 0V 17.7 at VCON = 1.65V 9.5 Crystal Loading Rating CL (xtal) at VCON = 3.3V 5.4 pF Crystal Pullability C0/C1 (xtal) AT cut 250 Recommended ESR RE AT cut Ω Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note, that frequency pulling and oscillator gain may decrease. 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid ms VCXO Tuning Range FXIN = 20 – 40MHz; XTAL C0/C1 < 250 0V ≤ VCON ≤ 3.3V 500 ppm CLK output pullability VCON=1.65V, ±1.65V ±200 ppm VCXO Tuning Characteristic 150 ppm/V Pull range linearity VCON pin input impedance kΩ VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic (with Loaded Outputs) IDD PECL/LVDS 320MHz<Fout<640MHz mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 320.0MHz 0.4 0.5 Integrated jitter RMS Integrated 12 kHz to 20 MHz 622.08MHz 0.4 0.6 ps 320.0MHz Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz ps 320.0MHz Period jitter Peak-to- Peak With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz ps 6. Phase Noise Specifications PARAMETERS FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M UNITS 320.0MHz -59 -86 -116 -129 -124 -140 -148 Phase Noise2 relative to carrier (typical) 622.08MHz -48 -80 -108 -118 -114 -131 -138 dBc/Hz

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6 8. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 uA Output Short Circuit Current IOSD -5.7 mA 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50Ω 50Ω OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7 10. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.2 0.3 0.45 ns Clock Fall Time tf @80/20% - PECL 0.2 0.3 0.45 ns OUT OUT 50Ω 50Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8 LAYOUT RECOMMENDATIONS PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL580 as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL580 layout.

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 9

PACKAGE INFORMATION

C L A E H D e B

16 PIN TSSOP ( mm )

Min. Max. A 1.20 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 4.50 H

6.40 BSC

L 0.45 0.75 e

0.65 BSC

(Preliminary) PL580-68/69 320-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 10

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL580-6X X C L R Order Number Marking Package Option PL580-68OC P580-68OC TSSOP - Tube PL580-68OC-R P580-68OC TSSOP - Tape & Reel PL580-68OCL P580-68OCL TSSOP - Tube (GREEN Package) PL580-68OCL-R P580-68OCL TSSOP - Tape & Reel (GREEN Package) PL580-68QC P580-68QC QFN - Tube PL580-68QC-R P580-68QC QFN - Tape & Reel PL580-68QCL P580-68QCL QFN - Tube (GREEN Package) PL580-68QCL-R P580-68QCL QFN - Tape & Reel (GREEN Package) PL580-69OC P580-69OC TSSOP - Tube PL580-69OC-R P580-69OC TSSOP - Tape & Reel PL580-69OCL P580-69OCL TSSOP - Tube (GREEN Package) PL580-69OCL-R P580-69OCL TSSOP - Tape & Reel (GREEN Package) PL580-69QC P580-69QC QFN - Tube PL580-69QC-R P580-69QC QFN - Tape & Reel PL580-69QCL P580-69QCL QFN - Tube (GREEN Package) PL580-69QCL-R P580-69QCL QFN - Tape & Reel (GREEN Package) TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE O=TSSOP Q= QFN 4x4 L= GREEN PACKAGE NONE= REGULAR PACKAGE R= TAPE & REEL NONE= TUBE PART NUMBER