PL580-30

PL580-30 PLL | Alldatasheet

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Technical content

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 1

FEATURES

Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies. Low phase noise output (@ 1MHz frequency offset -140dBc/Hz for 311.04MHz, -131dBC/Hz for 622.08MHz 19MHz-40MHz crystal input. 38MHz-640MHz output. Selectable PECL, LVDS, or CMOS outputs. No external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages.

DESCRIPTION

The PL580-30 is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and PECL, LVDS, or CMOS outputs, covering a wide frequency output range up to 640MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The PL580-30 is designed to address the demanding requirements of high performance applications such as SONET, GPS, XDSL, etc. BLOCK DIAGRAM DIE CONFIGURATION Note1: ^ Denotes internal pull up resistor. DIE SPECIFICATIONS Name Value Size 62 x 65 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil Y X (0,0) (1550,1475) 62 mil 65 mil GNDOSC GNDBUF GNDDIG DNC LM LP GNDANA DNC OE_SEL^ GNDBUF CMOS LVDSB PECLB VDDBUF VDDBUF PECL LVDS OUTSEL1^ SEL0^ SEL1^ VDDDIG VDDOSC VDDANA VDDANA OUTSEL0v XIN XOUT DNC SEL2 OE_CTRL VCON Die ID: 2222-22A C502A Phase Detector Charge Pump Loop Filter VCO (FXiNx16) VCO Divider XTAL OSC QBAR OE XIN XOUT Q VCON VARICAP Performance Tuner Output Divider (1,2,4,8)

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 2 OUTPUT ENABLE LOGICAL LEVELS OUTSEL0v (Pad #25) OUTSEL1^ (Pad #18) Selected Output LVDS PECL (Default) High Drive CMOS Standard Drive CMOS Note: For bonding convenience, ‘OUTSEL0’ incorporates an internal pull down resistor while ‘OUTSEL1’ incorporates an internal pull up resistor. OUTPUT SELECTION AND ENABLE OE_SEL^ (Pad #9) OE_CTRL (Pad #30) State 0 (Default) Output enabled Tri-state Tri-state 1 (Default) 1 (Default) Output enabled Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”, Pad #30: Logical states defined by PECL levels if OE_SELECT is “0” Logical states defined by CMOS levels if OE_SELECT is “1” FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency VCO Max* VCO Min* Reserved Reserved Fin x 2 Fin x 8 Fin x 16 Fin x 4 All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency.

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 3 PAD ASSIGNMENT Pad # Name X (µm) Y (µm) Ground, Oscillator circuitry. GNDANA 361 109 Ground, Analog circuitry. LP 473 109 Performance/Frequency tuning Inductor. LM 587 109 Performance/Frequency tuning Inductor. DNC 702 109 Do No Connect. DNC 874 109 Do No Connect. GNDDIG 1042 109 Ground, Digital circuitry. GNDBUF 1171 109 Ground, buffer circuitry. OE_SELECT 1400 125 Used to select between PECL or CMOS logic states for OE. Incorporates internal pull up. LVDS 1400 259 LVDS Output. PECL 1400 476 PECL Output. VDDBUF 1400 616 3.3V power supply, Buffer circuitry. VDDBUF 1400 716 3.3V power supply, Buffer circuitry. PECLB 1400 871 Complementary PECL Output. LVDSB 1400 1089 Complementary LVDS Output. CMOS 1400 1227 Single ended CMOS output. GNDBUF 1389 1365 Ground, buffer circuitry. OUTSEL1 1232 1365 Used to select CMOS, PECL or LVDS output type. Incorporates internal pull up. SEL1 1042 1365 SEL0 854 1365 Used to select multiplication factor. Incorporates internal pull up. VDDDIG 659 1365 3.3V power supply, Digital circuitry. VDDANA 559 1365 3.3V power supply, Analog circuitry. VDDANA 459 1365 3.3V power supply, Analog circuitry. VDDOSC 358 1365 3.3V power supply, Oscillator circuitry. OUTSEL0B 194 1365 Used to select CMOS, PECL or LVDS output type. Incorporates internal pull down. XIN 109 1223 Crystal input. See crystal specification for details. XOUT 109 1017 Crystal output. See crystal specification for details. SEL2 109 858 Used to select multiplication factor. Incorporates internal pull up. DNC 109 646 Do Not Connect OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table. VCON 109 181 Voltage Control Input. 0V to 3.3V.

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 4 PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values for your application. In addition, the chart below could be used as a reference for quick inductor value selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance enhancement of your custom board design, please follow the following instruction: Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side.

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 5 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Parallel Fundamental Mode MHz at VCON = 0V 17.7 at VCON = 1.65V 9.5 Crystal Loading Rating CL (xtal) at VCON = 3.3V 5.4 pF Crystal Pullability C0/C1 (xtal) AT cut 250 Recommended ESR RE AT cut Ω Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note, that frequency pulling and oscillator gain may decrease. 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid ms VCXO Tuning Range FXIN = 19 – 40MHz; XTAL C0/C1 < 250 0V ≤ VCON ≤ 3.3V 500 ppm CLK output pullability VCON=1.65V, ±1.65V ±200 ppm VCXO Tuning Characteristic 150 ppm/V Pull range linearity VCON pin input impedance kΩ VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 6 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 38MHz<Fout<100MHz 65/45/30 PECL/LVDS/CMOS 100MHz<Fout<320MHz 80/60/40 Supply Current, Dynamic (with Loaded Outputs) IDD PECL/LVDS 320MHz<Fout<640MHz mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. 5. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS 155.52MHz 0.4 0.5 311.04MHz 0.4 0.5 Integrated jitter RMS Integrated 12 kHz to 20 MHz 622.08MHz 0.4 0.5 77.76MHz 2.5 155.52MHz 311.04MHz Period jitter RMS With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz ps ps 77.76MHz 155.52MHz 311.04MHz Period jitter Peak-to- Peak With capacitive decoupling between VDD and GND. Over 10,000 cycles. 622.08MHz ps 6. Phase Noise Specifications PARAMETERS FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M UNITS 77.76MHz -66 -96 -124 -136 -132 -145 -149 155.52MHz -62 -92 -120 -132 -128 -144 -150 311.04MHz -59 -86 -116 -129 -124 -140 -148 Phase Noise relative to carrier (typical) 622.08MHz -48 -80 -108 -118 -114 -131 -138 dBc/Hz Note: Phase Noise measured at VCON = 0V.

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 7 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 uA Output Short Circuit Current IOSD -5.7 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50Ω 50Ω OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 8 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL FREQ. CONDITIONS MIN. TYP. MAX. UNITS Clock Rise & Fall Times <150MHz 0.2 0.5 0.7 Clock Rise & Fall Times >150MHz <320MHz 0.2 0.4 0.55 Clock Rise & Fall Times tr & tf >320MHz @20/80% - PECL @80/20% - PECL 0.2 0.3 0.45 ns 11. CMOS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V mA Output drive current IOL VOL = 0.4V, VDD = 3.3V mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 0.7 ns Output Clock Rise/Fall Time 20%-80% with 50Ω Load 0.3 ns OUT OUT 50Ω 50Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V

(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 9

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL580-30 X C Order Number Marking Package Option PL580-30DC P580-30DC Die (Waffle Pack) PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D= Die