PL560-08

PL560-08 PLL | Alldatasheet

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Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 02/10/05 Page 1 PRODUCT DESCRIPTION PhaseLink’s Analog Frequency MultiplierTM (AFMs) are the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase locked loop, in CMOS technology. PhaseLink’s patent pending PL56X family of AFM products can achieve up to 800 MHz output frequency with practically no jitter or phase noise deterioration. In addition, the low frequency input crystal requirement makes the AFMs the most affordable high performance timing source in the market. PL560-XX family of products utilize a low-power CMOS technology and are housed in a 16-pin (T)SSOP, and 16-pin 3x3 QFN.

FEATURES

• Non Phase Locked Loop frequency multiplication
• Input frequency from 30-200 MHz
• Output frequency from 60-800-MHz
• Low Phase noise and jitter (equivalent to fundamental crystal at the output frequency)
• Unbeatably low jitter o RMS phase jitter < 0.25ps (12kHz-20MHz) o RMS period jitter < 2.5 ps
• Low Phase Noise o -142 dBc/Hz @100kHz Offset from 155.52MHz o -150 dBc/Hz @10MHz Offset from 155.52MHz
• High linearity pull range (typ. 5%)
• +/- 120 PPM pullability VCXO
• Low input frequency eliminates the need for expensive crystals
• Differential output levels (PECL, LVDS), or single- ended CMOS
• Single 2.5V or 3.3V +/- 10% power supply
• Optional industrial temperature range (-40°C to +85°C)
• Available in 16-pin (T) SSOP, and 3x3 QFN Figure 1: 2x AFM Phase Noise at 311.04MHz

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 3 PRODUCT SELECTION GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Phase Noise AT Frequency Offset From Carrier (dBc/Hz) Part Number Input Frequency Range (MHz) Analog Frequency Multiplication Factor Output Frequency Range (MHz) Output Type Carrier Freq. (MHz) 10 Hz 100 Hz

1 KHz

1 MHz

622.08 -55 -85 -110 -130 -137 -148 -150 PL560-09 75 - 200 300 - 800 LVDS 622.08 -55 -85 -110 -130 -137 -148 -150 PL560-37 30 - 80 120 - 320 CMOS 155.52 -50 -82 -110 -128 -142 -148 -150 PL560-38 30 - 80 120 - 320 PECL 155.52 -50 -82 -110 -128 -142 -148 -150 PL560-39 30 - 80 120 - 320 LVDS 155.52 -50 -82 -110 -128 -142 -148 -150 PL560-47 30 - 80 60 - 160 CMOS 155.52 -65 -95 -122 -138 -142 -148 -149 PL560-48 30 - 80 60 - 160 PECL 155.52 -65 -95 -122 -138 -142 -148 -149 PL560-49 30 - 80 60 - 160 LVDS 155.52 -65 -95 -122 -138 -142 -148 -149 PL560-68 75 - 200 150 - 400 PECL 311.04 -60 -85 -112 -135 -142 -150 -151 PL560-69 75 - 200 150 - 400 LVDS 311.04 -60 -85 -112 -135 -142 -150 -151 Phase Noise numbers were obtained using Agilent 5500. FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE RMS Period Jitter (Ps) Peak to Peak Period Jitter (Ps) RMS Accumulated (L.T.) Jitter (Ps) Phase Jitter (12 KHz-20MHz) (Ps) Spectral Specifications / Sub-harmonic Content (dB), Frequency (MHz) Part Number Jitter Calc. Freq. (MHz) Max. Min. Typ. Max. Carrier Freq. (Fc) -75% (Fc) -50% (Fc) -25% (Fc) +25% (Fc) +50% (Fc) +75% (Fc) PL560-08 622 0.09 622 -50 -50 -45 -47 -47 -55 PL560-09 622 0.09 622 -50 -50 -45 -47 -47 -55 PL560-37 155 2.5 0.25 155.52 -75 -62 -65 -75 PL560-38 155 2.5 0.25 155.52 -75 -62 -65 -75 PL560-39 155 2.5 0.25 155.52 -75 -62 -65 -75 PL560-47 155 2.5 0.25 155.52 -68 -68 PL560-48 155 2.5 0.25 155.52 -68 -68 PL560-49 155 2.5 0.27 155.52 -68 -68 PL560-68 311 2.5 0.18 311.04 -72 -85 PL560-69 311 2.5 0.18 311.04 -72 -85 Note: Wavecrest Data 10,000 hits. No Filtering was used in Jitter Calculations. Agilent 5500 was used for Phase Jitter Calculations. Spectral Specifications were obtained using Agilent E7401A.

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 4 CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS BOARD LAYOUT CONSIDERATIONS To minimize parasitic effects, and improve performance: Place the crystal as close as possible to the IC. Make the board traces that are connected to the crystal pins symmetrical. The board trace symmetry is important, as it reduces the negative parasitic effects, for a clean frequency multiplication with low jitter. Parasitic have negative effect on frequency pulling of a VCXO and jitter. CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE CRYSTAL SPECIFICATIONS TUNING PERFORMANCE CL (xtal) ESR (RE) CRYSTAL TUNING (Typical) PART NUMBER CRYSTAL RESONATOR FREQUENCY (FXIN) MOD E CONDI- TIONS TYP. Max. CRYSTAL FREQ (MHz) C0/C1 VC: 1.65V 0V VC: 1.65V 3.4V 155.52 3.0pF 12.2fF 245 -145 ppm +108 ppm PL560-08/09 PL560-68/69 75~200MHz Funda- mental At Vcon 1.65V 5pF 30 Ω 155.52 1.8pF 5.7fF 316 -134 ppm +87 ppm 30.72 2.8pF 12.4fF 228 -167ppm +176ppm 30.72 4.5pF 19.1fF 236 -163ppm +167ppm 38.88 5.1pF 20.9fF 242 -131ppm +98ppm 38.88 5.3pF 25.6fF 207 -157ppm +141ppm PL560- 37/38/39 PL560- 47/48/49 30~80MHz Funda- mental At Vcon 1.65V 5pF 30 Ω 77.76 2.0pF 6.7fF 305 -92ppm +110ppm Note: Non specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink. XTA XTAL Ceramic SMD AFM IC XIN (Pin # 4) XOUT (Pin # 5) AFM IC XIN (Pin # 4) XOUT (Pin # 5)

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 5 VOLTAGE CONTROL SPECIFICATION PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time TVCXOSTB From power valid ms VCXO Tuning Range XTAL C0 /C1 <300 200 ppm CLK output pullability VCON= 1.65V ± 1.65V XTAL C0 /C1 <300 ±100 ±120 ppm Linearity VCON input impedance 130 kΩ VCON modulation BW 0V < VCON < 3.3V, -3dB kHz EXTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION The required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design (Gerber file available upon request). These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value. For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink’s board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure:

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 6 Figure 5: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE PCB side - Cinternal = Based on AFM Device - LWB1 = 2 nH, (2 places), Stray inductance - Cpad = 2.0 pF, Bond pad and its ESD circuitry - Cstray = 1.0 pF, Stray Capacitance - C11 = 0.4 pF, The following amplifier stage - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if used

• There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
• LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23.
• Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used.
• Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
• For 4X AFMs, repeat the same procedure in the L4X worksheet.
• See the examples below.

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 7 DETERMINING STRAY L’s AND C’s IN A LAYOUT Figure 5: Diagram Representation of the Board Layout Lets take the PL560-38 (4x VCXO) for example. This takes a crystal input range of 30 to 80 MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz). 120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL560-3x in the L2x worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4x at 120 MHz. Results: L2X = 180 nH, L4X = 82 nH. 320 MHz AFM tuning: Repeat the previous procedure for L2x at 120 MHz and L4x at 320 MHz. Results: L2X = 24 nH, L4X = 10 nH. Proceed and assemble the test units. Measuring 120 MHz L2x: Connect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3v pk-pk amplitude. Vary the generator above and below 30 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak accorded at 29.8x2 or 59.6 MHz.

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 8 Measuring 320 MHz L2x: Connect the RF generator and scope probe as shown in Figure 6, above. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3v pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak accorded at 78.0 x 2 = 156 MHz In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2x value with 180 nH and see if it peaks at 59.6 MHz. IF it it does not, adjust the Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2x and fine tune LWB1 for 156 MHz. Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray) Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray) Internal Capacitor Selection by Device Device Number Cinternal (pF) P560-0X 7.625 6.250 P560-3X 34.125 16.500 P560-4X 34.125 P560-6X 7.625

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 9 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature TA -40 +85 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 Input Static Discharge Voltage Protection kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. PECL ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) IDD Fout = 622.08 mA Operating Voltage VDD 2.25 3.63 V Output Clock Duty Cycle @ Vdd – 1.3V Short Circuit Current ±50 mA Output High Voltage VOH RL = 50 Ω to (VDD – 2V) VDD – 1.025 V Output Low Voltage VOL VDD – 1.620 V Clock Rise Time tr @20/80% 0.25 0.45 ns Clock Fall Time tf @80/20% 0.25 0.45 ns PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF DUTY CYCLE 45 - 55% 55 - 45% OUT OUT 50Ω 50Ω PECL Levels Test Circuit VDD 2.0V 50% OUT OUT tSKEW PECL Output Skew

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 10 LVDS ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) IDD Fout = 622.08, LVDS mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 1.25V (LVDS) Short Circuit Current ±50 mA Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 µA Output Short Circuit Current IOSD -5.7 mA Differential Clock Rise Time tr 0.2 0.5 0.7 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.5 0.7 ns OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit OUT LVDS Transistion Time Waveform OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF OUT OUT VOD VOS 50Ω 50Ω LVDS Levels Test Circuit

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 11 CMOS ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded Outputs IDD At 100MHz, load=15pF mA Operating Voltage VDD 2.25 3.63 V Output High Voltage VOH IOH = -8.5mA 2.4 V Output Low Voltage VOL IOL = 8.5mA 0.4 V Output High Voltage at CMOS level VOHC IOH = -4mA VDD– 0.4 V Output drive current IOSD VOL = 0.4V, VOH = 2.4V (per output) 8.5 mA Output Clock Rise/Fall Time Tr/Tf 10% ~ 90% VDD with 10 pF load 1.2 1.6 ns Output Clock Duty Cycle Measured @ 50% VDD Short Circuit Current IS ±50 mA

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 12 BOARD LAYOUT DESIGN CONSIDERATIONS FOR AFMs L2x and L4x: Try to reduce the PCB trace inductance to a minimum by placing L2x and L4x as physically close to their respective pins as possible. Also be sure to bypass each Vdd connection especially taking care to place a 0.01 uF bypass at the Vdd side of L2x and L4x (See recommended layout). Crystal connections: Be sure to keep the ground plane under the crystal connections continuous so that the stray capacitace is consistent on both crystal connections. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection pins of the IC. If you chose to use a series capacitance and or inductor to fine tune the crystal frequency be sure to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout). Even if one of the capacitors with be a 0.01 uf and the other is used to tune the frequency. And to further maintain a symmetrical balance on a crystal that may have more internal Cstray on one pin or the other. Place capacitor pads (Cbal) on each crystal lead to ground (see recommended layout). You can refer to (xxx) if tuning of Cbal is required. R3rd is only required if a 3rd overtone crystal is used. Vdd and Gnd: Bypass VDDANA and VDDBUF with separate bypass capacitors and if a Vdd plane is used feel each bypass cap with its own via. And be sure to connect any ground pin including the bypass caps with short via connection to the ground plane. OESEL: J1 is recommended so the same PCB layout can be used for both Output Enable low (No J1) or Output Enable high (J1 = ohms) if this function is chosen. Note: Please contact PhaseLink for the Gerber files of the board layouts. 4X Layout 2X Layout

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 13 PACKAGE PIN DESCRIPTION AND ASSIGNMENT PIN ASSIGNMENTS Name Pin# Type Product

Description

I 2X & 4X Set to “0” (GND) to choose to turn off the oscillator when outputs are disabled (OE). Default (no connect) is OSC always on. GNDOSC P 2X & 4X GND connection for oscillator circuitry. VCON I 2X & 4X Control Voltage input. Use this pin to change the output frequency by varying the applied Control Voltage. XIN I 2X & 4X Input from crystal oscillator circuitry. XOUT O 2X & 4X Output from crystal oscillator circuitry. OECTRL I 2X & 4X Output Enable input (see "OE LOGIC SELECTION TABLE"). DNC Do Not Connect. L4X I External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This inductor is used with 4X AFMs. GNDANA GND connection. VDDOSC P VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. GNDBUF P 2X & 4X GND connection for output buffer circuitry. Q O 2X & 4X PECL/LVDS or CMOS output. QBAR O 2X & 4X Complementary PECL/LVDS output or in phase CMOS. VDDBUF P 2X & 4X VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDDANA P 2X & 4X VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. OESEL I 2X & 4X Selector input to choose the OE control logic (see “OE SELECTION TABLE”. VDDOSC P 2X & 4X VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. L2X I 2X & 4X External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. PLL560-0X OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL L4X VDDOSC L2X VDDOSC OESEL VDDANA VDDBUF QBAR Q GNDBUF P560-0X VDDOSC OECTRL XOUT L4X VDDBUF Q GNDBUF QBAR OESEL VDDANA VDDOSC L2X GNDOSC OSCOFF SEL VCON XIN PLL560-4X OSCOFFSEL GNDOSC VCON XIN XOUT OECTRL DNC GNDANA L2X VDDOSC OESEL VDDANA VDDBUF QBAR Q GNDBUF P560-4X GNDANA OECTRL XOUT DNC VDDBUF Q GNDBUF QBAR OESEL VDDANA VDDOSC L2X GNDOSC OSCOFF SEL VCON XIN

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 14

PACKAGE INFORMATION

16 PIN SSOP

16 PIN 3x3 QFN

C L A

16 PIN SSOP ( inch )

Min. Nom. A .053 .064 .004 .006 B .008 C .007 D .189 .193 E .150 .154 H .228 .236 L .016 .025 e .025 BASIC E H D e B Max. .069 .010 .012 .010 .197 .157 .244 .050

Analog Frequency Multiplier VCXO Family of Products 47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev.:03-22-05 Page 15

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL560-XX X X Order Number Marking Package Option PL560-XXOC-R P560-XX OC TSSOP – Tape and Reel PL560-XXQC-R P560-XX QC QFN – Tape and Reel PL560-XXXC-R P560-XX XC SSOP – Tape and Reel PL560-XXOC P560-XX OC TSSOP – Tube PL560-XXQC P560-XX QC QFN – Tube PL560-XXXC P560-XX XC SSOP – Tube PART NUMBER TEMPERATURE C= COMMERCIAL I= INDUSTRIAL PACKAGE TYPE O=TSSOP Q=QFN 3x3 X=SSOP