PI6049A

PI6049A AMI | Alldatasheet

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REVISION NUMBER : REV 2 PAGES : 1 of 13 DATE : 2-13-04 PI6049A Contact Image Sensor Data Sheet

2.5 MHz maximum pixel rate

scanners, check readers, and office automation equipment. spacing is approximately 42.3 µm. The size of each sensor without the scribe lines is 14560 µm by 380 µm. Figure 1. Sensor Block Diagram

There are five unique features incorporated in the PI6049A which improve the sensor’s performance. 1. Pixel-to-Pixel Offset Cancellation Circuit The sensor employs a pixel-to-pixel offset can cellation circuit, which reduces the Fix Pattern Noi se (FPN), and amplifier offsets. In ad dition, this i nnovative circuit design g reatly improve s t he opti cal li nearity an d lo w noi se sensitivity. 2. Parallel Integrate, Transfer and Hold The sensor has a parallel integrate, transfer and hold feature, which allows the sensor to be read out while photon integration is taking pla ce. These features are approached through the use of an integrate and hold cell, located at ea ch pixel site. Ea ch p ixel’s charge is re ad from it s storage site as the sensor’s shift regi ster sequentially transfers each pixel’s charge onto a common video line. 3. Dual Scan Initiation Inputs, GBST and SI Each sensor has two scan initiation inputs, the Global Start Pulse (GBST) and the Start Pulse (SI). Th ese clocks help to reduce the sen sor-to-sensor t ransition Fix Pattern Noise by initializi ng an d p reprocessing all sensors simultaneously before they start their read out scan . The in ternal shift registe r start s the scan after GB ST is clocked in on the falling edge of the Clock input (CLK). The Start Input Control (SIC) selects the first sensor in a sequence of cascaded sensors to operate with 29 clock cycles of delay by connecting it to Vdd on the first sensor, and to Ground for all subsequent sensors. Then, only the first sen sor clocks out 29 inactive pixels before accessing its first a ctive pixel. Duri ng these 29 clock cycles, the first sensor and all of the subsequent cascaded sensors cycle through their pre-scan initialization process. After initialization, only the first sens or starts its read cycle with its first-active pixel app earing on the 3 0th clock cycle. The second and subsequent sensors await the entry of their Start Pulse (SI). Furthermore, the first sensor’s Start Pulse (SI) is left unconne cted, while the sub sequent sensors all have their Start Pulse’s (SI) connected to the SO of their respective preceding sensor. The external scan Start Pulse (SI) is connected to all of the sensors' Global Start Pulse (GBST) inputs. As the first sensor completes its scan, its End-of-Scan (SO), appears 1 pixel before its last pixel. The second and subsequent sensors will th en sta rt thei r regi sters 1 clock cycle b efore th e appearance of their respe ctive first pixels, and their SO also appears 1 pixel before their last pixel. 4. Power Saving Each sensor incorporates a power-saving feature when multiple sensors are cascaded together to form a linear imaging array. The Start In put Control (SIC) on ea ch sensor selects a unique f eature of powering up a particular sensor’s output amplifier when it’s selected and po wering it do wn when n ot selected. For the PI6049A, only the first sensors’ amplifier is used and all subsequent sensors have their amplifiers turned off. The pixels from each sensor a re transfe rred o nto a commo n video line which i s connected to th e amplifier of the first sensor. The advantage of using only o ne active amplifier is two f old; saving on power consumption and reducing sensor-to- sensor FPN. 5. Common Reference Voltage between Cascaded Sensors Each sensor has an input/output bias control (VR), which serves as an offset voltage reference. Each bias control pad is connected to an internal bias source and tied to its own amplifier’s reference bias input. In operation, these pads on eve ry sen sor are con nected together. Ea ch sen sor the n “shares” the sam e bia s level to maintain a constant bias among all of the sensors. Page 3 of 13, Revised 2-13-04

first sensor. (See discussion of the sensors unique features for further details). features for further details). Clock Input for the Shift Register. DVDD I Digital Power Supply. AVSS I Analog Signal Ground. DVSS I Digital Signal Ground. Output Video Signal from the Amplifier. OR O Differential Reference Output. OS O Differential Video Output. Output from the Shift Register at the end of a scan. Table 1. Input and Output Terminals

Table 2 lists the electro-optical specifications of the PI6049A sensor at 25oC and Vdd = 5.0 volts. Table 2. Electro-Optical Specifications

• Notes for the above Table 2 are listed on the next page under “Definitions of Electro-Optical Specifications”. Page 6 of 13, Revised 2-13-04

Definitions of Electro-Optical Specifications All electrical specifications are measured at a pixel rate of 2.0 MHz, a temperature of 25oC, Vdd=5.0 volts, and at an inte gration time of 2.2 ms. Th e ave rage outp ut voltage (V pavg), is adj usted to approximately 1.0V, unle ss stated otherwise. The modules’ internal Green LED (525 ± 20 nm ) was u sed a s the li ght source for measurements re quiring i llumination. As a gui deline, the re commended l oad o n the output sho uld be 1KΩ<RL<10kΩ. All measurements were taken with a 2k ohm load on the output. 1. Sensitivity (Sv) is defined as the slope of the Vpavg vs Exposure curve. 2. Saturation Voltage (VSat) is defin ed as the m aximum video o utput voltage swing measured from th e dark level to the saturation level. It is mea sured by using the module LED light source with the module imaging a uniform white target. The LED light level is increa sed until the output voltage no longer in creases with an increase i n t he LE D b rightness. T he dark level is set by th e v oltage on V R and in a typical CIS m odule application, sits at approximately 0.7V. 3. Photo-Re sponse Non-Uniformity (Up). Up = ((Vpma x-Vpavg)/Vpavg) x 100% or ((Vpavg-Vpmin)/Vpavg) x 100%, whicheve r is the greater, whe re Vpmax is the maximum pixel output voltage in the light, Vpmin is the minimum pixel output voltage in the light and Vpavg is average output voltage of all pixels in the light. 4. Adjacent Photo-Response Non-Uniformity (Upn). Upn = Max ((Vpn – Vpn+1) / Min (Vpn, Vpn+1)) x 100%, where Vpn is the pixel output voltage of pixel n in the light. 5. Dark Output Voltage (Vd). Vd is the average dark output level and is essentially the offset level of the video output in the dark. The dark level is set by the voltage on VR and in a typical CIS module application, sits at approximately 0.7V. 6. Dark Output Non-Uniformity (Ud). Ud = Vdmax-Vdmin, where Vdmax is the maximum pixel output voltage in the dark and Vdmin is the minimum pixel output voltage in the dark. 7. Random Thermal Noise (rms), (Vno ), is the standard deviation of n pixels in t he dark. A sample size n=64 was used. A 4 mV rms value has a peak-peak equivalent of 24 mV. 8. Senso r-to-Sensor Photo-Response Non-Uniformity (Usensor). Usensor = (Vpavg – Wavg) / Wavg), where Wavg is the average output of all sensors on the same wafer that pass all other specifications. 9. Photo-Response Linearity (PRL). Photo-Response Linearity is defined as the max deviation of response compared to a best fit line. The data points plotted are those that lie within 10% of the saturation level and 90% of the saturation level. Outside these ranges the module is operating close to non-linearity. Page 7 of 13, Revised 2-13-04

Table 3 lists the recommended operating conditions @ 25oC. Table 3. Recommended Operating Conditions @ 25oC

1. Applies to all clocks; GBST, SIC, SI and CLK.
2. The dark level is set by the voltage on the VR input pad, which is internally set to a typical value of 0.7 volts.

Alternatively, if the user wishes to use a dark level greater than this, then VR can be supplied externally.

1. Although the device will operate with a pixel rate of less than 500 KHz, it is recommended that the device be

significant integration of dark current.

1. Tint is the in tegration tim e of a sin gle sen sor an d is the time between two Start Pulse s. The minim um
2. The clock duty cycle is defined as the ratio of the positive duration of the clock to its period.

Table 4 lists the absolute maximum ratings. Table 4. Absolute Maximum Ratings

1. Applies to all clocks; GBST, SIC, SI and CLK

Table 5. Timing Requirements

1. The shift re gister will lo ad on all f alling CLK edges, so setup a nd hold times (T set, Thol d) a re n eeded to
2. SI starts the register scanning and the first active pixel is read out on the 30th clock cycle of the CLK signal.

sensor becomes the SI to the subsequent sensor, hence the SI clock = the SO clock.

1. As discussed under the thi rd unique feature, the GB ST starts the initialization process and prep rocesses all
2. The transition between pixels does not always reach the dark offset level as shown in Figure 4 (Vout). Figure
3. The pixel rise time is defined as the tim e from when the CLK’s rising edge has reached 50% of its maximum

lowest point before the next pixel begins to rise.

pixel which coincides with the 344th clock cycle.

29 Inactive pixels (29 Clocks) 344 Active Pixels (344 Clocks)

Figure 4. Overall Timing Diagram Figure 5. Timing of GBST-to-First Pixel of the First Sensor

Page 13 of 13, Revised 2-13-04 2004 Peripheral Imaging Corporation. Printed in USA. All rights reserved. Specifications are subject to change without notice. Con tents m ay n ot be rep roduced i n whole or in p art with out th e express prior written permission o f Peripheral Imaging Corporation. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by P eripheral Im aging C orporation f or i ts use nor f or a ny i nfringement of pat ents or ot her rights granted by implication or otherwise under any patent or patent rights of Peripheral Imaging Corporation