AMIS-49200

AMIS-49200 AMI | Alldatasheet

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Technical content

AMIS-49200 Fieldbus MAU Data Sheet AMIS-49200 Fieldbus MAU Chip 1 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet Table of Contents 2 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

1.0 Introduction

1.1 Overview

AMIS-49200 Fieldbus MAU (media access unit) is a transceiver chip for low speed FOUNDATION Fieldbus® and Profibus® PA devices. It was des igned to be a ne ar pin-for-p in re placement of the Yoko gawa µSAA22Q MAU. “Near pin-f or-pin” means that associat ed component values may change, but no board changes are required.

1.2 Definitions, Acronyms and Abbreviations

ESD - Electrostatic discharge ICFF - FOUNDATION Fieldbus LQFP - Low profile quad flat pack Manchester - Communications encoding scheme implemented in FOUNDATION Fieldbus MAU - Medium attachment unit MDS - Medium dependent sub-layer µSAA22Q - Name of Yokogawa’s MAU IC

1.3 References

• Fieldbus Medium Attachment Unit (MAU) Ch ip, µSAA22Q, Yokogawa Electric Corporation, June 12, 1998, Document No.: SS-96-01 (Rev.3).
• Fieldbus Standard for Use in Industrial Control Systems Part 2: Physical Layer Specification and Service Definition, Amendment to Clause 22 ISA/SP50 –1996-544B, dS50.02, Part 2, Draft Standard.
• Profibus PA s pecifications EN 501 70 (form erly DIN 19 245) covers al l o f Profibus an d inclu des P A ( 31.25 kb ps Intrinsica lly Safe Physical Layer), references IEC 61158-2.

2.0 AMIS-49200 Fieldbus MAU Description

2.1 Features

AMIS-49200 F ieldbus MA U i s a transce iver IC for lo w s peed F OUNDATION F ieldbus a nd Profi bus P A devic es. It incor porates t he following features:

• Current consumption 500uA (typ)
• VCC voltage: 6.2V to 4.75V
• VDD voltage: 5.5V to 2.7V
• Compatible to IEC 1158-2 and ISA 50.02
• Shunt regulator
• Voltage reference (internal only)
• Series regulator
• Band-pass filter
• Slew rate control
• Segment current control
• Low voltage detection
• Carrier detect
• Data rate: 31.25kbps voltage mode
• Dual voltage supply 3-6.2V
• 44-pin LQFP package 3 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

2.2 Block Diagram

N_PFail1N_PFail2 Vmid Vref SHUNT SGNDSHSETIN SHSET SRSET SRTR SRAO SRSETIN Vmid CRT CCOUT CCINM CCINP TXE POL VSS SIGIN HPF Vref LPF FLTOUT FLT VO VDD TXS RXS CCD RXA VSS VSS MDS Interface Bandpass Filter Carrier Detector Series Regulator Shunt RegulatorLow Voltage Detectors Current Driver Vmid Reference BandgapBias Circuitry Zero-Cross Detector Receive Block Transmit Block Power Supply Block Tri-Level Modulator Slew Control 31 30 218 1096 7451511 1214 VSS42 VSS43 MDS_CTRL26 VSS VSS VSS VSS VSS VCC VCC VCC VCC VCC VCC VSS Figure 1: AMIS-49200 Fieldbus MAU Block Diagram 4 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

2.3 Package Information

The IC will be packaged in a 44-pin LQFP package as shown below. Figure 2: Package Dimensions (44-pin LQFP) 5 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet AMIS-49200 Fieldbus MAU 44 pin LQFP 12 3 567 33 32 31 30 26 25 24 2329 28 27 VSSRxA RxS TxE TxS POL VSS VSS VSS VSS VSS VCC 89 10 114 VDRV VSS CRT VCC VDD VO SRTR SRAO SRSET SRSETIN VSS CCD FLOUT FLT LPF HPF SIGN NC1 CCOUT CCINM CCINP VREF VMID N_PFAIL1 N_PFAIL2 SHSETIN SHSET SHUNT SGND VSS VSS VSS Pin Information Figure 3: AMIS 49200 Fieldbus MAU Pin Out Table 1: Pin Numbers and Signal Description Signal Name Pin No. I/O (Note 1) Description VSS 1 Ground Connect to ground VREF 2 AO Internal bandgap voltage (1.18V) VMID 3 AO 2V bias voltage for AC signals N_PFAIL1 4 AI/O Power fail alarm at VCC input. This pin is an open-drain output of negative logic. N_PFAIL2 5 AI/O Power fail alarm at VDD input. This pin is an open-drain output of negative logic. SHSETIN 6 AI Feedback (non-inverting) input for the shunt regulator SHSET 7 AO Divided voltage of VCC input. Feeding this voltage to SHSETIN pin results in 5V voltage at VCC. SHUNT 8 AI Control pin of the shunt regulator. Its sink current (25mA max) is controlled so that the voltage at SHSETIN is equal to VREF (1.18V). VSS/ SGND 9 Ground The cur rent absorbed b y S HUNT pin ( 25mA ma x) is fed to this pin, which must be connected to the ground level VSS 10 Ground Ground VSS 11 Ground Ground SRSETIN 12 AI Feedback (inver ting) input for the seri es regul ator. T he series regulator controls its output (SRA O) to m ake this input voltage is equal to VREF (1.18V). SRSET 13 AO Divided voltage of VO output. Feeding this voltage into SRSE TIN pin results in 3V at VO pin. SRAO 14 AO Output pin of an operational amplifier for the series regulator SRTR 15 AI Gate of a PMOS transistor for the series regulator VO 16 AO Output pin of the series regulator. (20mA max) 6 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet Table 1: Pin Numbers and Signal Description (Continued) Signal Name Pin No. I/O (Note 1) Description VDD 17 Digital Supply Supply voltage input for digital block VCC 18 Analog Supply Analog supply voltage CRT 19 AI/O Current integration to limit output slew rate VSS 20 Ground Ground VDRV 21 AO Output of an operational amplifier for slew rate control. This signal can be fed to current driver. VSS 22 Ground Ground CCINP 23 AI Non-inverting input of an operational amplifier for transmission current driver CCINM 24 AI Inverting input of an operational amplifier for transmission current driver CCOUT 25 AO Output of an operational amplifier for transmission current driver MDS_CTRL 26 AI For POL = VDD MDS_CTRL should = VSS FOR POL = VS S MDS_CTRL can be tied to VDD or used as a not reset to control when transmit communications will be enabled SIGIN 27 AI Input pin of the band-pass filter. This pin is connected to VMID bias level w ith 270K resister. HPF 28 AI Feedback signal of high-pass filter. This pin is connected to the o utput of an opamp for high pass filter with 75K resistor. LPF 29 AI Non-inverting input of an operational amplifier for the low-pass filter FLT 30 AI Input pin of low-pass filter for feedback. This pin is connected to the output of the high-pass filter throug h 20kΩ and the non-inverting input of the low-pass filter through 54kΩ resisters. FLTOUT 31 AO Output of the o perational amplif ier for the lo w-pass filter. This signal is internally connected to non-inverting input to form a voltage-follower. CCD 32 AO Current integration (for carrier detect circuit) VSS 33 Ground Ground RXA 34 DO MDS-MAU interface signal for received si gnal activity. This pin is a push-pull output. RXS 35 DO MDS-MAU interface signal for received signal. This pin is a push-pull output. TXE 36 DIS MDS-MAU interf ace signal for enable si gnal tra nsmission (Sch mitt Trigger Input) TXS 37 DIS MDS-MAU interface signal for signal to be transmitted (Schmitt Trigger Input) POL 38 DIS Selects polarity of T xE input. When th is pin is connected to GND, TxE is active high. When this pin is connected to VDD, TxE is active low. VSS 39 Ground Ground VSS 40 Ground Ground VSS 41 Ground Connect to ground VSS 42 Ground Connect to ground VSS 43 Ground Connect to ground VCC 44 Analog Supply Analog supply voltage Note: 1. AI = Analog Input, AO = Analog Output, AI/O = Analog Input/Output, DIS = CMOS Digital Input (Schmitt Trigger), DO = CMOS Digital Output. 7 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

3.0 Electrical Characteristics

3.1 Operating Conditions

Unless otherwise noted, all block and sub-block specifications apply over the operating temperature (-40 to 85oC) Table 2: Absolute Maximum Ratings Parameter Symbol Min. Max. Units Conditions Analog block supply voltage VCC -0.3 6.5 V Digital block supply voltage VDD -0.3 6.0 V Digital input pin voltage VIN -0.3 VDD + 0.3 V (TxS, TxE, & POL pins) Digital output pin voltage VOUT -0.3 VDD + 0.3 V (RxS and RxA pins) Input pin current IIN - ±5 mA Not for shunt pin Output pin current IOUT - 30 mA For shunt, SGND and VO Storage temperature TStorage -55 125 °C Table 3: Normal Operating Conditions Parameter Symbol Min. Typ. Max. Units Conditions Analog supply voltage VCC 4.75 5 6.2 V Digital supply voltage VDD 2.7 3 VCC - 1.1V V Supply voltages are configurable, or can be supplied from off-chip Storage temperature TOperating -40 85 °C Current consumption ICC 500 800 µA 25°C, SHUNT current = 1mA, No current from series regulator Table 4: CMOS Input Specifications Parameter Symbol Min. Max. Units Input high voltage VIH 0.7•VDD VDD V Input low voltage VIL 0 0.3•VDD V Input high current IIH 1 µA Input low current IIL -1 µA Schmitt negative threshold Vt- 0.2•VDD V Schmitt positive threshold Vt+ 0.8•VDD V Schmitt hysteresis Vh 1 V 8 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

3.2 Power Supply Blocks

Table 5: Regulator Specifications Parameter Symbol Min. Typ. Max. Units Conditions Shunt Regulator Sink current ISH 0.001 25 mA Internal pass t ransistor N-ch & pad Load capacitance CSH 5 µF Load regulation 0 1.6 4 % ISH = 1 to 25mA Temperature coefficient TCVcc ±200 ppm/°C No load capacitance Series Regulator Input voltage VCC 4.75 6.2 V Internally tied to VCC pin 2.91 3.0 3.09 V Preset, ISR = 0 Output voltage VO 2.85 3.5 V External setting & N-JFET Output current ISR 20 mA Internal pass tr ansistor P-ch & pad Load capacitance CSR 5 µF For stability use Cap w/ ESR Load regulation 0 2 4 % ISR = 0 to 20mA Temperature coefficient TCVo ±200 ppm/°C Low Voltage Detectors (applies to N_PFail1 and N_PFail2) Threshold VTH9 85 90 95 % Vref SxSETIN > VTH9 (output: L Æ H) Hysteresis VHYS5 .012 .025 .038 V SxSETIN < (VTH9 - VHYS5) (output: H Æ L ) Output sink current IOL 30 135 µA VOL=0.4V (open drain) Output leakage current IL 1 µA VOH = 5V Table 6: Voltage Reference Specifications Parameter Symbol Min. Typ. Max. Units Conditions Bandgap Voltage Reference Output voltage tolerance VREF 1.157 1.185 1.205 V Equates to: +/- 2 percent Temperature drift 50 ppm/°C Hysteresis VREFHYS - 100 - µV Note 1 Supply voltage VCCREF 4.75 5 6.2 V Load current IREFOUT - - 0 µA No load during operation VMID voltage reference Output voltage VMID 1.95 2.0 2.05 V Output current IMID -30 100 µA Load capacitance CMID 0.01 0.1 1 µF DVC6000F uses 1uF Temperature coefficient TCMID ± 200 ppm/°C Notes: 1. Hysteresis is defined as the change in the 25°C reading after 85°C to 25°C cycle and –40°C to 25°C cycle.

3.3 Transmitter Blocks

Table 7: MDS-MAU Interface Parameter Symbol Min. Typ. Max. Units Conditions MDS-MAU Interface POL input pin POL V TxE input pin TxE V TxS input pin TxS See Schmitt Trigger Input Specs. V Note: The associated MDS chip must handle the jabber detect function. 9 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet Table 8: Tri-level Modulator Parameter Symbol Min. Typ. Max. Units Conditions Tri-level Modulator and Slew Control (Output is at VDRV) Output voltage VO VMID 3.02 V Load current IO -35 +120 µA |∆V| 10mV Output for silence VS VMID+0.485 VMID+0.500 VMID+0.515 V TXE disabled Output for high level VH VS+0.380 VS+0.400 VS+0.420 V TXE active Output for low level VL VS-0.420 VS-0.400 VS-0.380 V TXE active Asymmetry of VH and VL ∆VHL -0.02 0.02 V Rise and fall times tf, tr 4.7 µsec Note 2 (CRT=22pF) Notes: 2. By adding an e xternal capa citor betw een the CRT pin a nd ground, slew ra te at VDRV outpu t can be contr olled. The controlling equation i s tf or tr =2us + should have a guard pattern around them to avoid unnecessary interference. Table 9: Current Control Amplifier Parameter Symbol Min. Typ. Max. Units Conditions Current Control Amplifier (Output is at CCOUT) Input common mode voltage range VCM 0 VCC – 1 V Output voltage swing VO 1 VCC – 0.5 V Load current Io -2300 100 µA Input offset voltage VOS -3 +3 mV Slew rate SR 0.54 V/µs Gain bandwidth product GBW 1.15 MHz Phase margin PM 66 Deg CL=10pf RL=200k 10 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

3.4 Receiver Block

Table 10: Receiver Sub-blocks Parameter Symbol Min. Typ. Max. Units Conditions Band Pass Filter Input voltage VBP 1 4 V SIGIN pin to GND Output voltage swing FLTOUT 1 4 V Output slew rate SR 0.6 V/µs Input offset voltage VOS ± 5 mV RF1 60 75 90 kΩ RF2 216 270 324 kΩ RF3 16 20 24 kΩ Filter resistors RF4 43 54 65 kΩ Carrier Detector VTH+ 40 50 60 mV Threshold voltage VTH- -60 -50 -40 mV Relative to VMID Output high voltage VOH VDD-0.6 V IOH = 0 mA Output low voltage VOL 0.3 V IOL = 0 mA Output high current IOH 50 µA VDD-VO ≤ 0.6V Output low current IOL 50 µA VO ≤ 0.6V Output rising time tR 0.3 µs CL = 10pF Output leak current tF 0.3 µs CL = 10pF Zero-cross Detector VTH+ VMID+0.025 VMID+0.040 VMID+0.058 V No carrier Threshold voltage VTH- VMID VMID VMID V Carrier active Output high voltage VOH VDD-0.6 V IOH = 0 mA Output low voltage VOL 0.3 V IOL = 0 mA Output high current IOH 50 µA VDD-VO ≤ 0.6V Output low current IOL 50 µA VO ≤ 0.6V Output rising time tR 0.3 µs CL = 10pF Output leak current tF 0.3 µs CL = 10pF Notes: 1. The band pass filter is made up of a two pole high pass filter in series with a two pole low pass filter. The filter consists of four resistors internal to AMIS-49200, and four external capacitors. The active part of each filter is an amplifier connected in a follower configuration. 11 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

4.0 Theory of Operation

4.1 Overview

AMIS-49200 incorporates two different po wer supply circuits. Both derive their po wer from the bus. Using th e internal configuration, the sh unt r egulator is set for 5V and th e s eries reg ulator is s et for 3V. Us ers ca n m odify either p ower s upply by ad ding external components. AMIS-49200 Fieldbus can also monitor these power supply voltages and generate power-fail signals if they fall below a specified value. AMIS-49200 Fieldbus MAU tr ansmits a Ma nchester-encoded signal provided from a sta ndard MDS-MAU interface. T he output driv er makes it possible to design various signal circuits, which depend on the power requirements of your device. The slew rate of the signal can be controlled to minimize unnecessary radiation as specified in IEC/ISA standards. AMIS-49200 Fieldbus MAU has a built-in band-pass filter which makes it easy to design your own receiver. The receive block operates on a Ma nchester-encoded si gnal. It dec odes the sig nal and veri fies pr oper amp litude with a z ero-cross a nd c arrier detect c ircuit, respectively. Detected signals are then passed on to a controller with the standard MDS-MAU interface.

4.2 Power Supply Block

The power supply block contains four sub-blocks: 1. A shunt regulator - for establishing a supply voltage of VCC (typ. = 5V) used by the analog circuitry 2. A series regulator - for establishing a supply voltage of VDD (typ. = 3V) used for digital circuitry 3. Two low voltage detectors - for monitoring the two supply voltages 4. A bandgap voltage reference - which is used internally for generating a bias level for AC signals 4.2.1. Shunt Regulator The shunt regulator controls its sink current to the SHUNT pin so that the voltage applied to the SHSETIN pin is equal to VREF. The VCC input is d ivided by an internal network to provide a voltage equal to Vr ef at the S HSET pin. If SHSET and SHS ETIN pins are tied together, and VCC and SHUNT pins are connected to a power source of high impedance (e.g., current mirror circuit of signal driver), the Shunt regulator provides 5V power to itself and external circuits. A capacitor of 5 µF or larg er capacity is necessary to stabilize thi s regulator. It is possible to increase the V CC voltag e u p to 6.2V b y d ividing V CC with an e xternal network to su pply the a ppropriate volta ge t o SHSETIN pin. In this case, SHSET pin must be kept open. The output voltage is determined by the following equation: VCC = VREF × (1 + R1 / R2) Rsh 3 . 25 Rsh 25 mA ( Max ) VCC SHUNT SGNDSHSETIN SHSET Shunt Regulator ( Internal Configuration ) 9 6 7 A 6 System VCC Rsh 3.25Rsh 25 mA ( Max ) VCC SHUNT SGND SHSETINSHSET Shunt Regulator (External Configuration ) 9 6 7 System VCC N/C VREF VREF Cfb 50 pF 16 Meg Cfb 50 pF 16Meg Figure 4: Shunt Regulator 12 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet The SHUNT pin is normally connected to VCC. It is possible to insert a resister between VCC and SHUNT to measure the shunt current. Its value should be small enough to keep VDS (voltage between SHUNT pin and SGND pin) larger than 2.5V (i.e., resistor must be less than 100Ω.). Since the internal transistor can sink as much as 25mA, n o additional circuit is nec essary in most cases. Note that the drai n current must not e xceed 25mA because no protection is implemented for th e internal transistor. If you do not need the s hunt regulator, you should connect SHUNT and SHSETIN pins to GND and open SHSET pin. Then VCC must be supplied from another source. 4.2.2. Series Regulator The series regulator pr oduces a regulated voltage at the V O pin from V CC. If y ou connect SRAO and SRT R pins together, the intern al amplifier will regulate the i nput voltage at SR SETIN pin to e qual VREF. An intern al feedback signal is ge nerated to pro duce a v oltage equal to VREF at pin SRSET. If you connect SRSET and SRSETIN pins, the series regulator supplies 3V at pin VO. A capacitor of 5µF or larger capacity is necessary to stabilize this regulator. The capacitor is expected to have an ESR resistor for the circuit to be stable. If the capacitor is low, a series resistor with the cap load will help stabilize the circuit). SRSET SRTR SRAO SRSETIN VO May Supply VDD Series Regulator (External Configuration) 121415 N/C Rsr 1.54Rsr 20mA (Max) Cfb1 40pF VREF Cc2 20pF VCC CD SRSET SRTR SRAO SRSETIN VO May Supply VDD 121415 Rsr 1.54Rsr 20mA (Max) Cfb1 40pF VREF Cc2 20pF VCC CD Series Regulator (Internal Configuration) Figure 5: Series Regulator The supply current must not exceed 20mA because no current limiting is applied to the internal transistor. You can increase VO voltage up to 3.5V by dividing VO with an external network to supply the appropriate voltage to pin SRSETIN. In this case, pin SRSET must be kept open. The drain-source voltage of the i nternal transistor must be lar ger or equal to 2V. If this condition is not satisfied, you may need an external P-channel JFET to create the d esired low voltage-drop regulator. The output v oltage is det ermined by the fo llowing equation. VO = VREF × (1 + R4/R5) 4.2.3. Low Voltage Detectors Low voltage detectors are included to monitor supply voltages and generate “Power Fail” signals. The low voltage alarms are detected by sensing the voltage on pins SHSETIN and SRSETIN. These pins also provide feedback for the sh unt and series regulators. If the voltage on the SHSETIN pin is lower than the threshold, VTH9 (90 percent VREF), N_PFAIL1 goes low. Typically SHSETIN monitors the analog rail voltage VCC. If the volt age on the S RSETIN pin is lower than the thr eshold, VTH9, N_PFAIL2 goes low. T ypically SRSETIN monitors the digital rail voltage VDD. Both outputs are open drain, so a res istor will be required. If you do not use one of these pins, it should be connected to GND. You can also add capacitors to delay these signals. In this case, sink current must not exceed the maximum value. If you do not wish to use one of the low voltage detectors its corresponding output pin should be connected to GND. 13 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

4.3 Transmit Block

The transmit block contains four sub-blocks: 1. MDS-interface – decodes input signals to generate internal control signals. 2. Tri-level modulator – generates current signals used as inputs to the slew-rate controller. 3. Slew rate controller – converts current to three distinct VDRV voltage levels (VS, VH, VL). 4. Current drive amplifier – op amp designed to drive current drivers for 31.25kbps voltage-mode medium. 4.3.1. MDS-interface The MDS-inter face dec odes input sign als t o ge nerate int ernal contro l s ignals. T he POL pin, is used to sel ect the pol arity of T xE (transmit enable). The TxE and TxS (transmit signal) are the MDS-MAU interface signals. These three signals are CMOS logic signals powered by the VDD supply voltage. When POL is connected to GND, T xE is assumed to be active high (positive logic). Likewise, if POL is connected to VDD, TxE is assumed to be active low (negative logic). See Table 11 to see how MDS_CTRL Pin 26 can be used to control MD S interface operation. T he follo wing tab le shows th e res ulting VDRV output for the various comb inations of interf ace signals. Table 11: MDS-interface Logic POL TxE TxS VDRV Low Low High VS Low VH Low High High VL Low VH Low High VL Low High High High VS 4.3.2. Tri-level Modulator The tri-level modulator switches current signals into a summing node. The slew rate controller converts the current to a voltage signal, VDRV. The DC level of silence (VS) is nominally 2.5V. Transmission high (VH ) is nominally 2.9V and transmission low (VL) is nominally 2.1V, yielding an amplitude of 0.8V. VDRV R 20K 20R 400K CRT Tri-Level Modulator Slew Control VCC N_VL VMID 1.2K 80K 80K Active Low Active Low N_Vs 1.2K 1.2K Figure 8: Tri-level Modulator 15 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet 4.3.3. Slew Rate Controller Amplifier (A3), shown in the above figure, controls the slew rate. The amplifier converts the current signals from the tri-level modulator to a voltage signal, VDRV. It controls its slew rate with a capacitor (CRT) connected to the CRT pin. The waveform at the VDRV pin is symmetric and the fall/rise times are determined by the following equation: tF, tR = 2.0[µs] + 0.12 [µs/pF] × CRT The constant part comes fro m the intern al capacitor (not shown). It is recomme nded to make a g uard pattern o n your circuit board around the CRT pin and the hot side of CRT to avoid unnecessary interference. 4.3.4. Current Drive Amplifier The drive amp lifier is an o perational amplifier optimized to drive curr ent drivers fo r 31. 25kbps voltage-mode medium. Its inpu t and output signals are exposed to allow flexible design of the external driver. Note th at this amplifier cannot directly sink the necessary current from the medium. In the following drive circuit the current (IBUS) through the current-detect resister (RF) is determined by the following equation. IBUS = (1/RF) × (VDRV - VMID) × (RB/RA). A diode and/or a resister con nected to the emitter are necessary to s hift the DC l evel of CCOUT and to sup press the loop gain. The resistance value depends on your design (overall gain and emitter current). CCOUT CCINP CCINM Current Control Circuit VCC IBUS VDRVVmid RA RB RA Rf RB Figure 9: Current Control Circuit

4.4 Receive Block

The receive block contains three sub-blocks, which are internally connected: 1. A band pass filter – to filter the desired incoming communication signal. 2. Carrier detector – generates the RxA signal by detecting the signal amplitude. 3. Zero-cross detector generates the RxS signal by detecting the high/low transitions of the Manchester code. 16 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet 4.4.1. Band Pass Filter The band pass filter is a series connection of a h igh-pass and a low-pass filters each having two poles. Eac h filter is comprised of a voltage follower and on chip resisters, so only four external capacitors are necessary. The following figure shows an internal circuit and the connection of external capacitors. Cut-off frequency, fL, of the high-pass filter is determined by C1 and C2 while cut-off frequency, fH, of the low-pass filter is determined by C3 and C4. 212F1F C*C*R*R Lf π= R R LQ = =0.95 434F3F C*C*R*R Hf π= C C L *44.0Q = =0.95 The possib le r anges of f L a nd f H are 1k Hz ~ 10k Hz a nd 1 0kHz ~ 100kHz, res pectively. T he v alues in t he fo llowing fi gure a re recommended to obtain 1kHz and 47.6kHz cut-off frequencies. SIGIN RF2 270K RF1 75K RF3 20K RF4 54K HPF Vmid 1000pf FLTOUT FLT Bandpass Filter 31 30 VCC VCC C3=220pf To Detectors 1000pf C1C2 C4=47pf Signal Input Figure 10: Band Pass Filter 4.4.2. Receive Signal Detection The carrier detector generates the receive activity (RxA) signal by detecting the input signal amplitude. Minimum amplitude is 100mVp- p (TYP). A d elay, determined by the capacitor connected between the CCD pin and GND, is a dded to av oid detection of tra nsient noise. The recommended value of CCD is 100pF. The output can drive a CMOS input of VDD supply voltage. The zero-cross detector gen erates the recei ve signal (RxS) with minimum phase error (jitter) by detecting the transition between high and low l evels of the inc oming Ma nchester code. H ysteresis of + 40mV (T YP) is appl ied to av oid unnecessary s witching b y n oise. Once the carrier-detect goes active the hysteresis is removed and the switching point threshold is set to Vmid. The output can drive a CMOS input of VDD supply voltage. 17 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet Zero-Cross Detector Carrier Detector Vtrip = Vmid Vhyst = + 40mV VHi50 = Vmid + 50mV VLo50 = Vmid - 50mV RXS CCD RXA VCC VCC R (1Meg) C (60pF) Vmid VCC VHi50 VLo50 RxSig ZC Tript Pt CD_Output Level Convert VCC VDD Level Convert VDD Filtered received signal from Bandpass Filter Figure 11: Receive Signal Detectors

5.0 AMIS-49200 as Replacement for Yokogawa µSAA22Q

The AMIS-49200 is a near pin-for-pin compatible replacement for the Yokogawa µSAA22Q Fieldbus MAU. There are some differences between the two chips both in the internal operation, the required external connections and th e value (or e xistence) of some of the external components. These differences are small and those who used the µSAA22Q would most likely be able to use the AMIS-49200 in designs with only some component value changes.

5.1 Functional Differences Between the µSAA22Q and the AMIS-49200

5.1.1. Jabber Inhibit The AMIS-49200 does not implement the Jabber Inhibit function in the µSAA22Q. Typically the AMIS-4 9200 will be connected with a Link Controller chip such as the Yokogawa FIND1. This link controller has a Jabber Inhibit function so the absence of this function in the AMIS-49200 should not be a problem. As can be s een in T able 12, MDS_CT RL is onl y co nnected to grou nd if POL is con nected to VD D. See T able 1 for a detai led description of the interaction between MDS_CTRL and POL. In Table 12, the µSAA22Q recommends that the JAB/ signal (pin 39) be connected to ground if the signal is not used. On AMIS-49200, pin 39 must be connected to ground. 5.1.2. Low Power Mode The low power mode on the µSAA22Q allows the user to have a quiescent current draw of less than 10mA yet still communicate at the proper IEC 6 1158-2 sig nal l evels. Ver y f ew, if any, F ieldbus devices are ca pable of oper ating at such a low current lev el s o this capability was not included in the AMIS-49200. 18 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet The pins affected by this are 41, 42, and 43. If the low power mode is not being used on the µSAA22Q, these three pins are grounded. On the AMIS-49200 it is required that these pins be grounded.

5.2 Pin Differences Between the µSAA22Q and the AMIS-49200

Table 12: Pin Connection Differences Between the µSAA22Q and the AMIS-49200 µSAA22Q AMIS-49200 Pin Num Signal Name Recommended Connection Signal Name Required Connection

1 NC Ground VSS Ground

11 NC Ground VSS Ground

22 NC Ground VSS Ground

26 NC Ground MDS_CTRL Ground*

33 NC Ground VSS Ground

39 JAB/ Ground if not used VSS Ground

41 CJB 1 µf cap VSS Ground

42 VTX Ground VSS Ground

43 VSL Ground VSS Ground

• MDS_CTRL is only connected to ground if POL is connected to VDD. See Table 1 for a detailed description of the interaction between MDS_CTRL and POL. 19 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

5.3 External Circuitry

Figure 12 shows the external circuitry required to con nect the AMIS-49200 to an IEC 61158-2 conformant network. This schematic is the circuit that was use d to pass the F ieldbus F oundation Ph ysical La yer Conformance test as sp ecified in F ieldbus F oundation specification FF830, Rev 1.5. This circuit is similar but not identical to the circuit recommended by Yokogawa for the µSAA22Q. Figure 12: AMIS-49200 Reference Circuit Implementation Table 13 below lists the four external component values that need to be changed with using the AMIS-49200 in a circuit that previously used the µSAA22Q. Table 13: Passive External Component Value Differences Between the µSAA22Q and the AMIS-49200 Component µSAA22Q Value AMIS-49200 Value C1 100pf 150pf C3 100pf 47pf C4 470pf 220pf C8 10nf 1µf C1 connects to signal CCD (pin 32) and controls the carrier detect assert and dr op-out timing. Particular implementations may require that the val ue of C1 b e ch anged to accommodate rec eived sig nal level c hanges introduced by the ad dition of intrinsic s afety components added to the external circuitry. C3 and C4 are part of the receive filter and determine the band pass characteristics of the 20 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet receive filter. It is u nlikely that these would need to be changed. C8 is a noise filter for VMID . It is important that VMID ha ve as little noise as possible as it is used as a reference for many sub-circuits in the AMIS-49200. There is o ne other minor difference in the recommended external circuitry between the µSAA22Q and the AMIS-49200. Figure 13 shows the startup circuits recommended for the µSAA22Q and the AMIS-49200. The circuit shown for the AMIS-49200 is different from that shown for the µSAA22Q but either one will work. Both are current sources that turn on when power is applied to the H1 segment terminals so that the AMIS-49200 can turn on without any turn-on transients on the network. 1 k 100 k

5.1 V V Shunt

µSAA22Q Startup Circuit AMIS 49200 Startup Circuit Figure 13: Recommended Start-up Circuits

5.4 Active Components

Transistors Q1 – Q4 are ord inary small signal transistors. Diodes D1 and D2 are sim ilarly ordinary small signal diodes. Users desiring to replace a µSAA22Q with the AMIS-49200 in an existing design should be able to use whatever transistors and diodes were used with the µSAA22Q. For new designs, the specified transistors can be used or other devices may be chosen.

5.5 Alternative Designs

Some users of the Yokogawa µSAA22Q did not use the exact recommended external circuit for the media interface circuit (see Figure 12). Using the AMIS-49200 that did not follow the Yokogawa recommended external circuit may result in some compatibility problems. There are an almost infinite number of alternative designs and it is beyond the scope of this document to identify the possible designs and their possible compatibility problems.

5.6 Verification

All designs using the AMIS-49200 should re-run the entire physical layer conformance test as defined in Fieldbus Foundation document FF-830, FOUNDATION™ Specificati on 31.25 kbit/s Physical Layer Conformance Test. Board layout can alter the behavior of all circuit implementations, even designs that follow the recommended implementation. 21 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com

AMIS-49200 Fieldbus MAU Data Sheet

6.0 Appendix (A) – Manchester Encoding

All Fieldbus devices transmit the data onto the media as a Manchester-encoded baseband signal. With Manchester encoding, zeros and ones are represented by transitions that occur in the middle of the bit period (see below). For Foundation Fieldbus H1 and Profibus PA, the nominal bit time is 3 2µsec, with the transition occurring at 16µsec. The Manchester encoding rules h ave been extended to include two additional symbols, non-data plus (N+) and non-data minus (N-). The symbol encoding rules are shown below. Logical "0" T "N+" T "N-" T Logical "1" T 32 usec Figure 14: Manchester Encoding

7.0 Company or Product Inquiries

For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com North America Tel: +1.208.233.4690 Fax: +1.208.234.6795 Europe 22 AMI Semiconductor – Jan. 07, M-20532-003 www.amis.com Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2007 AMI Semiconductor, Inc.