PI0512WS AMI | Alldatasheet

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PI0512WS Page 1 of 8 – July 26, 2001

Description

Peripheral Imaging Corporation's WS series is family of self -scanning photodiode solid-state linear imaging arrays. These photodiode sensors employ PIC ’s proprietary CMOS Image Sensing Technology to integrate the sensors into single mono lithic chip. These sensors are optimally designed for applications in spectroscopy. Accord ingly, these sensors contain a linear array of photodiodes with an optimized geometrical as pect ratio (50- mm aperture pitch x 2500- mm aperture width) for helping to maintain mechanical stabili ty in spectroscopic instruments and for providing their light-capturing ability. The family of sensor consists of active photodiode arrays of different number of pixels, 256 and 512. Figure 1 . Pinout configuration. PI0512WS 512-Pixel 50- mm-Pitch Wide Aperture Spectroscopic Photodiode Array Engineering Data Sheet 650 N. Mary Ave. Sunnyvale, California, 94085 Phone: 408-962-1913 Fax: 408-962-1998 Peripheral Imaging Corporation

– July 26, 2001 The WS series devices are mounted in 22-pin ceramic side-bra zed dual-in-line packages that will insert in a standard DIP socket. A diagram of the pack age and its pinout configuration is seen in Figure 1.

Features

  • High saturation capacitance (60 pF ) for wide dynamic range.
  • Wide spectral response (180-1000) for UV and IR response.
  • PN junction photodiodes highly resistive to UV damage.
  • Low dark current.
  • Integration time from 0.52 ms to 0.6 seconds at room tempe rature.
  • Longer integration time extended to hours by cooling.
  • High linearity.
  • Low power dissipation.
  • Geometrical structure to enhance stability and registratio n.
  • Standard 22-lead dual-in-line integrated-circuit package. Sensor Characteristics The Peripheral Imaging Corporation's self-scanned photodiode s are on 50- m m center-to-center spacing. Hence, their line density 20 diodes/mm and accordi ngly the overall die lengths of the different arrays vary with the number of photodiodes. For e xample, the 256-pixel array is 12.8-mm long and the 512 pixel array is 25.6-mm long. In addition, each array has four additional dummy, non- imaging photodiodes with two on each side. The height of the sensors is 2500 µ m. Accordingly, these slit-like apertures make these sensors de sirable for coupling to monochromators and spectrographs. Figure 2 Geometry and layout of photodiode pixels.

PI0512WS Page 5 of 8 – July 26, 2001 I/O Pins Although the PI0512WS package has 22 pins as shown in Figure 1, there are only 6 functionally active I/O pins in addition to the supply and b ias pins as shown in Figure 5. Table 1 defines the I/O acronyms, provides their full names and d escrib es their functions. In essence, only two clocks, CLK and START, are required for co ntrolling the timing of the sensor's video readout if the internal reset circuitry is no t used. However, if the internal reset circuitry is used, a third clock signal, RESET, is required. The remaining I/O descriptions are for the video signal output, the end-of-scan signal, and the bias and supply voltage. These I/Os are listed with their acronym designators and functiona l descriptions in the following Table 1. Table 1 . Symbols and functions and I/O pins. Symbol Function and Description VSS Ground. VDD +5.0 Volts. START Start Pulse: Input to start the line scan. CLK Clock Pulse: Input to clock the shift register. EOS End Of Scan: Output from the shift register to indicate the completion of one line scan. AVIDEO Active Video Line: Charge output from the photodiodes pixels . RESET Reset Control Gate: Pulsing this input will reset the video line to the reset bias. BIAS Reset Bias Supply: Input bias reference resetting the video line.

– July 26, 2001 Clock and Voltage Requirements Clocks requirements are relatively simple. As it was indicated in Figure 5 and Table 1, there are only three input signals that require clocked inputs. T hey are CLK, the clock for the shift register, START, the shift register start pulse, and RESET, the reset control gate. However, in certain applications where the internal reset circuitry is u nused, RESET can be tied to ground. Figure 6 Timing diagram. Table 2 . Symbol definitions and timing specifications for timing d iagram. Item Symbol Min Typical Max Units Clock cycle time to m s Clock pulse width tw m s Clock duty cycle 20 Prohibit crossing time of Start Pulse tprh ns Data setup time tds ns Data hold time tdh 100 ns End Of Scan delay tdeo 300 ns End Of Scan off tdee 300 ns Signal delay time tsd ns Signal settling time tsh 500 ns The timing specifications and the symbol definition for Figu re 6 are listed in Table 2. The control clock amplitudes for I/Os are compatible with the 5- Volt CMOS devices.

– July 26, 2001 Recommended Operating Conditions at Room Temperature Table 3 lists the recommended operational conditions. Table 3. Recommended operating conditions at room temperature. Parameters Symbol Min. Typical Max. Units Power supply VDD 4.5 5.0 5.0 Volts Input clock pulses high level 1 Vih VDD – 0.8 VDD VDD Volts Input clock pulse low level 1 Vil 0.0 0.0 0.8 Volts Video output bias levels (dark) Vbias 0.0 0.5 2.5 Volts Clock frequency 2 Fclk 100 1000 kHz Clock pulse duty cycle 20 Integration time 3 Tint 0.52 600 ms Notes: (1) Applies to all control-clock inputs. (2) The minimum clock frequency must be consistent with the inte gration time as indicated in note (3). (3) Integration time is specified at room temperature such that the maximum dark current charge build up in each pixel is less than 10% of the typical saturation charge. Accordingly, it can be as short as 0.52 ms or as long as 0.6 seconds at room temperature . Longer integration times are possible by cooling the device. Package Dimensions Note: Dimensions are in inches except where millimeters (mm ) are indicated.

Table 4 lists the electro-optical characteristics of PI0512W S sensor chip at 25 o C. Table 4. Electro-optical characteristics. photon at a given wavelength. (2) At wavelength of 575 nm (yellow-green) and with no window. (5) From 250-1000 nm, responsivity ≥ 20% of its peak value. by implication or otherwise under any patent or patent rights of AMIS.