PI0000HSN AMI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

  • Selectable saturation charge capacities. 65-pC capacity for wider dynamic range. 25-pC for lower noise readout.
  • Wide spectral response (180 – 1000 nm) for UV and IR response.
  • NP junction photodiodes with superior resistance to UV damage.
  • Low dark current.
  • Integration time up to 11 seconds at room te m - perature.
  • Integration time extended to hours by cooling.
  • Anti-blooming circuitry.
  • High linearity.
  • Low power dissipation (less than 1 mW).
  • Geometrical structure for enhanced stability and registration.
  • Standard 22-lead dual-in-line IC package.

Figure 1. Pinout configuration.

PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Page 2 of 8 March 13, 2002 Figure 2 . Geometry and layout of photodiode pixels. During normal operation, the photons incident in or near the NP photodiode junction generate free charges that are collected and stored on the junction's depletion capacitance. The number of collected charges is proportional to the light exposure. Figure 3 shows the stored signal charge as function of light exposure at a wavelength of 575 nm. The exposure is the product of the light intensity in nW/cm 2 and integration time in seconds. The charge accumulates linearly until reac h - ing the saturation charge, and the corresponding exposure is the saturation exposure. There are two saturation limits which are described in the Selectable Charge Capacity se c tion below. The responsivity may be calculated as the saturation charge divided by saturation exposure. The predicted typical responsivity of a photodiode is 1.5 × 10 -4 C/J/cm 2 at 575 nm. Figure 4 shows the predicted responsivity of the photodiodes as a function of wavelength. Figure 3 . Stored signal charge as function of exposure at a wavelength of 575 nm.

2 Dummy

25 µ m 2500 µ m 0 100 200 300 400 500 E xpo sure (nJ/cm 2 ) Output Charge (pC) saturation w/o cap saturation with cap

PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet Page 4 of 8 March 13, 2002 I/O Pins Besides the VSS and VDD supply pins, there are 9 functionally active I/O pins. Only two clocks, CLK and START, are required for controlling the timing of the sensor's video readout. One additional digital input, ADDCAP controls the bank of capacitors as described in the Selectable Charge Capacity section above. The digital output, EOS, marks the end of the line-scan. The charge output pin, QOUT, is typically connected to a charge-integrating amplifier that is biased to Vbias (see Recommended Operating Conditions section below). For normal anti-blooming operation, the ABG requires a 0.1- µ F capacitor connected to VSS and the ABD is also biased to Vbias. Each temperature diode is o p erated with a small constant current that forward- biases its PN junction. By measuring the forward-bias voltage, one can track the silicon die temperature. The temperature diodes may be disabled by connecting their anodes to VSS. These I/Os are listed with their acronym designators and functional descriptions in the following Table 1. Table 1 . Symbols and functions and I/O pins. Symbol Function and Description VSS Ground. VDD +5.0 Volts. START Start Pulse: Input to start the line scan. CLK Clock Pulse: Input to clock the shift register. ADDCAP Add Capacitors: Input that selects the bank of capacitors t o increase charge capacity. EOS End Of Scan: Output from the shift register to indicate the completion of one line scan. QOUT Video Charge Output: Output from the photodiodes pixels. ABG Anti-Blooming Gate: Self-biased gate for setting anti-bloom ing level. Requires 0.1- µ F connected to VSS. ABD Anti-Blooming Drain: Bias for anti-blooming drain. Set to Vbias. TD1 Temperature Diode 1: Anode of temperature diode 1. TD2 Temperature Diode 2: Anode of temperature diode 2. NC No Connection Figure 5 . Simplified circuit diagram of a HSN photodiode array. The diagram does not include the capacitor bank and the anti-blooming circuitry. CLK ART TD1 SHIFT REGISTER EOS QOUT TD2 VSS Dummy 1 Dummy 2 Dummy 4 Dummy 3 Pixel 1 Pixel 2 Pixel n-1 Pixel n

the symbol definition for Figure 6 are listed in Table 2. with the 5-Volt CMOS devices. Table 2. Symbol definitions and timing specifications for timing diag ram.

The following table lists the recommended operating conditio ns. Table 3. Recommended operating conditions at 25 ° C.

  1. Applies to all control-clock inputs.
  2. Integration time is specified at room temperature such that the maximum dark current charge build up in each pixel is

quency must be chosen so that the shift register completes i ts operation within the desired integration time.

The following table lists the electro-optical characteristic s. Table 4. Electro-optical characteristics at 25 ° C.

  1. Fill factor, quantum efficiency, and responsivity are relate d by the equation R = (q e λ/hc) .QE .FF .A, where q e is the
  2. At wavelength of 575 nm (yellow-green) and with no window.
  3. Measured at 50% Vsat with an incandescent tungsten lamp filt ered with an Schott KG -1 hea t-absorbing filter.
  4. Saturation charge specified for a video output bias of 4.5 v olts.
  5. Max dark leakage ≤ 1.5 x average dark leakage measured with an integration per iod of 500 ms at 25 o C.
  6. From 250-1000 nm, responsivity ≥ 20% of its peak value.

PI0256HSN, PI0512HSN, PI1024HSN Engineering Data Sheet AMI Semiconductor, Inc. www.amis.com 650 N. Mary Ave. • Sunnyvale • CA 95085 408-962-1913 Page 8 of 8 March 13, 2002 Package Dimensions The following figure provides the package dimensions. Device A B PI0256HSN 1.080 ± 0.010 6.4 mm PI0512HSN 1.080 ± 0.010 12.8 mm PI01024HSN 1.600 ± 0.010 25.6 mm Figure 7 . Package dimensions. Note: Dimensions are in inches except where millimeters (mm) are indicated. ©2001-2002 AMI Semiconductor. Printed in USA. All rights reserved. Specifications are subject to change without notice. Contents may not be reproduced in whole or in part without the express prior written permission of AMIS. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by AMIS for its use nor for any infringement of patents or other rights granted by implication or otherwise under any patent or patent rights of AMIS. 0.100+/-0.005 1.00+/-0.005 0.054+/-0.006 0.026+/-0.006 Pin 1 A Sensing Area B 2.5 mm Silicon Chip 0.394+/-0.010 0.148 +/-0.010 0.148 +/-0.010 0.080+/-0.008 0.400+/-0.010 [AT STAND OFF]