PD128G80VI

AM29PDL128G AMD | Alldatasheet

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Publication Number 25685 Revision B Amendment ++4 Issue Date October 13, 2004 July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM.” To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am29PDL128G Data Sheet Publication Number 25685 Revision B Amendment +4 Issue Date October 13, 2004

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This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25685 Rev: B Amendment/+4 Issue Date: October 28, 2004 Am29PDL128G 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ 128Mbit Page Mode device — Word (16-bit) or double word (32-bit) mode selectable via WORD# input — Page size of 8 words/4 double words: Fast page read access from random locations within the page „ Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications „ Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations „ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Organized as two 16 Mbit banks (Bank 1 & 4) and two 48 Mbit banks (Bank 2 & 3) „ VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on the device is determined by the voltage on the VIO pin „ SecSi (Secured Silicon) Sector region — 128 words (64 double words) accessible through a command sequence „ Both top and bottom boot blocks in one device „ Manufactured on 0.17 µm process technology „ 20-year data retention at 125°C „ Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS „ High Performance — Page access times as fast as 25 ns — Random access times as fast as 70 ns „ Power consumption (typical values at 10 MHz) — 38 mA active read current — 17 mA program/erase current — 1.5 µA typical standby mode current SOFTWARE FEATURES „ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families „ CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices „ Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank „ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES „ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion „ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data „ WP# (Write Protect) input —A t V IL, protects the two top and two bottom sectors, regardless of sector protect/unprotect status —A t V IH, allows removal of sector protection — An internal pull up to Vcc is provided „ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level „ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password „ ACC (Acceleration) input provides faster programming times in a factory setting „ Package options — 80-ball Fortified BGA Refer to AMD’s Website (www.amd.com) for the latest information.

October 28, 2004 Am29PDL128G 3 PRELIMINARY GENERAL DESCRIPTION The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords or 4 M double words (One word is equal to two bytes). The device is offered in an 80-ball Fortified BGA package. The word-wide data (x16) appears on DQ15-DQ0; the double word mode data (x32) appears on DQ31-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access times of 25 and 30 ns, with corresponding random access times of 70 and 80 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. To eliminate bus contention the de- vice has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with 2 simultaneous operations operating at any one time). This releases the system from waiting for the comple- tion of a program or erase operation, greatly improving sys- tem performance. The device can be organized in both top and bottom sector configurations (see Ta ble 1). Page Mode Features The device is AC timing, input/output, and package compat- ible with 8 Mbit x16 page mode mask ROM. The page size is 8 words or 4 double words. After initial page access is accomplished, the page mode op- eration provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Bank/Sector Sizes Bank Number of Sectors Sector Size (Word/Dbl. Word) Bank Size 1 84 / 2 16 Mbit31 32/16 2 96 32/16 48 Mbit 3 96 32/16 48 Mbit 4 84 / 2 16 Mbit31 32/16

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Figure 1. In-System Sector Protection/Sector Unprotection Algorithms

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Note: See “AC Characteristics” on page 53 for full specifications. BLOCK DIAGRAM Notes: 1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address r ange is A21-A-1. 2. RY/BY# is an open drain output. Part Number Am29PDL128G Speed Option Voltage Range: VCC = 3.0–3.6 V 70R Voltage Range: VCC = 2.7–3.6 V 70 80 90 Max Access Time, ns (tACC)7 0 8 0 9 0 Max CE# Access, ns (tCE)7 0 8 0 9 0 Max Page Access, ns (tPACC)2 5 3 0 3 5 Max OE# Access, ns (tOE)2 5 3 0 4 0 VCC VSS State Control Command Register PGM Voltage Generator VCC Detector Timer Erase Voltage Generator Input/Output Buffers Sector Switches Chip Enable Output Enable Logic Y-Gating Cell Matrix Address Latch Y-Decoder X-Decoder Data Latch RESET# RY/BY# (Note 2) STB STB A21–A2 A1–A0 (A-1) A3, A4 CE# OE# WE# DQ31–DQ0 VIO

October 28, 2004 Am29PDL128G 7 PRELIMINARY SIMULTANEOUS READ/WRITE BLOCK DIAGRAM VCC VSS Bank 1 Address Bank 2 Address A21–A0 RESET# WE# CE# DQ0–DQ15 DW/W# WP# ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# DW/W# DQ31–DQ0 Status Control A21–A0 A21–A0 A21–A0A21–A0 DQ31–DQ0 DQ31–DQ0 DQ31–DQ0 DQ31–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

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Special Handling Instructions for BGA Packages Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. B2 D2 E2 F2 G2 H2 J2 B3 D3 E3 F3 G3 H3 J3 B4 D4 E4 F4 G4 H4 J4 B5 D5 E5 F5 G5 H5 J5 B6 D6 E6 F6 G6 H6 J6 B7 D7 E7 F7 G7 H7 J7 DQ24 A19VIODQ26DQ13VSSDQ15CE# DQ8 A16DQ25DQ27DQ12DQ14DQ31/A-1A20 A14 A13DQ10RFUACCDQ29WE#WP# A12 RFUVSSRFURESET#DQ18A1A0 VSS A10DQ22DQ20DQ4VSSDQ16A3 DQ23 A7 A17 A15 RFU RFU A11 A9DQ6DQ21DQ3VIODQ1VCC B1 D1 E1 F1 G1 H1 J1 DQ7 A6VIODQ5DQ19DQ2DQ17DQ0 B8 D8 WORD# A21 RFU RY/BY# C8 E8 F8 G8 H8 J8 DQ9 V CC A18VSSDQ11DQ28VIODQ30VSS OE# 80-Ball Fortified BGA Top View, Balls Facing Down

October 28, 2004 Am29PDL128G 9 PRELIMINARY PIN DESCRIPTION A21–A0 = 22 Addresses DQ30–DQ0 = 31 Data Inputs/Outputs DQ31/A-1 = DQ31 (Data Input/Output, double word mode), A-1 (LSB Address In- put, word mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP# = Hardware Write Protect Input ACC = Acceleration Input RESET# = Hardware Reset Pin, Active Low WORD# = Word Enable Input At V IL, selects 16-bit mode, At VIH, selects 32-bit mode RY/BY# = Ready/Busy Output VCC = 3.0 Volt-only Single Power Supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer Power Supply VSS = Device Ground NC = Pin Not Connected Internally RFU = Reserved for Future Use LOGIC SYMBOL 32 or 16 DQ31–DQ0 (A-1) A21–A0 CE# OE# WE# RESET# WORD# RY/BY#ACC WP# VIO

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Am29PDL128G 70 PE I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) E = Extended (–55 °C to +125°C) F = Industrial (–40 °C to +85°C) for Pb-free Package K = Extended (-55C to +125C) for Pb-free Package PACKAGE TYPE PE = 80-Ball Fortified Ball Grid Array ( fBGA) 1 mm pitch, 15 x 10 mm package (LAB080) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29PDL128G

128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for BGA Packages Order Number Package Marking Am29PDL128G70R PEF PEI PD128G70R I,FAm29PDL128G70 PD128G70V Am29PDL128G80 PEI, PEE, PEF , PEK PD128G80V I, E F, KAm29PDL128G90 PD128G90V

register serve as inputs to the internal state machine. operations in further detail. Table 1. Am29PDL128G Device Bus Operations

1. Addresses are A21–A0 in double word mode (WORD# = V IH), A21–A-1 in word mode (WORD# = V IL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector Protection”

pins operate in the word or double word configuration. (LSB) function, which is named A-1. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V X X High-Z High-Z High-Z

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mining the specific word/double word within that page. to select the specific word, within that page. Table 2. Page Select, Double Word Mode Table 3. Page Select, Word Mode bank addresses (A21–A19) with zero latency. Table 4. Bank Select ration” for more information. the address bits required to uniquely select a bank. bles and timing diagrams for write operations.

October 28, 2004 Am29PDL128G 13 PRELIMINARY Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that V HH must not be asserted on ACC for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. See “Autoselect Mode” on page 21 and “Autoselect Command Sequence” on page 35 for more information. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note: This is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (t CE) for read access when the de- vice is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at V IH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteris- tics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V , the device draws CMOS standby current (ICC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby cur- rent is greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to tables in AC Characteristics for RESET# pa- rameters and to Figure 13 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the high impedance state.

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Table 5. Sector Address Table (Sheet 1 of 7)

Table 5. Sector Address Table (Sheet 2 of 7)

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Table 5. Sector Address Table (Sheet 3 of 7)

Table 5. Sector Address Table (Sheet 4 of 7)

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Table 5. Sector Address Table (Sheet 5 of 7)

Table 5. Sector Address Table (Sheet 6 of 7)

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select a sector; address bits A21:A19 uniquely select a bank. Table 5. Sector Address Table (Sheet 7 of 7)

Table 6. SecSi ™ Sector Addresses accessed in-system through the command register. read the corresponding identifier code on DQ7–DQ0. mand sequence is illustrated in Table 14 and Table 16. Sequence” for more information. Table 7. Autoselect Codes (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences.

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Table 8. Sector Block Addresses for Pr otection/Unprotection (Sheet 1 of 3)

Table 8. Sector Block Addresses for Pr otection/Unprotection (Sheet 2 of 3)

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the old 12 V controlled protection method. operations in sectors 0, 1, 268, and 269. The device is shipped with all sectors unprotected. AMD representative for details. Table 8. Sector Block Addresses for Pr otection/Unprotection (Sheet 3 of 3)

October 28, 2004 Am29PDL128G 25 PRELIMINARY It is possible to determine whether a sector is pro- tected or unprotected. See “Autoselect Mode” on page 21 for details. Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three dif- ferent sector protection states: „ Persistently Locked —A sector is protected and cannot change. „ Dynamically Locked—The sector is protected and can change by a simple command „ Unlocked—The sector is unprotected and can change by a simple command To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where in- dividual PPBs are programmable. It is the responsibil- ity of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no hardware mechanism to prevent sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to “1”, the PPBs cannot change. When cleared (“0”), the PPBs are change- able. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is de- faulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs are set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. The states are called dynamic because it is very easy to switch back and forth between the protected and un- protected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain the state across power cycles because the PPBs are Non-Vola- tile. Individual PPBs are set with a command, but all must be cleared as a group through a complex se- quence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protec- tion. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to “1”. Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into the current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PBBs during system operation. The WP# protects the top two and bottom two sectors when at V IL. These sectors generally hold system boot code. The WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initializa- tion. It is possible to have sectors that have been persis- tently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unpro- tected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and un- protected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again locks the PPBs, and the de- vice operates normally again.

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Table 9. Sector Protection Schemes whether or not the sector is protected or unprotected. DYB/PPB/PPB lock verify command to the device. place the device in password protection mode. state, rather than cleared to the unlocked state. ing a unique 64-bit Password to the device. identical to the Persistent Sector Protection method. all possible combinations to crack the password.

000 Unprotected—PPB and DYB are

001 Unprotected—PPB not

October 28, 2004 Am29PDL128G 27 PRELIMINARY 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. It also disables all further commands to the pass- word region. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there is no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify com- mand from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using V ID. This function is provided by the WP# pin and over- rides the previously discussed Sector Protection/Un- protection method. If the system asserts V IL on the WP# pin, the device disables program and erase functions in sectors 0, 1, 268, and 269 independent of whether it was previously protected or unprotected using “High Voltage Sector Protection” on page 27. If the system asserts VIH on the WP# pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector pro- tection or unprotection for these sectors depends on whether the sectors were previously protected or un- protected using “High Voltage Sector Protection” on page 27. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset. The ONL Y means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persis- tent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The proce- dure requires high voltage (V ID) to be placed on the RESET# pin. Refer to Table 1 for details on this proce- dure. Note: For sector unprotect, all unprotected sec- tors must first be protected prior to the first sector write cycle.

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Note:These algorithms are valid only in Persistent Sector Protection mode, and are not valid in Password Protection Mode.

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gion without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3. SecSi Sector protection bit is programmed.

1. Enter the SecSi Sector by issuing the SecSi Sector
2. Program the 64-bit password by issuing the Pass-
3. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

1. Program the SecSi Sector, excluding bytes 0–7.
2. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

1. Exit the SecSi Sector by issuing the SecSi Sector

Note: Step 4 may be performed prior to Step 2.

1. Enter the SecSi Sector by issuing the SecSi Sector
2. Program the entire SecSi Sector, including the first

eight bytes contain the 64-bit password.

1. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

1. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

1. Exit the SecSi Sector by issuing the SecSi Sector

Note: Step 4 may be performed prior to Step 3. Figure 3. SecSi Sector Protect Verify

or WE# do not initiate a write cycle. cally reset to the read mode on power-up. terfaces used for long-term compatibility. return the device to reading array data. Table 10. CFI Query Identification String

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Table 11. System Interface String

Table 12. Device Geometry Definition

34 Am29PDL128G October 28, 2004

Table 13. Primary Vendor-Specific Extended Query

October 28, 2004 Am29PDL128G 35 PRELIMINARY COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Tables 14, 15, 16, and 17 define the valid register command sequences. Writing incorrect ad- dress and data values or writing them in the im- proper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. See “AC Characteristics” on page 53 for timing di- agrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See “Erase Suspend/Erase Resume Commands” on page 38 for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also See “Requirements for Reading Array Data” on page 11 in the Device Bus Operations section for more information. See “Read-Only Operations” table for the read parameters, and Figure 12 shows the tim- ing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command cannot be written while the device is actively program- ming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 14 and Table 16 show the address and data re- quirements. To determine sector protection informa- tion, the system must write to the appropriate bank address (BA) and sector address (SA). Table 5 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word/four double word electronic serial number (ESN). The system can ac-

36 Am29PDL128G October 28, 2004

cess the SecSi Sector region by issuing the three-cy- cle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sec- tor command sequence. The Exit SecSi Sector com- mand sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or em- bedded Erase algorithm. Table 15 and Table 17 show the address and data requirements for both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further information. Note: The ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Double Word/Word Program Command Sequence The system may program the device by double word or word, depending on the state of the WORD# pin. Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 14 and Table 16 show the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” on page 46 for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note: A hard- ware reset immediately terminates the program operation. Note: the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] op- eration is in progress. The program command se- quence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read shows that the data is still “0.” Only erase operations convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 14 and Table 16 show the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 14). The device offers accelerated program operations through the ACC pin. When the system asserts V HH on the ACC pin, the device automatically enters the Un- lock Bypass mode. The system may then write the two-cycle Unlock Bypass program command se- quence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note: The ACC pin must not be at VHH any operation other than accel- erated programming, or device damage may result. In addition, the ACC pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. Figure 3 illustrates the algorithm for the program oper- ation. See the table, “Erase and Program Operations” on page 57 in “AC Characteristics” for parameters, and Figure 16 for timing diagrams.

38 Am29PDL128G October 28, 2004

ters, and Figure 18 for timing diagrams.1. See Table 14 and Table 14 for erase command sequence.

1. See the section on DQ3 for information on the sector erase

Figure 5. Erase Operation period during the sector erase command sequence. writing the Erase suspend command. if a sector is actively erasing or is erase-suspended. pend mode, and is ready for another valid operation. Command Sequence” on page 35 for details. pended bank is required when writing this command. Further writes of the Resume command are ignored. the chip has resumed erasing.

October 28, 2004 Am29PDL128G 39 PRELIMINARY password program command (38h) and the program address/data for each portion of the password when programming. There is no special addressing order re- quired for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location returns the programming status. Once pro- gramming is complete, the user must issue a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set to prevent verification. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell re- maining as a “0”. The password is all F’s when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the SecSi sec- tor is enabled. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device al- ways drives all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device does not op- erate in Simultaneous Operation when the Password Verify command is executed. Only the password is re- turned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Per- sistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Password Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Pass- word Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Com- mand should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Persistent Sector Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as pro- grammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the V CC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. The SecSi Sector Protection Bit Program command is permitted if the SecSi sector is enabled. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. In the Persistent Sector Protec- tion mode, exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the SecSi sector is enabled.

40 Am29PDL128G October 28, 2004

The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A21–A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. The DYB Write command is permitted if the SecSi sec- tor is enabled. Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command is ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the de- vice to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data bus and 4 times for a x16 data bus. Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the device is busy. Approximately 2 µs is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when read), the Password Unlock com- mand is issued again, only this time with the next part of the password. If WORD# = 1, the second Password Unlock command is the final command before the PPB Lock Bit is cleared (assuming a valid password). If WORD# = 0, this is the fourth Password Unlock com- mand. In x16 mode, four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY# signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock com- mands (2 for x32 bus and 4 for x16 bus), the order, and when to read the PPB Lock bit to confirm suc- cessful password unlock The Password Unlock command is permitted if the SecSi sector is enabled. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk erased with the other PPBs). The specific sector address (A21–A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command does not execute and the command times-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been pro- grammed with margin. If the PPB has been pro- grammed without margin, the program command should be reissued to improve the program margin. The PPB Program command is permitted if the SecSi sector is enabled. The PPB Program command does not follow the Embedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set, the ALL PPB Erase command does not execute and the command times-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased with- out margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-era- sure may occur making it difficult to program the PPB at a later time. Note: The total number of PPB pro- gram/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the SecSi sector is enabled. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device clears the DYBs. The bank address is latched when the com- mand is written.

October 28, 2004 Am29PDL128G 41 PRELIMINARY The DYB Write command is permitted if the SecSi sec- tor is enabled. PPB Lock Bit Set Command The PPB Lock Bit set command is used for setting the PPB lock bit. During Password Protection mode, only the Password Unlock command can reset the PPB Lock Bit to 0. Otherwise, a power-up or hardware reset resets the PPB Lock Bit to 0. PPB Lock Bit Status Command The programming of the PPB Lock Bit can be verified by writing a PPB Lock Bit status verify command to the device. Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note: There is no single command to independently verify the programming of a DYB or PPB for a given sector group.

42 Am29PDL128G October 28, 2004

WE# or CE# pulse, whichever happens later. on rising edge of WE# or CE# pulse, whichever happens first. RD = Read Data (DQ15:DQ0) from location RA. write data. Data latched on rising edge of WE#.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in the able denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. No unlock or command cycles required when bank is reading
6. Reset command is required to return to reading array (or to

providing status information).

1. Cycle 4 of autoselect command sequence is a read cycle. See
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector group and 01h for a
4. Device ID must be read across cycles 4, 5, and 6.
5. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode. erase operation, and requires bank address.

1. Program/Erase Resume command valid only during Erase

Suspend mode, and requires bank address.

1. Command valid when device is ready to read array data or when

device is in autoselect mode.

1. ACC must be at VID during entire operation of command.
2. Unlock Bypass Entry command is required prior to any Unlock

Table 14. Memory Array Command Definitions (x32 Mode)

SSA = SecSi Sector Address (A6:A0) is (0011010). PD[1:0] = Program Data. Password written in 2 portions. PWA = Password Address. A0 selects portion of password. PWD = Password Data being verified. RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock bit status. A21:A11 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in the able denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. Reset command returns device to reading array.
6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate

6, entire command sequence must be issued and verified again.

1. Data is latched on rising edge of WE#.
2. Entire command sequence must be executed for each portion of
3. Command sequence returns FFh if PPMLB is set.
4. Password is written over four consecutive cycles at addresses
5. A 2 µs timeout is required between any two portions of password.
6. A 100 µs timeout is required between cycles 4 and 5.
7. A 1.2 ms timeout is required between cycles 4 and 5.
8. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
9. DQ1 = 1 if PPB locked, 0 if unlocked.
10. For all other parts that use the Persistent Protection Bit (excluding

Table 15. Sector Protection Co mmand Definitions (x32 Mode)

44 Am29PDL128G October 28, 2004

WE# or CE# pulse, whichever happens later. on rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (A21:A-1). RD = Read Data (DQ15:DQ0) from location RA. write data. Data latched on rising edge of WE#.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in the table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. No unlock or command cycles required when bank is reading
6. Reset command is required to return to reading array (or to

providing status information).

1. Cycle 4 of auto command sequence is a read cycle. See
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector group and 01h for a
4. Device ID must be read across cycles 4, 5, and 6.
5. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode. erase operation, and requires bank address.

1. Program/Erase Resume command valid only during Erase

Suspend mode, and requires bank address.

1. Command is valid when device is ready to read array data or

when device is in autoselect mode.

1. ACC must be at V ID during entire operation of this command.
2. Unlock Bypass Entry command required prior to any Unlock

Table 16. Memory Array Command Definitions (x16 Mode)

SSA = SecSi Sector Address (A6:A0) is (0011010). PD[3:0] = Program Data. Password written as four 16-bit sections. PWA = Password Address. A0:A-1 selects portion of password. PWD = Password Data being verified. RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock bit status. A21:A11 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in the table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. Reset command returns device to reading array.
6. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate

cycle 6, the program command must be issued and verified again.

1. Data is latched on rising edge of WE#.
2. Entire command sequence must be executed for each portion of
3. Command sequence returns FFh if PPMLB is set.
4. Password is written over four consecutive cycles, at addresses
5. A 2 µs timeout is required between any two portions of password.
6. A 100 µs timeout is required between cycles 4 and 5.
7. A 1.2 ms timeout is required between cycles 4 and 5.
8. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
9. DQ1 = 1 if PPB locked, 0 if unlocked.
10. For all other parts that use the Persistent Protection Bit (excluding

Table 17. Sector Protection Co mmand Definitions (x16 Mode)

46 Am29PDL128G October 28, 2004

WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. from providing status information to valid data on DQ7. Table 18 shows the outputs for Data# Polling on DQ7. Figure 6. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

48 Am29PDL128G October 28, 2004

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare out- puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and “DQ2: Toggle Bit II” on page 48 explains the algorithm. Figure 21 shows the toggle bit timing dia- gram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ31–DQ0 (or DQ15–DQ0 for word mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ31–DQ0 (or DQ15–DQ0 for word mode) on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see “DQ5: Exceeded Timing Limits” on page 48). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset com- mand to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. Also see “Sector Erase Command Se- quence” on page 37. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last com- mand might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits.

Table 18. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to “DQ5: Exceeded Timing Limits” on page 48 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

50 Am29PDL128G October 28, 2004

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V .

1. Minimum DC input voltage on pins A9, OE#, RESET#,

which may overshoot to +14.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 8. Maximum Negative Figure 9. Maximum Positive functionality of the device is guaranteed.

October 28, 2004 Am29PDL128G 51 PRELIMINARY DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 4mA/MHz, with OE# at V IH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current VCC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA ICC1 VCC Active Inter-page Read Current, Word/Double Word Modes (Notes 1, 2) CE# = V IL, OE# = VIH 1 MHz 4.5 9 mA5 MHz 20 40

10 MHz 38 45

VCC Active Intra-page Read Current, Word/Double Word Modes (Note 2) CE# = VIL, OE# = VIH

1 MHz 1 18

5 MHz 3.5 45 ICC2 VCC Active Write Current (Notes 2, 3)C E # = VIL, OE# = VIH, WE# = VIL 17 35 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 1.5 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 1.5 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 1.5 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 30 45 mA Dbl. Word 30 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Word 21 45 mA Dbl. Word 21 45 ICC8 VCC Active Program-While-Erase- Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V IO V VOH2 IOH = –100 µA, VCC = VCC min V IO–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

52 Am29PDL128G October 28, 2004

Table 19. Test Specifications Figure 10. Test Setup Figure 11. Input Waveforms and Measurement Levels

1. See Figure 12 and Table 19 for test specifications
2. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V CC/2. The time from OE# high to

the data bus driven to VCC/2 is taken as tDF.

0 VRY/BY#

Figure 12. Read Operation Timings

54 Am29PDL128G October 28, 2004

Figure 13. Page Read Operation Timings

Figure 14. Reset Timings

56 Am29PDL128G October 28, 2004

Figure 15. WORD# Timings for Read Operations Note: Refer to the Erase and Program Operations table for tAS and tAH specifications. Figure 16. WORD# Timings for Write Operations

October 28, 2004 Am29PDL128G 57 PRELIMINARY AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Program Operations” on page 57 for more information. Parameter Speed Options JEDEC Std. Description 70R, 70 80 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 12 15 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 12.6 µs Double Word Typ 16 tWHWH1 tWHWH1 Accelerated Programming Operation, Double Word or Word (Note 2) Typ 10.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

58 Am29PDL128G October 28, 2004

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (See “Write Operation Status” on page 46)”.
2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

60 Am29PDL128G October 28, 2004

Figure 20. Back-to-back Read/Write Cycle Timings Figure 21. Data# Polling Timings (During Embedded Algorithms)

62 Am29PDL128G October 28, 2004

Figure 24. Temporary Sector Unprotect Timing Diagram

Figure 25. Sector/Sector Block Protect and

64 Am29PDL128G October 28, 2004

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Program Operations” on page 57 for more information. Parameter Speed Options JEDEC Std. Description 70R, 70 80 90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 45 ns tDVEH tDS Data Setup Time Min 35 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 12.6 µs Double Word Typ 16.6 tWHWH1 tWHWH1 Accelerated Programming Operation, Double Word or Word (Note 2) Typ 10.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.2 sec

1. Figure 26 indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

66 Am29PDL128G October 28, 2004

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables14, 15, 16, and 17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA BALL CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 100 sec Double Word Program Time 16.6 330 µs Excludes system level overhead (Note 5) Word Program Time 12.6 210 µs Accelerated Double Word Program Time 14.5 240 µs Accelerated Word Program Time 10.5 120 µs Chip Program Time (Note 3) Double Word Mode 69.6 208 sec Word Mode 105.7 317 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 13 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

October 28, 2004 Am29PDL128G 67 PRELIMINARY PHYSICAL DIMENSIONS LAB080—80-Ball Fortified Ball Grid Array 1 5x1 0m mp a c k a g e 0.50 BSC. N/A 15.00 mm x 10.00 mm PACKAGE LAB 080 NOM. --- --- --- 1.40 --- --- MAX. 10.00 BSC. 15.00 BSC. --- MIN. 0.60 0.40 9.00 BSC. 7.00 BSC. 0.60 0.70 1.00 BSC. A 0.50 1.00 BSC. ME D JEDEC PACKAGE SYMBOL A MD E φb N NOTE PACKAGE OUTLINE TYPE DEPOPULATED SOLDER BALLS MATRIX SIZE E DIRECTION MATRIX FOOTPRINT BALL PITCH - D DIRECTION BALL PITCH - E DIRECTION BODY SIZE STANDOFF BODY SIZE BODY THICKNESS PROFILE HEIGHT BALL DIAMETER MATRIX SIZE D DIRECTION BALL COUNT MATRIX FOOTPRINT SOLDER BALL PLACEMENT eD eE SD/SE SIDE VIEW SEATING PLANE C C0.25 C0.15 AD 1.00 ± 0.5 TOP VIEW B E C0.20 CORNER A1 CORNER ID. (INK OR LASER) φ 0.50 1.00 ± 0.5 0.20 C BOTTOM VIEW CORNER C 6 7 SE ABCDEFGHJK eD eE SD C AB NXφb φ0.25 φ0.10 M M NOTES UNLESS OTHERWISE SPECIFIED: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 . 2. ALL DIMENSIONS ARE IN MILLIMETERS . 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH . 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C .

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

68 Am29PDL128G October 28, 2004

Revision A (October 29, 2001) Initial release. Revision A+1 (November 13, 2001) Simultaneous Operation Block Diagram Added drawing. Table 13. “Primary Vendor-Specific Extended Added LAB080 package drawing. Added “V” to package marking. Device Bus Operations Corrected sector size references in sector address ta- ble. Password Protection Mode section: Clarified that first 8 bytes of SecSi Sector should be reserved for the password. Added description of using password and SecSi Sector concurrently. SecSi Sector Flash Memory Region Added section on using password and SecSi Sector concurrently. Corrected data for addresses 4D and 4Eh. Deleted PPB Status Command section. command sequences for easier reference. CC6 typical current to 30 mA. Changed t OE for 90 ns speed from 40 to 35 ns. Changed tOH for 70 ns speeds from 4 to 5 ns. ASO for 70 ns speed from 15 to 12 ns. Changed t DS for 80 ns speed from 45 to 35 ns. Changed all references to DPB to DYB.

October 28, 2004 Am29PDL128G 69 PRELIMINARY Figure 1. In-System Sector Protection/Sector Table 14. Memory Array Command Definitions (x32 Table 16. Memory Array Command Definitions (x16 Protect Verify fields to tables. command variable from SA(3A) to SA02. Table 15. Sector Protection Command Definitions Table 17. Sector Protection Command Definitions Revised Order Numbers and Package Markings to re- flect speed option changes. Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph data.” Changed CFI website address. Command Definitions Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to …”may place the device to an unknown state. A reset command is then required to return the device to reading array data.” Command Definition Table 14. and Table 15. Changed one of the Data bus cycles in both tables from 90 to A0. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region and Enter SecSi Sector/Exit SecSi Sector Command Sequence Added notes, “ Note that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled.” Sector Erase Command Sequence and Chip Erase Command Sequence Added “Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress.” Table 14. “Memory Array Command Definitions command sequence from BA to XXX. figuration Register Write Commands. Added ILR parameter to table. Deleted IACC parameter from table. gram Acceleration to 11.5 and 12.5.

70 Am29PDL128G October 28, 2004

Changed the max of Accelerated Double Word Pro- gram Time to 240. Changed the max of Accelerated Word Program Time to 120. BGA Ball Capacitance Replace table with capacitance table on the Am29PDL127H datasheet. Revision B+4 (October 28, 2004) Added Pb-Free options to Ordering information and Valid Combinations. Updated hyperlinks. Trademarks Copyright © 2000-2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .