PD127H53VI

AM29PDL127H AMD | Alldatasheet

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Publication Number 26864 Revision A Amendment +6 Issue Date June 07, 2005 Am29PDL127H Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path. Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. June 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26864 Rev: A Amendment/+6 Issue Date: June 07, 2005 Am29PDL127H 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 128 Mbit Page Mode device — Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations ■ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — Bank C: 48 Mbit (32 Kw x 96) — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) ■ Enhanced VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin —V IO options at 1.8 V and 3 V I/O ■ SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS ■ High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns ■ Power consumption (typical values at 10 MHz) — 45 mA active read current — 18 mA program/erase current — 1 µA typical standby mode current SOFTWARE FEATURES ■ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data ■ WP#/ ACC (Write Protect/Acceleration) input —A t V IL, hardware level protection for the first and last two 4K word sectors. —A t V IH, allows removal of sector protection —A t V HH, provides accelerated programming in a factory setting ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ Package options — 80-ball Fine-pitch BGA — Multi Chip Packages (MCP) This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes Am29PDL127H and is the factory-recommended migration path. Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 128 Mbit Page Mode device — Page size of 8 words: Fast page read access from random locations within the page ■ Single power supply operation — Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ■ Simultaneous Read/Write Operation — Data can be continuously read from one bank while executing erase/program functions in another bank — Zero latency switching from write to read operations ■ FlexBank Architecture — 4 separate banks, with up to two simultaneous operations per device — Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31) — Bank B: 48 Mbit (32 Kw x 96) — Bank C: 48 Mbit (32 Kw x 96) — Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31) ■ Enhanced VersatileI/OTM (VIO) Control — Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin —V IO options at 1.8 V and 3 V I/O ■ SecSiTM (Secured Silicon) Sector region — Up to 128 words accessible through a command sequence — Up to 64 factory-locked words — Up to 64 customer-lockable words ■ Both top and bottom boot blocks in one device ■ Manufactured on 0.13 µm process technology ■ 20-year data retention at 125°C ■ Minimum 1 million erase cycle guarantee per sector PERFORMANCE CHARACTERISTICS ■ High Performance — Page access times as fast as 20 ns — Random access times as fast as 55 ns ■ Power consumption (typical values at 10 MHz) — 45 mA active read current — 18 mA program/erase current — 1 µA typical standby mode current SOFTWARE FEATURES ■ Software command-set compatible with JEDEC 42.4 standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) complaint — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Erase Suspend / Erase Resume — Suspends an erase operation to allow read or program operations in other sectors of same bank ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data ■ WP#/ ACC (Write Protect/Acceleration) input —A t V IL, hardware level protection for the first and last two 4K word sectors. —A t V IH, allows removal of sector protection —A t V HH, provides accelerated programming in a factory setting ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ■ Package options — 80-ball Fine-pitch BGA — Multi Chip Packages (MCP)

June 07, 2005 Am29PDL127H 3 PRELIMINARY GENERAL DESCRIPTION The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The device is offered in an 80-ball Fine-pitch BGA package, and various multi-chip packages. The word-wide data (x16) appears on DQ15-DQ0. This de- vice can be programmed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respec- tively, allowing high speed microprocessors to operate with- out wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous Read/Write Operation with Zero Latency The Simultaneous Read/Write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Page Mode Features The page size is 8 words. After initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires a single 3.0 volt power supply (2.7 V to 3.6 V or 2.7 V to 3.3 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timing. Register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch ad- dresses and data needed for the programming and erase operations. Reading data out of the device is similar to read- ing from other Flash or EPROM devices. Device programming occurs by executing the program com- mand sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. Device erasure occurs by execut- ing the erase command sequence. The host system can detect whether a program or erase op- eration is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC de- tector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power con- sumption is greatly reduced in both these modes. AMD’s Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electri- cally erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Bank Sectors A 16 Mbit (4 Kw x 8 and 32 Kw x 31) B 48 Mbit (32 Kw x 96) C 48 Mbit (32 Kw x 96) D 16 Mbit (4 Kw x 8 and 32 Kw x 31)

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Table 7. Am29PDL127H Boot Sector/Sector Block Addresses for Figure 1. In-System Sector Protection/

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Note:RY/BY# is an open drain output. Part Number Am29PDL127H Speed Option VCC,VIO = 2.7–3.6 V 53 63 VCC = 2.7–3.6 V, VIO = 1.65–1.95 V 68 88 Max Access Time, ns (tACC)5 5 Max CE# Access, ns (tCE)6 0 7 0 Max Page Access, ns (tPACC) 20 25 30 30 Max OE# Access, ns (tOE) VCC VSS State Control Command Register PGM Voltage Generator VCC Detector Timer Erase Voltage Generator Input/Output Buffers Sector Switches Chip Enable Output Enable Logic Y-Gating Cell Matrix Address Latch Y-Decoder X-Decoder Data Latch RESET# RY/BY# (See Note) A22–A3 A2–A0 CE# WE# DQ15–DQ0 VIO OE#

June 07, 2005 Am29PDL127H 7 PRELIMINARY SIMULTANEOUS OPERATION BLOCK DIAGRAM VCC VSS Bank A Address Bank B Address A22–A0 RESET# WE# CE# DQ0–DQ15 STATE CONTROL COMMAND REGISTER RY/BY# Bank A X-Decoder OE# DQ15–DQ0 Status Control A22–A0 A22–A0 A22–A0A22–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank B X-Decoder Y-gate Bank C X-Decoder Bank D X-Decoder Y-gate Bank C Address Bank D Address WP#/ACC

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Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP , BGA, PDIP , SSOP , PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. B2 D2 E2 F2 G2 H2 J2 D3 E3 F3 G3 H3 J3 D4 E4 F4 G4 H4 J4 D5 E5 F5 G5 H5 J5 D6 E6 F6 G6 H6 J6 B7 D7 E7 F7 G7 H7 J7 NC DQ15A16A15A14A12A13NC DQ14 DQ13DQ7A11A10A8A9 DQ12 V CCDQ5A19A21RESET#WE# DQ10 DQ11DQ2A20A18WP#/ACCRY/BY# DQ8 DQ9DQ0A5A6A17A7 CE# OE# V SS DQ6 DQ4 DQ3 DQ1 V SSA0A1A2A4A3NC B1 D1 E1 F1 G1 H1 J1 VIO NCNCNCNCNCNCNC NC B8 D8 NC NC C8 E8 F8 G8 H8 J8 NC NC NC NC NC NC NC NC NC NC NC NCVSSVIONCA22NCNC NC 80-Ball Fine-pitch BGA Top View, Balls Facing Down

June 07, 2005 Am29PDL127H 9 PRELIMINARY PIN DESCRIPTION A22–A0 = 23-bit address bus for 128 Mb de- vice. A9 supports 12 V autoselect in- puts. DQ15–DQ0 = 16-bit data inputs/outputs/float CE# = Chip Enable Inputs OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= V IH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= V IL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V , program and erase operations are accelerated. VIO = Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) VCC = Chip Power Supply (2.7 V to 3.6 V) RESET# = Hardware Reset Pin LOGIC SYMBOL DQ15–DQ0 A22–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO (VCCQ)

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Note: For the Am29PDL127H, the last digit of the speed grade specifies the VIO range of the device. Speed grades ending in 3 (e.g., 53, 63) indicate a 3 Volt VIO range. Speed ending in 8 (e.g., 68, 88) indicate a 1.8 Volt VIO range. Contact AMD or Fujitsu for availability of 1.8V VIO range devices. Am29PDL127 H 53 VK I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE VK = 80-Ball Fine-pitch Ball Grid Array 0.8 mm pitch, 11.5 x 9 mm package (VBB080) SPEED OPTION See Product Selector Guide and Valid Combinations Process Technology H = 0.13 µm DEVICE NUMBER/DESCRIPTION Am29PDL127H

128 Megabit (8 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for BGA Packages Order Number Package Marking Speed (ns) VIO Range Am29PDL127H53 VKI PD127H53V I 55 2.7– 3.6 V Am29PDL127H63 VKI PD127H63V 65 2.7– 3.6 V Am29PDL127H68 VKI PD127H68V 65 1.65– 1.95 V Am29PDL127H88 VKI PD127H88V 85 1.65– 1.95 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29PDL127H Device Bus Operations

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High

Voltage Sector Protection section.

1. WP#/ACC must be high when writing to sectors 0, 1, 268, or 269.

mand is necessary in this mode to obtain array data. rent specification for reading array data. supplying the specific word location.

0.3 V XX VIO ±

0.3 V X (Note 2) X High-Z

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A2–A0 to select the specific word within that page. Table 2. Page Select dresses (A22–A20) with zero latency. Table 3. Bank Select and Unlock Bypass command sequences. the address bits required to uniquely select a bank. tables and timing diagrams for write operations. state, independent of the OE# input.

June 07, 2005 Am29PDL127H 13 PRELIMINARY (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the CMOS standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 150 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at V IH before the device reduces current to the stated sleep mode specification. I CC5 in the DC Characteris- tics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V , the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state

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Table 4. Am29PDL127H Sector Architecture

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Table 5. SecSi TM Sector Addresses accessed in-system through the command register. read the corresponding identifier code on DQ7–DQ0. the other bank, without exiting the autoselect mode. mand Sequence section for more information.

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Table 6. Autoselect Codes (High Voltage Method)

Table 7. Am29PDL127H Boot Sector/Sector Block

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The Am29PDL127H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. The WP# Hardware Protection feature is always avail- able, independent of the software managed protection method chosen. Selecting a Sector Protection Mode All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protec- tion method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is de- sired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a pro- gram or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is pro- tected or unprotected. See Autoselect Mode for de- tails. Persistent Sector Protection The Persistent Sector Protection method replaces the

12 V controlled protection method in previous AMD

flash devices. This new method provides three differ- ent sector protection states: ■ Persistently Locked—The sector is protected and cannot be changed. ■ Dynamically Locked—The sector is protected and can be changed by a simple command. ■ Unlocked—The sector is unprotected and can be changed by a simple command. To achieve these states, three types of “bits” are used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits ( PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB re- quires erasure, the device must be instructed to pre- program all of the sector PPBs prior to PPB erasure. Otherwise, a previously er ased sector PPBs can po- tentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure. Persistent Protection Bit Lock (PPB Lock) The Persistent Protection Bit Lock (PPB Lock) is a glo- bal volatile bit. When set to “1”, the PPBs cannot be changed. When cleared (“0”), the PPBs are change- able. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is de- faulted to power up in the cleared state – meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to

limited to 100 erase cycles. clear the PPB Lock is to go through a power cycle. hardware protection to sectors 0, 1, 268, and 269. vice operates normally again. Table 8. Sector Protection Schemes PPB, and PPB lock relating to the status of the sector. whether or not the sector is protected or unprotected. DYB/PPB/PPB lock verify command to the device. place the device in password protection mode.

000 Unprotected—PPB and DYB are

001 Unprotected—PPB not

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■ When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. ■ The only means to clear the PPB Lock bit is by writ- ing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the pass- word is permanently set with no means to read, pro- gram, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 µs delay for each “password check.” This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Password and Password Mode Locking Bit In order to select the Password sector protection scheme, the customer must first program the pass- word. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password re- gion, the customer may perform Password Verify oper- ations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: 1. Permanently sets the device to operate using the Password Protection Mode. It is not possible to re- verse this function. 2. Disables all further commands to the password re- gion. All program, and read operations are ignored. Both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Lock- ing Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit Password The 64-bit Password is located in its own memory space and is accessible through the use of the Pass- word Program and Verify commands (see “Password Verify Command”). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify com- mand from reading the contents of the password on the pins of the device. Write Protect (WP#) The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using V ID. This function is provided by the WP# pin and over- rides the previously discussed High Voltage Sector Protection method. If the system asserts V IL on the WP#/ACC pin, the de- vice disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. If the system asserts V IH on the WP#/ACC pin, the de- vice reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors de- pends on whether they were last protected or unpro- tected using the method described in High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Lock- ing Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONL Y means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Suc- cessful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB

June 07, 2005 Am29PDL127H 27 PRELIMINARY Lock Bit is set by issuing the PPB Lock Bit Set com- mand. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persis- tent Protection Mode. High Voltage Sector Protection Sector protection and unprotection may also be imple- mented using programming equipment. The proce- dure requires high voltage (V ID) to be placed on the RESET# pin. Refer to Figure 1 for details on this pro- cedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.

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Figure 3. SecSi Sector Protection Algorithm

Sector, follow the algorithm shown in Figure 4. Figure 4. SecSi Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. device to reading array data.

32 Am29PDL127H June 07, 2005

Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents.

Table 9. CFI Query Identification String Table 10. System Interface String

34 Am29PDL127H June 07, 2005

Table 11. Device Geometry Definition

Table 12. Primary Vendor-Specific Extended Query

36 Am29PDL127H June 07, 2005

Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 13 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. A reset com- mand is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristic section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Com- mands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The AC Characteristic table provides the read parame- ters, and Figure 12 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autose- lect mode. The system may read any number of autoselect codes without reinitiating the command se- quence. Table 13 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector

June 07, 2005 Am29PDL127H 37 PRELIMINARY command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. The SecSi Sector is not ac- cessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 13 shows the address and data requirements for both command sequences. See also “SecSi™ (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 13 shows the address and data requirements for the program command se- quence. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 13 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 14) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

38 Am29PDL127H June 07, 2005

Figure 5. Program Operation tion for information on these status bits. reading array data, to ensure data integrity. and Figure 18 section for timing diagrams. ings during these operations. gram/erase] operation is in progress. Note: See Table 13 for program command sequence.

40 Am29PDL127H June 07, 2005

visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. There is no special addressing order required for pro- gramming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once programming is complete, the user must issue a Read/Reset com- mand to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verifi- cation. The Password Program Command is only ca- pable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out by the Embedded Program Algorithm™ with the cell remain- ing as a “0”. The password is all ones when shipped from the factory. All 64-bit password combinations are valid as a password. Password Verify Command The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will al- ways drive all F’s onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not oper- ate in Simultaneous Operation when the Password Verify command is executed. Only the password is re- turned regardless of the bank address. The lower two address bits (A1-A0) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation. Password Protection Mode Locking Bit Program Command The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Per- sistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command. Persistent Sector Protection Mode Locking Bit Program Command The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Pass- word Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Com- mand should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. SecSi Sector Protection Bit Program Command The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which pre- vents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as pro- grammed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the V CC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. PPB Lock Bit Set Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully exe- cuted. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the Password Unlock command is executed. Upon set- ting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. Exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command (only in the Persistent Protection Mode). DYB Write Command The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A22–A12) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command.

June 07, 2005 Am29PDL127H 41 PRELIMINARY Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 µs at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 µs execution window for each portion of the unlock, the command will be ignored. Once the Password Unlock command is entered, the RY/BY# indicates that the device is busy. Approxi- mately 1 µs is required for each portion of the unlock. Once the first portion of the password unlock com- pletes (RY/BY# is not low or DQ6 does not toggle when read), the next part of the password is written. The system must thus monitor RY/BY# or the status bits to confirm when to write the next portion of the password. Seven cycles are required to successfully clear the PPB Lock Bit. PPB Program Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually pro- grammed (but is bulk erased with the other PPBs). The specific sector address (A22–A12) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been pro- grammed with margin. If the PPB has been pro- grammed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs be- yond 100 cycles is not guaranteed. The PPB Program command does not follow the Em- bedded Program algorithm. All PPB Erase Command The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually eras- ing a specific PPB. Unlike the PPB program, no spe- cific sector address is required. However, when the PPB erase command is written all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the com- mand will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-era- sure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. DYB Write Command The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sector is pro- tected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, remov- ing power or resetting the device will clear the DYBs. The bank address is latched when the command is written. PPB Lock Bit Set Command The PPB Lock Bit set command is used for setting the DYB, which is a volatile bit that is cleared at reset. There is one DYB per sector. If the PPB is set, the sec- tor is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the com- mand is written. PPB Status Command The programming of the PPB for a given sector can be verified by writing a PPB status verify command to the device. PPB Lock Bit Status Command The programming of the PPB Lock Bit for a given sec- tor can be verified by writing a PPB Lock Bit status ver- ify command to the device. Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.

42 Am29PDL127H June 07, 2005

WE# or CE# pulse, whichever happens later. on rising edge of WE# or CE# pulse, whichever happens first. RD = Read Data (DQ15:DQ0) from location RA. write data. Data latched on rising edge of WE#.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. No unlock or command cycles required when bank is reading
6. The Reset command is required to return to reading array (or to

providing status information).

1. Fourth cycle of autoselect command sequence is a read cycle.

section for more information.

1. The data is C0h for factory and customer locked and 80h for
2. The data is 00h for an unprotected sector group and 01h for a
3. Device ID must be read across cycles 4, 5, and 6.
4. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode. erase operation, and requires bank address.

1. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

1. Command is valid when device is ready to read array data or

when device is in autoselect mode. ID during the entire operation of command.

1. Unlock Bypass Entry command is required prior to any Unlock

return to the reading array. Table 13. Memory Array Command Definitions

PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. A22:A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles are
4. During unlock and command cycles, when lower address bits are
5. The reset command returns device to reading array.
6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

in cycle 6, program command must be issued and verified again.

1. Data is latched on the rising edge of WE#.
2. Entire command sequence must be entered for each portion of
3. Command sequence returns FFh if PPMLB is set.
4. The password is written over four consecutive cycles, at
5. A 2 µs timeout is required between any two portions of password.
6. A 100 µs timeout is required between cycles 4 and 5.
7. A 1.2 ms timeout is required between cycles 4 and 5.
8. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
9. DQ1 = 1 if PPB locked, 0 if unlocked.
10. For PDL128G and PDL640G, the WP address is 0111010. The

EP address (PPB Erase Address) is 1111010. Table 14. Sector Protection Command Definitions

44 Am29PDL127H June 07, 2005

WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 15 shows the outputs for Data# Polling on DQ7. Figure 7. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

46 Am29PDL127H June 07, 2005

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare out- puts for DQ2 and DQ6. Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 8 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 8). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits.

Table 15. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

48 Am29PDL127H June 07, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V .

1. Minimum DC input voltage on pins A9, OE#, RESET#,

which may overshoot to +12.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 9. Maximum Negative Figure 10. Maximum Positive functionality of the device is guaranteed.

June 07, 2005 Am29PDL127H 49 PRELIMINARY DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 5 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 150 ns. Typical sleep mode current is 1 μA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET# Input Load Current V CC = VCC max; VID= 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; VID= 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, OE# = VIH VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) OE# = VIH, VCC = VCC max (Note 1)

5 MHz 20 30

10 MHz 45 55

ICC2 VCC Active Write Current (Notes 2, 3) OE# = V IH, WE# = VIL 15 25 mA ICC3 VCC Standby Current (Note 2) CE#, CE2#, RESET#, WP/ACC# = VIO ± 0.3 V 15 µ A ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 1 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VIO ± 0.3 V; VIL = VSS ± 0.3 V 15 µ A ICC6 VCC Active Read-While-Program Current (Notes 1, 2) OE# = VIH 21 45 mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) OE# = VIH 21 45 mA ICC8 VCC Active Program-While-Erase- Suspended Current (Notes 2, 5) OE# = VIH 17 25 mA VIL Input Low Voltage VIO = 1.65–1.95 V –0.4 0.4 V VIH Input High Voltage VIO = 1.65–1.95 V VIO–0.4 V IO+0.4 V VIO = 2.7–3.6 V 2.0 VCC+0.3 V VHH Voltage for ACC Program Acceleration V CC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect V CC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage IOL = 100 µA, VCC = VCC min, VIO = 1.65–1.95 V 0.1 V IOL = 2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 0.4 V VOH Output High Voltage IOH = –100 µA, VCC = VCC min, VIO = 1.65–1.95 V VIO–0.1 V IOH = –2.0 mA, VCC = VCC min, VIO = 2.7–3.6 V 2.4 V VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

50 Am29PDL127H June 07, 2005

Table 16. Test Specifications to certain read-only operation parameters. Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

June 07, 2005 Am29PDL127H 51 PRELIMINARY AC CHARACTERISTIC Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF. 4. For 70 pF output load capacitance, 2 ns will be added to t ACC, tCE, tPACC, tOE values for all speed options. Parameter Description Test Setup Speed Options JEDEC Std. 53 63 68 88 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 65 65 85 ns tAVQV tACC Address to Output Delay CE#, OE# = V IL M a x5 56 56 58 5n s tELQV tCE Chip Enable to Output Delay OE# = V IL M a x6 06 57 08 5n s tPACC Page Access Time Max 20 25 70 85 ns tGLQV tOE Output Enable to Output Delay Max 20 25 30 30 ns tEHQZ tDF Chip Enable to Output High Z (Note 3) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 3) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Notes 3) Min 5 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns

52 Am29PDL127H June 07, 2005

Figure 13. Read Operation Timings Figure 14. Page Read Operation Timings

0 VRY/BY#

Figure 15. Reset Timings

54 Am29PDL127H June 07, 2005

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options J E D E C S t dD e s c r i p t i o n 5 36 36 88 8 U n i t tAVAV tWC Write Cycle Time (Note 1) Min 55 65 65 85 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 30 35 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 25 30 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 10 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns t ELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 40 ns tWHDL tWPH Write Pulse Width High Min 20 25 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

56 Am29PDL127H June 07, 2005

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)

Figure 18. Chip/Sector Erase Operation Timings

58 Am29PDL127H June 07, 2005

1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status rea d

cycle, and array data read cycle. Figure 21. Toggle Bit Timings (During Embedded Algorithms)

1. DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

Figure 22. DQ2 vs. DQ6

Figure 23. Temporary Sector Unprotect Timing Diagram

60 Am29PDL127H June 07, 2005

Figure 24. Sector/Sector Block Protect and

June 07, 2005 Am29PDL127H 61 PRELIMINARY AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std. Description 53 63 68 88 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 65 65 85 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 30 35 ns tDVEH tDS Data Setup Time Min 25 30 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 40 ns tEHEL tCPH CE# Pulse Width High Min 20 25 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 6 µs t WHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec

62 Am29PDL127H June 07, 2005

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D OUT is the data written to the device.

Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings

June 07, 2005 Am29PDL127H 63 PRELIMINARY ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. BGA PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 108 sec Word Program Time 7 210 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 4 120 µs Chip Program Time (Note 3) 50 200 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 13 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

64 Am29PDL127H June 07, 2005

VBB080—80-Ball Fine-pitch Ball Grid Array 11.5 x 9 mm package 3233 \\ 16-038.9h NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEP T AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. PACKAGE VBB 080 JEDEC N/A 11.50 mm x 9.00 mm NOM PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.00 OVERALL THICKNESS A1 0.20 --- --- BALL HEIGHT A2 0.62 --- 0.76 BODY THICKNESS D 11.50 BSC. BODY SIZE E 9.00 BSC. BODY SIZE D1 8.80 BSC. BALL FOOTPRINT E1 5.60 BSC. BALL FOOTPRINT MD 12 ROW MATRIX SIZE D DIRECTION ME 8 ROW MATRIX SIZE E DIRECTION N 80 TOTAL BALL COUNT φb 0.30 0.35 0.40 BALL DIAMETER e 0.80 BSC. BALL PITCH SD / SE 0.40 BSC. SOLDER BALL PLACEMENT (A3-A6, B3-B6, L3-L6, -M3-M6) DEPOPULATED SOLDER BALLS BOTTOM VIEWTOP VIEW SIDE VIEW A1 CORNER A2A INDEX MARK CORNER 10 PIN A1 ML J K e C0.05 (2X) (2X) C0.05 E D BACEDFHG e SE BCA C Mφ 0.15 φ 0.08 M 0.10 C C0.08 NXφb SD A B C SEATING PLANE

June 07, 2005 Am29PDL127H 65 PRELIMINARY REVISION SUMMARY Revision A (September 30, 2002) Initial release. Revision A+1 (October 29, 2002) Distinctive Characteristics Added VIO option at 1.8 V and 3 V I/O to Enhanced VIO Control section. Modified wording of WP#/ACC (Write Protect/Acceler- ation) Input. Product Selector Guide Modified the Product Selector Guide Table. Changed package type from TBD to VK. Added VKI to Valid combinations table. Added Process Technology to Standard Product sec- tion. Revised Order Numbers and Package Markings to re- flect speed option changes. Global Changed 55 speed option to 53, changed 65 speed option to 63 and 68. Changed CFI website address. Programmed or Protected at the factory. command sequence from BA to XXX. Deleted IACC parameter from table. Corrected the package marking for package type PC on 83 and 88 speed options. Revision A+3 (June 20, 2003) Distinctive Characteristics Changed the active read current to 55 mA. Product Selector Guide Added row to table to expand speed options and allow for another VCC range. Revision A+4 (June 30, 2003) Product Selector Guide Corrected typo in the V CC,VIO range for the 53 speed option. Revision A+5 (November 24, 2003) Global Deleted 64-ball Fortified BGA package option (LAA064). Deleted the 83 speed option (85 ns t ACC, VIO = 2.7–3.6 V). Replaced the 88 speed option (85 ns tACC, V IO = 1.65–1.95 V) with 78 (70 ns t ACC, V IO = 1.65–1.95 V). Changed data sheet status from Advance Information to Preliminary.

66 Am29PDL127H June 07, 2005

Table 16. Sector Protection Command Definitions cycle before the final read cycle (RD0). Added notation to superseding documents. Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .