PAS109B PIXART | Alldatasheet
Document overview
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Technical content
Features
164x124 pixels, 1/11” Lens Automatic/Manual exposure-gain control On chip 10-bit ADC On chip PGA On chip 9-bit DAC User selectable output data formats:
- 8-bit formatted data
- 8/4/2/1-bit raw data Output tri-state through /CSB pin or register AE report Horizontal mirror output Flash light application allowable Automatic de-flicker External oscillator I2C Interface Wide operating supply range: 2.4 – 3.6V Low power dissipation: 16mW @ 60fps Low power down dissipation: 200µµµµW
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 2 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 1. Pin Assignment
7 VDDY1 BYPASS Reference voltage
Pin# Name Type Description Power Supply
28 VDDD P Digital VDD
27 GNDD P Digital Ground
3 VDDA P Analog VDD
2 GNDA P Analog Ground
19 VDDQ P Digital VDD
18 GNDQ P Digital Ground
1 GNDE P Ground
17 D0 O Pixel data output, LSB
16 D1 O Pixel data output
15 D2 O Pixel data output
12 D3 O Pixel data output
11 D4 O Pixel data output
10 D5 O Pixel data output
9 D6 O Pixel data output
8 D7 O Pixel data output, MSB
22 PXCK O Pixel clock output
23 HSYNC O Horizontal Synchronization clock
24 VSYNC O Vertical Synchronization clock
6 VRT I/O ADC reference voltage, top level
4 VCM I/O Common mode voltage reference
5 VRB I/O ADC reference voltage, bottom level
25 SCL I I2C interface clock
26 SDA I/O I2C interface bi-direction data
Misc. Pins
30 CSB I Chip select bar, active low
20 SYSCLK I System clock input pin
14 VLRST BIAS Fixed bias input voltage
13 NC - Not connected
21 NC - Not connected
29 NC - Not connected
31 NC - Not connected
32 NC - Not connected
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 3 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 2. Block Diagram CS PXCK VSYNC HSYNC Reference Voltage Interface control D0..D7b0..b9 Gain code Time Ex posure Gen. Clock ADC 10- Bit ReadOut CDS + Row drive Column & (164x124) Imager Control Timing Decision AEC/AGC PGA Block Diagram Control register I2C SCL SDA Edge detect Data packing Data companding DAC 9-bit Fig 2.1 – Block diagram of PAS109 As the block diagram of PAS109 is shown in Figure 1. By pulling the CSB pin to low, the 164x124 sensor starts to produce a signal according to the amount of the light integrated in pixels. An entire raw data is then fed to a CDS readout array to reduce FPN noise and reset noise. A differential signal is then read out serially and fed to a programmable gain amplifier (PGA) followed by a 10-bit A/D converter. V oltage reference block generates all necessary voltage and current for sensor array and analog circuit.
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 4 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 3. Pixel Array And Pixel Color Pattern 3.1. Pixel array and pixel color pattern The output image format of PAS109B is QQVGA (164x124 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. Dummy row G R G R G R G R B G B G B G B G G R G R G R G R Array: 164(H) x 124(V) B G B G B G B G G R G R G R G R B G B G B G B G Dummy row Dummy row Dummy row Dark line Dark line Dummy row Fig 3.1. Pixel array and pixel color pattern Note: 1. Pixel color pattern does not apply to monochrome sensor. 2. Pixel read-out proceeds from left to right, and from bottom row to top row. 3. Pixel array not drawn to scale. Row 125 Row 124 Row 0 Row 1 164 columns 1column 1 column 124 rows Row 3 Row 2
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 5 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002
4 Output timing:
Hsync=22 PXCK B B B B B BB B2+160+2 raw dataB B B B line time = Hs +4+2+160+2+4 = 194 pixclks B B B Hsync PXCLK 2+160+2 raw data Fig. 4.1 Inter-line timing Valid frame data (124 lines) BlackBlackHsync. Black Frame time (=126 lines)Vsync. Vsync Hsync Fig. 4.2 Inter-frame timing (frame time=126 lines) Valid frame data (124 lines) Frame time (>126 lines) BlackBlack Hsync Vsync Black Hsync Fig. 4.3 Inter-frame timing(frame time>126 lines)
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 6 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 5. I2C Bus PAS109B supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.
5.1 I 2C bus overview
Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 5.1. Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 5.2. Both the master and slave can transmit and receive data from the bus. Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Fig 5.1 Start and Stop Conditions S Start Condition SDA SCL P Stop Condition
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 7 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 Fig 5.2 Valid Data
5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)
S : Start A : Acknowledge by slave P : Stop RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read cycle, RW=0 write cycle. SUBADDRESS : The address values of PAS109B internal control registers (Please refer to PAS109B register description) During write cycle, the master generates start condition and then places the 1 st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS109B) issues acknowledgment, the master places 2 nd byte (sub-address) data on SDA line. Again follow the PAS109B acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS109B control register (address was assigned by nd byte). After PAS109B issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS109B sub-address is automatically increment after each DA TA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS109B can be programming via this way. (Please refer to Fig 5.3.) S SLAVE ID (7 BIT) RW A SUBADDRESS (8 BIT) A DATA PA 1ST BYTE 2ND BYTE n BYTEs + A MSB LSB=0 A DATA DATA STABLE DATA CHANGE ALLOWED SDA SCL
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 8 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002
5.2.2 Slave transmits data to master (read cycle)
The sub-address was taken from previous write cycle The sub-address is automatically increment after each byte read Am : Acknowledge by master Note there is no acknowledgment from master after last byte read During read cycle, the master generates start condition and then place the 1 st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DA TA was also placed on SDA line by PAS109B. The 8 bit data was read from PAS109B internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS109B place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DA TA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS109B) must releases SDA line to master to generate STOP condition. (Please refer to Fig 5.3.) Fig 5.3 Data Transfer Format S SLAVE ADDRESS (7 BITS) RW A DATA (8 BIT) Am DATA 1 P 1ST BYTE 2ND BYTE n BYTE NO ACK IN LAST BYTE Am DATA SDA SCL S Start Condition 1-7 8 9 1-7 8 9 1-7 8 9 P Stop Condition ACK from Receiver DataACK from Receiver DataACK from Receiver R/WAddress
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 9 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002
5.3 I2C Bus Timing
Fig 5.4 I2C Bus Timing
5.4 I2C Bus Timing Specification
SYMBOL MIN. MAX. UNIT SCL clock frequency fscl 10 400 kHz Hold time (repeated) START condition. After this period, the first clock pulse is generated. t HD:STA 4.0 - us Low period of the SCL clock tLOW 4.7 - us HIGH period of the SCL clock tHIGH 0.75 - us Set-up time for a repeated START condition tSU;STA 4.7 - us Data hold time. For I2C-bus device tHD;DA T 0 3.45 us Data set-up time tSU;DA T 250 - ns Rise time of both SDA and SCL signals tr 30 N.D. ns(note1) Fall time of both SDA and SCL signals tf 30 N.D. ns(note1) Set-up time for STOP condition tSU;STO 4.0 - us Bus free time between a STOP and START tBUF 4.7 - us Capacitive load for each bus line Cb 1 15 pF Noise margin at LOW level for each connected device (including hysteresis) VnL 0.1 VDD - V Noise margin at HIGH level for each connected device (including hysteresis) VnH 0.2 VDD - V Note: It depends on the "high" period time of SCL. SDASDASDASDA SCLSCLSCLSCL ttttf ttttHD;STA ttttLOW ttttr ttttHD;DAT ttttHIGH ttttSU;DAT ttttf ttttSU;STA ttttHD;STA ttttSP ttttSU;STO ttttBUFttttr PPPPS SSSSSSSrSSSS
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 10 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 6. Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Vdd DC supply voltage -0.5 3.8 V Vin DC input voltage 0.5 Vdd+0.5 V Vo u t DC output voltage -0.5 Vdd+0.5 V Topt1 Operating temperature (chip functional) -10 70 ℃ Topt2 Operating temperature (guaranteed performance) 0 40 ℃ Symbol Parameter Min. Typ. Max. Unit Type :PWR VDD Analog and digital operating voltage 2.4 3.0 3.6 V IDD Operating Current 8 mA Istby Standby current 100 uA Type :IN & I/O Reset and SYSCLK VIH Input voltage HIGH 2.0 VDD V VIL Input voltage LOW 0 0.8 V Cin Input capacitor 10 pF Ilkg Input leakage current TBD uA Type : OUT & I/O for PXD0:7, PXCK, H/VSYNC & SDA, load 10pf, 1.2kΩ, 3.0volts VOH Output voltage HIGH Vdd-0.2 V VOL Output voltage LOW 0.2 V AC Operating Condition Symbol Parameter Min. Typ. Max. Unit SYSCLK Master clock frequency 4.5 48 MHz PXCK Pixel clock output frequency 1.5 MHz Sensor Characteristics Parameter Symbol Min. Typ. Max. Unit Note Photo response non-uniformity PRNU 1.18 % Saturation output voltage Vsat. 1.35 V Dark output voltage Vdark 35 mV/sec Dark signal non-uniformity DSNU 2.52 % Sensitivity ( Red channel ) R 2.0 V/Lux-sec Sensitivity ( Green channel ) G 2.0 V/Lux-sec Sensitivity ( Blue channel ) B 1.35 V/Lux-sec
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 11 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 7. Package Information 7.1. 32-pin LCC 7.1.1. Pin Connection Diagram 1 2 3 4 1314151617181920 NC GNDA VDDA VCMNC VDDY1 VRT VRB HSYNC NC VLRST GNDQ VDDQ SYSCLK PXCK SCL SDA GNDD VDDD NC CSB NC -- Bottom View -- 29 30 31 32 GNDE VSYNC
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 12 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 7.1.2. Package Outline
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 13 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 7.2. 32-pin LCC chip with lens package 7.2.1. Pin Connection Diagram
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 7.2.2. Lens Specification & Package Outline Lens specification: EFL 1.7mm BFL 1.65mm F no. 2.2 Diagonal Field of View 52° Distortion -3% IR filter cutoff 648nm+10nm Note: Customized lens is available upon request. Package Outline:
PixArt Imaging Inc. PAS109B CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without p e r m i s s i o n . 15 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1.1, Mar. 2002 8. Ordering Information Part Number Color/Monochrome Package PAS109BCB-32 Color 32-pin LCC (plastic) PAS109BBB-32 Monochrome 32-pin LCC (plastic) PAS109BCL-32 Color 32-pin LCC chip with lens PAS109BBL-32 Monochrome 32-pin LCC chip with lens