PAS202BCA PIXART | Alldatasheet
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Technical content
Features
§ VGA(644 x 484 pixels) resolution, ~1/4” Lens § Bayer-RGB color filter array § On-chip 10-bit pipelined A/D converter § Output format: 10-bit parallel RGB raw data § On-chip 9-bit background compensation DAC § On-chip programmable gain amplifier q 4-bit color gain amplifier(x3) q 5-bit global gain amplifier (x5) § Continuous variable frame time(1/2sec~1/30sec) § Continuous variable exposure time § I2C Interface § Digitally programmable registers § Single 3.3V supply voltage § 100 mW low power dissipation § 350 uW low power down dissipation § Flash light timing § Mirror output Package 32 pins LCC
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 2 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 1. Pin Assignment Pin No. Name Type Defintion
1 VSSAY GND Analog ground
2 VLRST BIAS Fixed bias input voltage, 1.65V
3 PXD9 OUT Digital data out
4 PXD8 OUT Digital data out
5 PXD7 OUT Digital data out
6 PXD6 OUT Digital data out
7 PXD5 OUT Digital data out
8 VDDQ PWR Digital VDD, 3,3V
9 VSSQ GND Digital ground
10 VSSQ GND Digital ground
11 PXD4 OUT Digital data out
12 PXD3 OUT Digital data out
13 NC Not connected
14 PXD2 OUT Digital data out
15 PXD1 OUT Digital data out
16 PXD0 OUT Digital data out
17 SYSCLK IN Master clock input
18 PXCLK OUT Pixel clock output
19 HSYNC OUT Horizontal synchronization signal
20 VSYNC OUT Vertical synchronization signal
21 SCL IN I2C clock
22 SDA I/O I2C data
23 VDDD PWR Digital VDD, 3.3V
24 VSSD GND Digital ground
25 CSB IN Chip select (Low, active, chip disable if high)
26 VCM BYPASS Analog voltage reference
27 VRT BYPASS Analog voltage reference
28 VRB BYPASS Analog voltage reference
29 NC Not connected
30 VSSA GND Analog ground
31 VDDA PWR Analog VDD, 3.3V 32 VDDAY PWR Analog VDD, 3.3V
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 3 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 Timing Digital Control Register setsI2C Interface Global gain 5-bits 10-bit pipelined ADC Color gain B,G,R 4-bits Sensor Array CDS ckts Col. Decoders Row Decoders SDA SCL SysClk PXCLK Hsync Vsync Pxo<9:0> cmd 9-bit +/-1V DAC dac[8:0] 2. Block Diagram Fig 2.1 – Block diag ram of the PAS202BCA/PAS202BBA
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 4 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 3. Output Format 3.1. Pixel Array And Pixel Color Pattern The output image format of PAS202BCA/PAS202BBA is VGA (640x480 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. Fig 3.1. Pixel array and pixel color pattern Note: 1. Pixel color pattern does not apply to monochrome sensor. 2. Pixel read-out proceeds from left to right, and from bottom row to top row. 3. Pixel array not drawn to scale. B G R G B G R G B G B G R G B G R G R G B G R G row lines Row 1 Row 484 Row 485 Pixel array: 644(H) x 486(V) Row 0 Dark pixel R G B Dark pixel 540 dark pixel 13 dark pixel 13 dark pixel 13 dark pixel 13 R pixel 13 B pixel No filter pixel 13 G pixel column lines 644 R G B G R G R G B R G G B G R G B R G B G B G G R G B 13 dark pixel 13 dark pixel 13 dark pixel 13 R pixel 13 B pixel No filter pixel 13 G pixel 13 dark pixel 13 dark pixel 540 dark pixel
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 5 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002
3.2 Output timing:
Pixel per line is programmable, 772 pixels ~ 1156 pixels. 4+4 blank pixel for each line. ( See Fig 3.2. Fig 3.3) 1+1 Dark line for each frame.(See Fig 3.4. Fig 3.5 ) Dark line output format: Fig 3.6. Fig 3.2. Inter-line timing (default) Hsync. xxxx xxxx2+640+2 pixels outxxxx line time =4+644+4 pixclks xxx Pixclk_a 2+640+2 pixels out B G B G Note: "x" indicates don't care PXD[9:0] Nov_by2*2 pixclks Nov_by2*2-8 pixclks Fig 3.3. Inter-line timing (programmable) Fig 3.4. Inter-frame timing (default) Hsync. xxxx xxxx2+640+2 pixels outxxxx line time (min)= 120+4+2+640+2+4 = 772 pixclks xxx 120 pixclks Pixclk_a 2+640+2 pixels out B G B G Note: "x" indicates don't care PXD[9:0] Valid frame data (484 lines) DarkHsync. 120 Pixclks 120 Pixclks Frame time(min) (=486 lines)Vsync.
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 6 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 Valid frame data (484 lines) Hsync. Pixclks Frame time = lpf lines Vsync. Dark Dark DarkDark Valid frame data (484 lines) Valid frame data (484 lines) Fig 3.5. Inter-frame timing (programmable) Fig 3.6. Dark line output format Row Dark pixel column lines 644 R G B 13 dark pixel 13 dark pixel 13 dark pixel 13 R pixel 13 B pixel No filter pixel 13 G pixel 13 dark pixel
540 Dark pixel
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 7 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 4. I2C Bus PAS202BCA/PAS202BBA supports I2C-bus transfer protocol and is acting as slave device. The 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.
4.1 I2C bus overview
§ Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. § Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). § Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 4.1. § Valid data: The data on the SDA line must be stable during the high period of the SCL clock. Within each byte, MSB is always t ransferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 4.2. § Both the master and slave can transmit and receive data from the bus. § Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Fig 4.1 Start and Stop Con ditions S Start Condition SDA SCL P Stop Condition
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 8 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 Fig 4.2 Valid Data
4.2 Data Transfer Format
4.2.1 Master transmits data to slave (write cycle)
§ S : Start § A : Acknowledge by slave § P : Stop § RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW=1 read c ycle, RW=0 write cycle. § SUBADDRESS : The address values of PAS202BCA/PAS202BBA internal control registers (Please refer to PAS202BCA/PAS202BBA register description) During write cycle, the master generates start condition and then places the 1 st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS202BCA/PAS202BBA) issues acknowledgment, the master places 2 nd byte (sub -address) data on SDA line. Again follow the PAS202BCA/PAS202BBA acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS202BCA/PAS202BBA control register (address was assigned by 2 nd byte). After PAS202BCA/PAS202BBA issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS202BCA/PAS202BBA sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control S SLAVE ID (7 BIT) RW A SUBADDRESS (8 BIT) A DATA PA 1ST BYTE 2ND BYTE n BYTEs + A MSB LSB=0 A DATA DATA STABLE DATA CHANGE ALLOWED SDA SCL
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 9 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 registers value inside PAS202BCA/PAS202BBA can be programming via this way. (Please refer to Fig 4.3.)
4.2.2 Slave transmits data to master (read cycle)
§ The sub-address was taken from previous write cycle § The sub-address is automatically increment after each byte read § Am : Acknowledge by master § Note there is no acknowledgment from master after last byte read During read cycle, the master generates start condition and then place the 1 st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS202BCA/PAS202BBA. The 8 bit data was read from PAS202BCA/PAS202BBA internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS202BCA/PAS202BBA place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS202BCA/PAS202BBA) must releases SDA line to master to generate STOP condition. (Please refer to Fig 4.3.) Fig 4.3 Data Transfer Format S SLAVE ADDRESS (7 BITS) RW A DATA (8 BIT) Am DATA 1 P 1ST BYTE 2ND BYTE n BYTE NO ACK IN LAST BYTE Am DATA SDA SCL S Start Condition 1-7 8 9 1-7 8 9 1-7 8 9 P Stop Condition ACK from Receiver DataACK from Receiver DataACK from Receiver R/WAddress
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 10 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002
4.3 I2C Bus Timing
Fig 4.4 I2C Bus Timing
4.4 I2C Bus Timing Specification
SYMBOL MIN. MAX. UNIT SCL clock frequency fscl 10 400 kHz Hold tie (repeated) START condition. After this period, the first clock pulse is generated. t HD:STA 4.0 - us Low period of the SCL clock tLOW 4.7 - us HIGH period of the SCL clock tHIGH 0.75 - us Set-up time for a repeated START condition tSU;STA 4.7 - us Data hold time. For I2C-bus device tHD;DAT 0 3.45 us Data set-up time tSU;DAT 250 - ns Rise time of both SDA and SCL signals tr 30 N.D. ns(note1) Fall time of both SDA and SCL signals tf 30 N.D. ns(note1) Set-up time for STOP condition tSU;STO 4.0 - us Bus free time between a STOP and START tBUF 4.7 - us Capacitive load for each bus line Cb 1 15 pF Noise margin at the LOW level for each connected device (including hysteresis) VnL 0.1 VDD - V Noise margin at the HIGH level for each connected device (including hysteresis) VnH 0.2 VDD - V Note 1: It depends on the "high" period time of SCL. SDA SCL tf tHD;STA tLOW tr tHD;DAT tHIGH tSU;DAT tf tSU;STA tHD;STA tSP tSU;STO tBUFtr P SS rS
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 11 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 5. Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Vdd DC supply voltage -0.5 3.8 V Vin DC input voltage 0.5 Vdd+0.5 V Vout DC output voltage -0.5 Vdd+0.5 V Symbol Parameter Min. Typ. Max. Unit Type :PWR VDD Analog and digital operating voltage 3.00 3.3 3.60 V IDD Operating Current 30 mA Type :IN & I/O Reset and SYSCLK VIH Input voltage HIGH 2.0 VDD V VIL Input voltage LOW 0 0.8 V Cin Input capacitor 10 pF Ilkg Input leakage current 1.0 uA Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 20pf, 3.3volts VOH Output voltage HIGH Vdd-0.2 V VOL Output voltage LOW 0.2 V AC Operating Condition Symbol Parameter Min. Typ. Max. Unit fsysclk Master clock frequency 8 48 MHz fpxclk Pixel clock output frequency 12 MHz Sensor Characteristics Parameter Symbol Min. Typ. Max. Unit Note Photo response non-uniformity PRNU 1.7 % Saturation output voltage Vsat. 1.2 V Dark output voltage Vdark 53 mV/sec Dark signal non-uniformity DSNU 2.79 Lsb Sensitivity ( Red channel ) R 0.8 V/Lux-sec Sensitivity ( Green channel ) G 0.6 V/Lux-sec Sensitivity ( Blue channel ) B 0.6 V/Lux-sec Column non-uniformity Cnu 1.56 %
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 12 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 tLOW tr tHIGH tf PXCLK 25 26 27 28 56789101112 VSSD VCM VRT VRBPXD7 VLRST VSSAY VDDA VSSA NC PXD1 NC PXD9 PXD8 PXD6 PXD5 VDDQ VSSQ PXD4 PXD3 PXD2 SYSCLK PXCLK HSYNC VSYNC VDDD SDA SCL -- Bottom View -- 21 22 23 24 CSB VHRST VSSQ PXD0 PXCLK Timing Specification @12M Hz Symbol Parameter Min. Typ. Max. Unit tLOW Low period of the PXCLK duty cycle 40% 50% 60% % tHIGH High period of the PXCLK duty cycle 40% 50% 60% % tr Rise time signal 10 ns tf Fall time signal 10 ns Cb Capacitive load for each bus line 15 pF 6. Package Information 6.1. Pin Connection Diagram
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 13 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 6.2. Package Outline
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 6.3. Optical Center(Sensor Array Center)and Die/Package Center Offset
PixArt Imaging Inc. PAS202BCA/PAS202BBA CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 15 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V1. 2, May. 2002 7. Referencing Schematic PAS202-32PINS-PP.opj BY Jeffery V1.0 pas202BXA-32P A 1 1Tuesday, May 28, 2002 Title Size Document Number Rev Date: Sheet of VDDA VDDD VDDD 3.3V PXD4 PXD2 VSYNC PXD7 PXD1 SYSCLK PXCLK PXD9 PXD0 PXD3 PXD6 PXD5 PXD8 HSYNC VDDD VDDA DGND CSB AGND SDA SCL 0.1uF L2 3.3UH PAS202BCA PAS202BBA PAS202 VDDAY VSSAY VLRST PXD9 PXD7 PXD6 PXD5 VDDQ VSSQ VSSQ PXD4NC PXD2 PXD1 PXD0 SYSCLK PXCLK HSYNC SCL SDA VDDD VSSD CSB VCM VRT NC VSSA VDDA PXD8 PXD3 VSYNC VRB 4.7k 4.7k C6 10uF 300k 0.1uF R2 300k 300k 0.1uF 0.1uF 3.3UH C14 10uF C15 10uF C16 1uF C13 1uF C10 1uF C12 1uF C11 1uF NOTES on capacitors: 1.The 0.1uF caps for pin 8,23,31 and 32 MUST have trace lengths LESS than 5mm. 2.C10,C11,C6 for pins 26,27 and 28 MUST have trace lengths LESS than 5mm.