PAS106BCA-323 PIXART | Alldatasheet
Document overview
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Technical content
Features
§ CIF(356 x 292 pixels ) resolution, ~1/5” Lens § Bayer-RGB color filter array § On-chip 10 -bit pipelined A/D converter § Output format: 10-bit parallel RGB raw data § On-chip 6-bit (1 sign bit+ 5 magnitude bit) background compensation DAC § On-chip programmable gain amplifier q 5-bit color gain amplifier(x4) q 5-bit global gain amplifier (x5) § Continuous variable frame time(1/2sec~1/30sec) § Continuous variable exposure time § I2C Interface § Digitally programmable registers § Single 3.3V supply voltage § 100 mW low power dissipation Scan Mode Progressive S/N Ratio >45dB Package 32-pin LCC
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 2/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 1. Pin Assignment Pin No. Name Type Definition
1 VSSA GND Analog ground
2 VRB BYPASS Analog voltage reference
3 VRT BYPASS Analog voltage reference
4 VCM BYPASS Analog voltage reference
5 VDDA PWR Analog VDD, 3.3V 6 VDDA PWR Analog VDD, 3.3V 7 VDDAY1 PWR Analog VDD, 3.3V 8 VDDAY2 PWR Analog VDD, 3.3V
9 VSSAY GND Analog ground
10 CSB IN Chip select (Low, active, chip disable if high)
11 PXD9 OUT Digital data out
12 PXD8 OUT Digital data out
13 PXD7 OUT Digital data out
14 PXD6 OUT Digital data out
15 PXD5 OUT Digital data out
16 PXD4 OUT Digital data out
17 VDDQ PWR Digital VDD, 3,3V
18 VSSQ GND Digital ground
19 PXD3 OUT Digital data out
20 PXD2 OUT Digital data out
21 PXD1 OUT Digital data out
22 PXD0 OUT Digital data out
23 PXCLK OUT Pixel clock output
24 HSYNC OUT Horizontal synchronization signal
25 VSYNC OUT Vertical synchronization signal
26 SYSCLK IN Master clock input
27 SCL IN I2C clock
28 SDA I/O I2C data
29 VDDD PWR Digital VDD, 3.3V
30 VSSD GND Digital ground
31 VSSA GND Analog ground
32 VLRST BIAS Fixed bias input voltage, 1.65V
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 3/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 2. Block Diagram Timing Digital Control Register setsI2C Interface Global gain 5-bits 10-bit pipelined ADC Color gain B,G1,G2,R 5-bits Sensor Array CDS ckts Col. Decoders Row Decoders SDA SCL SysClk PXCLK Hsync Vsync Pxo<9:0> cmd 6-bit +/-1V DAC
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 4/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 3. Pixel Array And Pixel Color Pattern The output image format of PAS106BCA -323/PAS106BBA -323 is CIF (352x288 pixel array). To provide the co-processor with the extra information it needs for interpolation at the edges of the pixel array, an border of 2 pixels on all 4 sides of the array are available. Fig 3.1. illustrates the pixel array and pixel color pattern. Dark pixel R G B No filter Dark pixel G2 R G2 R G2 R G2 R B G1 B G1 B G1 B G1 G2 R G2 R G2 R G2 R Array: 356(column)x 294(row) B G1 B G1 B G1 B G1 G2 R G2 R G2 R G2 R B G1 B G1 B G1 B G1 Dark pixel R G B No filter Dark pixel Fig 3.1. Pixel array and pixel color pattern Note: 1. Pixel color pattern does not apply to monochrome sensor. 2. Pixel read-out proceed s from left to right, and from bottom row to top row. 3. Pixel array not drawn to scale.
20 R pixel 20 G pixel 20 B pixel 20 pixel
30 dark pixel 30 dark pixel 30 dark pixel 30 dark pixel 30 dark pixel 30 dark pixel 30 dark pixel 30 dark pixel
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 5/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 4. Output timing: Fixed pixel clock for each line(row), 444pxclk. 4+4 blank pxclk for each line. ( See Fig 4.1. ) 1+1 Dark line for each frame.(See Fig 4.2. ) Dark line output format: Fig 4.3. Fig 4.1. Inter-line timing Fig 4.2. Inter-frame timing 4+356+4=364 pxclks Hsync Hsync x x x x x x x xR G B No filfter
20 R pixels 20 B pixels20 G pixels 20 pixels
30 dark pixels30 dark pixels30 dark pixels28 dark pixels Note: "x" indicates don't care. pxclks pxclks Fig 4.3. Dark line output format Hsync. xxxx xxxx2+352+2 pixels outxxxx line time = 80+4+2+352+2+4 = 444 pxclks xxx 80 pxclks Pxclk_a 2+352+2 pixels out B G
1 B G
1 Note: "x" indicates don't care PXD[9:0]
Valid frame data (292 lines) DarkHsync. Pxclks Pxclks Frame time (=294 lines)Vsync.
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 6/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 5. I2C Bus PAS106BCA-323/PAS106BBA-323 supports I2C -bus transfer protocol and is acting as slave device. Th e 7 bits unique slave address is 1000000 and supports receiving / transmitting speed up to 400kHz.
5.1 I2C bus overview
§ Only two wires SDA (serial data) and SCL (serial clock) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. § Only the master can initiates a transfer (start), generates clock signals, and terminates a transfer (stop). § Start and stop condition: A high to low transition of the SDA line while SCL is high defines a start condition. A low to high transition of the SDA line while SCL is high defines a stop condition. Please refer to Fig 5.1. § Valid data: The data on the SDA line must be stable during the high period of the SCL c lock. Within each byte, MSB is always transferred first. Read/write control bit is the LSB of the first byte. Please refer to Fig 5.2. § Both the master and slave can transmit and receive data from the bus. § Acknowledge: The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Fig 5.1 Start and Stop Conditions S Start Condition SDA SCL P Stop Condition
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 7/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 Fig 5.2 Valid Data
5.2 Data Transfer Format
5.2.1 Master transmits data to slave (write cycle)
§ S : Start § A : Acknowledge by slave § P : Stop § RW : The LSB of 1ST byte to decide whether current cycle is read o r write cycle. RW=1 read cycle, RW=0 write cycle. § SUBADDRESS : The address values of PAS106BCA -323/PAS106BBA-323 internal control registers (Please refer to PAS106BCA -323/PAS106BBA-323 register description) During write cycle, the master generates start condition and then places the 1 st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After slave(PAS106BCA-323/PAS106BBA-323) issues acknowledgment, the master places 2 nd byte (sub-address) data on SDA line. Again follow the PAS106BCA -323/PAS106BBA-323 acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS106BCA -323/PAS106BBA-323 control register (address was assigned by 2 nd byte). After PAS106BCA -323/PAS106BBA-323 issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi -byte write, the PAS106BCA-323/PAS106BBA-323 sub -address is automatically increment after each DATA byte transferred. S SLAVE ID (7 BIT) RW A SUBADDRESS (8 BIT) A DATA PA 1ST BYTE 2ND BYTE n BYTEs + A MSB LSB=0 A DATA DATA STABLE DATA CHANGE ALLOWED SDA SCL
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 8/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 The data and A cycles is repeat until last byte write. Every control registers value inside PAS106BCA-323/PAS106BBA-323 can be programming via this way. (Please refer to Fig 5.3.)
5.2.2 Slave transmits data to master (read cycle)
§ The sub -address was taken from previous write cycle § The sub -address is automatically increment after each byte read § Am : Acknowledge by master § Note there is no acknowledgment from master after last byte read During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address (7 bits) with a read/write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS106BCA -323/PAS106BBA-323. The 8 bit data was read from PAS106BCA-323/PAS106BBA-323 internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS106BCA -323/PAS106BBA-323 place the next 8 bits data (address is increment automatically) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave (PAS106BCA -323/PAS106BBA-323) must releases SDA line to master to generate STOP condition. (Please refer to Fig 5.3.) Fig 5.3 Data Transfer Format S SLAVE ADDRESS (7 BITS) RW A DATA (8 BIT) Am DATA 1 P 1ST BYTE 2ND BYTE n BYTE NO ACK IN LAST BYTE Am DATA SDA SCL S Start Condition 1-7 8 9 1-7 8 9 1-7 8 9 P Stop Condition ACK from Receiver DataACK from Receiver DataACK from Receiver R/WAddress
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 9/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002
5.3 I2C Bus Timing
5.4 I2C Bus Timing Specification
SYMBOL MIN. MAX. UNIT SCL clock frequency fscl 10 400 kHz Hold time (repeated) START condition. After this per iod, the first clock pulse is generated. t HD:STA 4.0 - us Low period of the SCL clock tLOW 4.7 - us HIGH period of the SCL clock tHIGH 0.75 - us Set-up time for a repeated START condition tSU;STA 4.7 - us Data hold time. For I2C -bus device tHD;DAT 0 3.45 us Data set -up time tSU;DAT 250 - ns Rise time of both SDA and SCL signals tr 30 N.D. ns(note1) Fall time of both SDA and SCL signals tf 30 N.D. ns(note1) Set-up time for STOP condition tSU;STO 4.0 - us Bus free time between a STO P and START tBUF 4.7 - us Capacitive load for each bus line Cb 1 15 pF Noise margin at the LOW level for each connected device (including hysteresis) VnL 0.1 VDD - V Noise margin at the HIGH level for each connected device (including hysteresis) VnH 0.2 VDD - V Note1: It depends on the "high" period time of SCL. SDA SCL tf tHD;STA tLOW tr tHD;DAT tHIGH tSU;DAT tf tSU;STA tHD;STA tSP tSU;STO tBUFtr P SS rS
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 10/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 6. Specifications Absolute Maximum Ratings Symbol Parameter Min Max Unit Vdd DC supply voltage -0.5 3.8 V Vin DC input voltage 0.5 Vdd+0.5 V Vout DC output voltage -0.5 Vdd+0.5 V Tstg Storage temperature 0 70 ℃ Symbol Parameter Min. Typ. Max. Unit Type :PWR VDD Analog and digital operating voltage 3.15 3.3 3.45 V IDD Operating Current 35 mA Type :IN & I/O Reset and SY SCLK VIH Input voltage HIGH 2.0 VDD V VIL Input voltage LOW 0 0.8 V Cin Input capacitor 10 pF Ilkg Input leakage current 1.0 uA Type : OUT & I/O for PXD0:9, PXCLK, H/VSYNC & SDA, load 10pf, 1.2k Ω, 3.3 volts VOH Output voltage HIGH Vdd-0.2 V VOL Output voltage LOW 0.2 V AC Operating Condition Symbol Parameter Min. Typ. Max. Unit fsysclk Master clock frequency 8 48 MHz fpxclk Pixel clock output frequency 4 MHz Sensor Characteristics (To be determined) Parameter Symbol Min. Typ. Max. Unit Note Photo response non -uniformity PRNU 1.02 % Saturation output voltage Vsat. 1.4 V Dark output voltage Vdark 52 mV/sec Dark signal non -uniformity DSNU 1.9 Lsb Sensitivity ( Red channel ) R 1.2 V/Lux-sec Sensitivity ( Green channe l ) G 1.0 V/Lux-sec Sensitivity ( Blue channel ) B 0.8 V/Lux-sec
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 11/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 7. Package Information 7.1. Pin Connection Diagram 25 26 27 28 56789101112 HSYNC SYSCLK SCL SDAVDDA VRB VSSA VSSA VSSD VDDD PXD5 PXD7 VRT VCM VDDA VDDAY1 VDDAY2 CSB PXD9 PXD8 PXD6 VDDQ VSSQ PXD3 PXD2 PXCLK PXD0 PXD1 -- Bottom View -- 21 22 23 24 VSYNC VLRST VSSAY PXD4
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 12/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 7.2. Package Outline
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 13/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 7.3. Sensor center and Die&Package center bias Chip Center Logo Sensor Center = Package Center
PixArt Imaging Inc. PAS106BCA-323/PAS106BBA-323 CMOS Image Sensor IC All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14/14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw V2.0, May 2002 8. Referencing Circuit Schematic V2.1 PAS106_SENSOR-32PINS.opj 1 1Wednesday, May 22, 2002 Title Size Document Number Rev Date: Sheet of VDDD VDDA 3.3V PXD3 HSYNC AGND PXCLK PXD1 SYSCLK PXD6 PXD5 PXD8 PXD2 PXD4 VSYNC PXD7 PXD0 PXD9 SCL SDA VLRST VDDA AGND VLRST VDDA DGND VDDD VDDD DGND VDDD CSB C9 0.1uF 1uF 1uF 1uF C5 10uF L2 3.3UH PAS106BCA-323 PAS106BBA-323 PAS106_32 VLRST VSSA VRB VRT VDDA VDDA VDDAY1 VDDAY2 VSSAY CSB PXD9PXD7 PXD6 PXD5 PXD4 VDDQ VSSQ PXD3 PXD1 PXD0 PXCLK HSYNC VSYNC SYSCLK SCL VDDD VSSD VSSA VCM PXD8 PXD2 SDA 0.1uF 0.1uF 0.1uF 3.3UH C12 10uF C11 1uF C14 1uF C13 10uF 300k 0.1uF C10 0.1uF 300k R4 4.7k R5 4.7k 300k CSB_SW NOTES on capacitors: 1.The 0.1uF caps for power pins MUST have trace lengths LESS than 5mm. 2.C5,C7 and C8 for pins 2,3 and 4 MUST have trace lengths LESS than 5mm.