P620-88OC

PLL620-88 PLL | Alldatasheet

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Technical content

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 1

FEATURES

19MHz to 65MHz crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Supports 2.5V or 3.3V Power Supply. Available in 16 pin TSSOP package.

DESCRIPTION

The PLL620-88 (PECL) and PLL620-89 (LVDS) are XO ICs specifically designed to work with fundamental or 3rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. They require very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. BLOCK DIAGRAM PIN CONFIGURATION OUTPUT SELECTION AND ENABLE OE_SELECT OE_CTRL State Tri-state 1 (Default) Output enabled 0 (Default) Output enabled 1 (Default) Tri-state Input selection: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” OUTPUT FREQUENCY DIVIDE BY TWO SELECTOR Output Intput/2 Input O E Q PLL620-8X Block Diagram Q Oscillator Amplifier PLL 620-8x VDD XIN XOUT DNC OE N/C GND DNC DNC GNDBUF QBAR VDDBUF Q GNDBUF GND

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 2 PIN AND PAD ASSIGNMENT Name Pin# Power Supply. XIN Crystal input. See Crystal Specification on page 3. XOUT Crystal output. See Crystal Specification on page 3. DNC Do Not Connect. Output Divide by Two selector pin. See the OUTPUT DIVIDE BY TWO SELECTOR Table on page 1. OE_CTRL Output Enable input. See OUTPUT SELECTION AND ENABLE TABLE on page 1. DNC Do Not Connect. GND Ground. GNDBUF Ground for output buffer circuitry. Q PECL or LVDS output. VDDBUF Power supply for output buffer circuitry. QBAR Complementary PECL or LVDS output. GNDBUF Ground for output buffer circuitry. DNC Do Not Connect. DNC Do Not Connect. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 3 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Fundamental MHz Crystal Loading Rating CL (xtal) 8.5 pF Interelectrode Capacitance pF Recommended ESR RE AT cut Ω 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD PECL/LVDS mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS at 27MHz 2.3 Period jitter peak-to-peak at 27MHz With capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 ps Accumulated jitter RMS at 27MHz 2.3 Accumulated jitter peak-to-peak at 27MHz With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. ps Random Jitter “RJ” measured on Wavecrest SIA 3000 2.3 ps Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise relative to carrier 27MHz -75 -100 -125 -140 -145 dBc/Hz Note: Phase Noise measured on Agilent E5500

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 4 6. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 uA Output Short Circuit Current IOSD -5.7 mA 7. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50Ω 50Ω OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 5 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.620 V 9. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns OUT OUT 50Ω 50Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V

Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/08/04 Page 6

PACKAGE INFORMATION

C L A E H D e B

16 PIN TSSOP ( mm )

Min. Max. A 1.20 0.05 0.15 B 0.19 0.30 C 0.09 0.20 D 4.90 5.10 E 4.30 4.50 H

6.40 BSC

L 0.45 0.75 e

0.65 BSC

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-8x x C Order Number Marking Package Option PLL620-88OC-R P620-88 OC TSSOP – Tape and Reel PLL620-88OC P620-88 OC TSSOP – Tube PLL620-89OC-R P620-89 OC TSSOP – Tape and Reel PLL620-89OC P620-89 OC TSSOP – Tube PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE O=TSSOP