PLL620-80 PLL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 1
FEATURES
- 19MHz to 65MHz crystal input.
- Output range: 9.5MHz – 65MHz
- Selectable OE Logic (enable high or enable low).
- Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output).
- Supports 2.5V or 3.3V Power Supply.
- Available in die form.
DESCRIPTION
The PLL620-80 is a XO IC specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. It requires very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. Furthermore, it provides selectable CMOS, PECL or LVDS outputs. DIE SPECIFICATIONS Name Value Size 62 x 65 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil BLOCK DIAGRAM DIE CONFIGURATION OUTPUT SELECTION AND ENABLE OUT_SEL1* (Pad 18) OUT_SEL0* (Pad 25) Selected Output* 0 0 High Drive CMOS 0 1 Standard CMOS 1 0 LVDS 1 1 PECL (default) OE_SELECT (Pad 9) OE_CTRL (Pad 30) State
0 Tri-state 0
1 (Default) Output enabled 0 (Default) Output enabled 1 (Default) 1 Tri-state Pads #9, #18 & #25: Bond to GND to set to “0”, No connection results to “default” setting through internal pull-up. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” OUTPUT FREQUENCY SELECTOR S2 Output
0 Input/2
1(Default)* Input *Internally set to ‘Default’ through 60K pull-up resistor 181920212325 Y X (0,0) (1550,1475) 62 mil 65 mil 24 22 17 861 2 3 4 5 GND GND GND GND GND GNDBUF GNDBUF OE_SEL^ PECL LVDS VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1^ Reserved N/C VDD VDD VDD VDD OUTSEL0^ XIN XOUT N/C OE CTRL S2^ N/C Reserved Die ID: A2020-20B C502A XIN XOUT OE Q PLL620-80 Q Oscillator Amplifier
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 2 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Fundamental 19 65 MHz Crystal Loading Rating CL (xtal) Die 8* pF Interelectrode Capacitance C0 5 pF Recommended ESR RE AT cut 30 W Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD PECL/LVDS/CMOS 100/80/40 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 3 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS at 27MHz 2.3 Period jitter peak-to-peak at 27MHz With capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 20 ps Accumulated jitter RMS at 27MHz 2.3 Accumulated jitter peak-to-peak at 27MHz With capacitive decoupling between VDD and GND. Over 1,000,000 cycles. 24 25 ps Random Jitter “RJ” measured on Wavecrest SIA 3000 2.3 ps Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise relative to carrier 27MHz -75 -100 -125 -140 -145 dBc/Hz Note: Phase Noise measured on Agilent E5500 6. CMOS Output Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V 30 mA Output drive current (High Drive) IOL VOL = 0.4V, VDD = 3.3V 30 mA IOH VOH= VDD-0.4V, VDD=3.3V 10 mA Output drive current (Standard Drive) IOL VOL = 0.4V, VDD = 3.3V 10 mA Output Clock Rise/Fall Time (Standard Drive) 0.3V ~ 3.0V with 15 pF load 2.4 Output Clock Rise/Fall Time (High Drive) 0.3V ~ 3.0V with 15 pF load 1.2 ns
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 4 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change DVOD -50 50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change DVOS RL = 100 W (see figure) 0 3 25 mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±1 ±10 uA Output Short Circuit Current IOSD -5.7 -8 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 W CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50W 50W OUT VDIFF RL = 100W CL = 10pF CL = 10pF LVDS Switching Test CircuitLVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 5 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 W to (VDD – 2V) (see figure) VDD – 1.620 V 10. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns OUT OUT 50W 50W PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 6 PAD DESCRIPTIONS Pad # Name X (mmmmm) Y (mmmmm) Description 1 GND 248 109 Ground. 2 GND 361 109 Ground. 3 Optional GND 473 109 Optional Ground. 4 GND 587 109 Ground. 5 GND 702 109 Ground. 6 Reserved 874 109 Reserved for future use. 7 GNDBUF 1042 109 Ground, buffer circuitry. 8 GNDBUF 1171 109 Ground, buffer circuitry.
9 OE_SEL 1400 125
This is the selector input to choose the OE control logic. See the OE SELECTION AND ENABLE table on page 1. Internal pull up. 10 LVDS 1400 259 LVDS output. 11 PECL 1400 476 PECL output. 12 VDDBUF 1400 616 Power supply, buffer circuitry. 13 VDDBUF 1400 716 Power supply, buffer circuitry. 14 PECLB 1400 871 Complementary PECL output. 15 LVDSB 1400 1089 Complementary LVDS output. 16 CMOS 1400 1227 CMOS output. 17 GNDBUF 1389 1365 Ground, buffer circuitry.
18 OUTSEL1 1232 1365
Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. 19 Reserved 1042 1365 Reserved for future use. 20 Not connected 854 1365 Not Connected. 21 VDD 659 1365 Power supply. 22 Optional VDD 559 1365 Optional Power supply. 23 VDD 459 1365 Power supply. 24 VDD 358 1365 Power supply.
25 OUTSEL0 194 1365
Selector input to choose the selected output type (PECL, LVDS, CMOS). See the OUTPUT SELECTION AND ENABLE table on page 1. Internal pull up. 26 XIN 109 1223 Crystal input. See Crystal Specifications on page 3. 27 XOUT 109 1017 Crystal output. See Crystal Specifications on page 3. 28 Not connected 109 858 Not Connected.
29 S2 109 646
Output Divide by Two selector pin, as presented on the OUTPUT FREQUENCY SELECTOR Table on page 1. Internal pull up. 30 OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table on page 1. 31 Not connected 109 181 Not connected. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
Low Phase Noise XO (9.5-65MHz Output) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/09/04 Page 7
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-80 DC Order Number Marking Package Option PLL620-80DC P620-80DC Die – Waffle Pack PART NUMBER PACKAGE TYPE D=DIE TEMPERATURE C=COMMERCIAL I=INDUSTRIAL