P620-00DC

PLL620-00 PLL | Alldatasheet

Document overview

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Technical content

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

100MHz to 200MHz Fundamental or 3rd Overtone Crystal input. Output range: 100 – 200MHz (no multiplication), 200 – 400MHz (2x multiplier) or 400 – 700MHz (4x multiplier). Available outputs: PECL, LVDS, or CMOS (High Drive (30mA) or Standard Drive (10mA) output). Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil.

DESCRIPTION

The PLL620-00 is an XO IC specifically designed to work with high frequency fundamental and third overtone crystals. Its design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring LVDS or PECL output levels at high frequencies. DIE SPECIFICATIONS Name Value Size 62 x 65 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil BLOCK DIAGRAM DIE CONFIGURATION OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) OUTSEL0 (Pad #25) Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) OE_SELECT (Pad #9) OE_CTRL (Pad #30) State Tri-state 1 (Default) Output enabled 0 (Default) Output enabled 1 (Default) Tri-state Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0” OE Q PLL620-00 Vin Q PLL by-pass SEL PLL (Phase Locked Loop) Oscillator Amplifier Y X (0,0) (1550,1475) 62 mil 65 mil GND GND GND GND GND GND GNDBUF OE_SEL^ PECL LVDS VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1^ SEL1^ SEL0^ VDD VDD VDD VDD OUTSEL0^ XIN XOUT NC OE CTRL SEL2^ SEL3^ NC Die ID: A1010-10A C502A

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2 FREQUENCY SELECTION TABLE SEL3 (Pad #28) SEL2 (Pad #29) SEL1 (Pad #19) SEL0 (Pad #20) Selected Multiplier Fin x 4 Fin x 2 No multiplication (no PLL) All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications 3. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (Loaded Outputs) IDD PECL/LVDS/CMOS 100/80/40 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) Short Circuit Current ±50 mA NAME SYMBOL CONDITIONS MIN MAX UNITS Parallel Resonant mode Fund. Or 3rd Overtone N/A Load capacitance (capacitance on built-in on die seen by crystal) CL Die only, no bond wire, no package 3.2 pF Inter-electrode capacitance pF Oscillation Frequency Fund. Or 3rd Overtone 100 200 MHz

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3 4. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS 2.5 Period jitter peak-to-peak At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles 18.5 ps Accumulated jitter RMS 2.5 Accumulated jitter peak-to- peak At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. ps Random Jitter “RJ” measured on Wavecrest SIA 3000 2.5 ps Integrated jitter RMS at 155MHz Integrated 12 kHz to 20 MHz 0.3 0.4 ps Period jitter RMS Period jitter peak-to-peak At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles ps Accumulated jitter RMS Accumulated jitter peak-to- peak At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. ps Random Jitter “RJ” measured on Wavecrest SIA 3000 ps Integrated jitter RMS at 622MHz Integrated 12 kHz to 20 MHz 1.6 1.8 ps Note: Higher Q factor of 3rd overtone crystals will result in even better jitter performance. Measured on Wavecrest SIA 3000 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 155.52MHz -75 -95 -125 -140 -145 Phase Noise relative to carrier 622.08MHz -75 -95 -110 -125 -120 dBc/Hz Note: Higher Q factor of 3rd overtone crystals will result in even better phase noise performance. 6. CMOS Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS IOH VOH= VDD-0.4V, VDD=3.3V mA Output drive current (High Drive) IOL VOL = 0.4V, VDD = 3.3V mA IOH VOH= VDD-0.4V, VDD=3.3V mA Output drive current (Standard Drive) IOL VOL = 0.4V, VDD = 3.3V mA Output Clock Rise/Fall Time (Standard Drive) 0.3V ~ 3.0V with 15 pF load 2.4 Output Clock Rise/Fall Time (High Drive) 0.3V ~ 3.0V with 15 pF load 1.2 ns

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Differential Voltage VOD 247 355 454 mV VDD Magnitude Change ∆VOD -50 mV Output High Voltage VOH 1.4 1.6 V Output Low Voltage VOL 0.9 1.1 V Offset Voltage VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS RL = 100 Ω (see figure) mV Power-off Leakage IOXD Vout = VDD or GND VDD = 0V ±10 uA Output Short Circuit Current IOSD -5.7 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf RL = 100 Ω CL = 10 pF (see figure) 0.2 0.7 1.0 ns OUT OUT VOD VOS 50Ω 50Ω OUT VDIFF RL = 100Ω CL = 10pF CL = 10pF LVDS Switching Test Circuit LVDS Levels Test Circuit LVDS Transistion Time Waveform OUT OUT OUT 0V (Differential) 20% 80% 20% 80% tR tF VDIFF

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage VOH VDD – 1.025 V Output Low Voltage VOL RL = 50 Ω to (VDD – 2V) (see figure) VDD – 1.620 V 10. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.6 1.5 ns Clock Fall Time tf @80/20% - PECL 0.5 1.5 ns OUT OUT 50Ω 50Ω PECL Levels Test Circuit PECL Transistion Time Waveform OUT OUT 50% 20% 80% tR tF VDD DUTY CYCLE 45 - 55% 55 - 45% 50% OUT OUT tSKEW PECL Output Skew 2.0V

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 6 PAD ASSIGNMENT Pad # Name X (µµµµm) Y (µµµµm) Ground. GND 361 109 Ground. GND 473 109 Ground. GND 587 109 Ground. GND 702 109 Ground. N/C 874 109 No Connection. GND 1042 109 Ground. GNDBUF 1171 109 Ground, Buffer circuitry. OE_SELECT 1400 125 Used to select between PECL or CMOS logic states for OE. See Output Selection and Enable table on page 1. Internal pull up. LVDS 1400 259 LVDS output. PECL 1400 476 PECL output. VDDBUF 1400 616 3.3V power supply, Buffer circuitry. VDDBUF 1400 716 3.3V power supply, Buffer circuitry. PECLB 1400 871 Complementary PECL output. LVDSB 1400 1089 Complementary LVDS output. CMOS 1400 1227 CMOS output GNDBUF 1389 1365 Ground, Buffer Circuitry. OUTSEL1 1232 1365 Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. SEL1 1042 1365 Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. SEL0 854 1365 Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. VDD 659 1365 3.3V power supply. VDD 559 1365 3.3V power supply. VDD 459 1365 3.3V power supply. VDD 358 1365 3.3V power supply. OUTSEL0 194 1365 Used to select CMOS, PECL or LVDS output type. See Output Selection and Enable table on page 1. Internal pull up. XIN 109 1223 Crystal input. See crystal specification page 2. XOUT 109 1017 Crystal output. See crystal specification page 2. SEL3 109 858 Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. SEL2 109 646 Used to select multiplication factor. See Frequency Selection table on page 1. Internal pull up. OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table on page 1. NC 109 181 No Connection.

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 7

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL620-00 D C Order Number Marking Package Option PLL620-00DC P620-00DC Die – Waffle Pack PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE D=DIE