P4C1026 PYRAMID | Alldatasheet
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Technical content
Document # SRAM127 REV E Revised April 2007
DESCRIPTION
The P4C1026 is a 1 Meg ultra high speed static RAM organized as 256K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil SOJ – 28-Pin 400 mil SOJ – 28-Pin 400 mil Ceramic DIP – 32-Pin Ceramic LCC
FEATURES
Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Low Power Single 5V±10% Power Supply Data Retention with 2.0V Supply Three-State Outputs FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM SOJ (J5, J7), DIP (C7) Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. The P4C1026 is available in a 28-pin 300 mil and 400 mil SOJ packages, as well as Ceramic DIP and LCC packages, providing excellent board level densities. LCC(L13)
Page 2 of 10Document # SRAM127 REV E MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with –0.5 to +7 V Respect to GND Terminal Voltage with –0.5 to VTERM Respect to GND V CC +0.5 V (up to 7.0V) TA Operating Temperature –55 to +125 °C Symbol Parameter Value Unit T BIAS Temperature Under –55 to +125 °C Bias TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Industrial Commercial Grade(2) Ambient Temperature GND VCC –40°C to +85°C 0°C to +70°C 5.0V ± 10% 5.0V ± 10% Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Unit pF pF CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Typ. ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH VCC = Max ., f = Max., Outputs Open ___ 35 mA mA___ CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC Standby Power Supply Current (CMOS Input Levels) I SB1 Symbol VIH VIL VHC VLC VCD VOL VOH ILI ILO Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Input Clamp Diode Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current Output Leakage Current Test Conditions VCC = Min., IIN = –18 mA IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., CE = VIH VOUT = GND to VCC P4C1026 Min 2.2 –0.5(3) VCC –0.2 –0.5(3) 2.4 Max VCC +0.5 0.8 VCC +0.5 0.2 –1.2 0.4 Unit V V V V V V V µA µA Military -55°C to +125°C 0V 5.0V ± 10%
Page 3 of10Document # SRAM127 REV E DATA RETENTION CHARACTERISTICS Symbol VDR ICCDR tCDR tR Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Test Conditions CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Min 2.0 tRC Typ.* VCC = 2.0V 3.0V 10 15 Max VCC = 2.0V 3.0V 250 500 Unit V µA ns ns DATA RETENTION WAVEFORM *TA = +125°C §tRC = Read Cycle Time † This parameter is guaranteed but not tested. ICC Symbol Parameter Temperature Range Dynamic Operating Current* Commercial Industrial –15 –20 –25 –35 Unit mA mA POWER DISSIPATION CHARACTERISTICS VS. SPEED 80808090 80 75 75 75
Page 4 of 10Document # SRAM127 REV E TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with V IL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF READ CYCLE NO. 1 (OEOEOEOEOE CONTROLLED)(5) AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tRC tAA tAC tOH tLZ tHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Chip Enable to Power Up Time Chip Disable to Power Down Time -15 Min Max -20 Min Max -25 Min Max -35 Min Max Unit ns ns ns ns ns ns ns ns
Page 5 of10Document # SRAM127 REV E TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WEWEWEWEWE CONTROLLED)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show t WZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address. TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7) AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. Parameter -15 -20 -25 -35 UnitMin Min Min MinMax Max Max Max tWC tCW tAW tAS tWP tAH tDW tDH tWZ tDW Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time from End of Write Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write ns ns ns ns ns ns ns ns ns ns
- including scope and test fixture.
be used in series with D OUT to match 166 Ω (Thevenin Resistance). Figure 1. Output Load Figure 2. Thevenin Equivalent
Page 7 of10Document # SRAM127 REV E
ORDERING INFORMATION
The P4C1026 is available in the following temperature, speed and package options. 15 20 25 35 Plastic SOJ, 300 mil -15J3C -20J3C -25J3C -35J3C Plastic SOJ, 400 mil -15J4C -20J4C -25J4C -35J4C Plastic SOJ, 300 mil -15J3I -20J3I -25J3I -35J3I Plastic SOJ, 400 mil -15J4I -20J4I -25J4I -35J4I Ceramic DIP, 400 mil N/A -20CM -25CM -35CM 28-Pin Ceramic LCC N/A -20L28M -25L28M -35L28M 32-Pin Ceramic LCC N/A -20L32M -25L32M -35L32M Ceramic DIP, 400 mil N/A -20CMB -25CMB -35CMB 28-Pin Ceramic LCC N/A -20L28MB -25L28MB -35L28MB 32-Pin Ceramic LCC N/A -20L32MB -25L32MB -35L32MB Speed Military Temperature Military Processeed* Temperature Range Package Commercial Industrial * Military temperature range with MIL-STD-883, Class B compliance N/A = Not Available
Page 8 of 10Document # SRAM127 REV E SOJ SMALL OUTLINE IC PACKAGE SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol Min Max A 0.120 0.148 A1 0.078 - b 0.014 0.020 C 0.007 0.011 D 0.700 0.730 e E E1 0.292 0.300 Q0 . 0 2 5 - 28 (300 mil)
0.050 BSC
0.267 BSC
0.335 BSC
Pkg # # Pins Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.013 0.019 C 0.007 0.013 D 0.720 0.730 e E 0.435 0.445 E1 0.395 0.405 E2 0.360 0.380 Q0 . 0 2 5 - 28 (400 mil)
Page 9 of10Document # SRAM127 REV E Pkg # # Pins Symbol Min Max A 0.115 0.255 b 0.016 0.020 b2 0.045 0.065 C 0.008 0.018 D 1.384 1.416 E 0.387 0.403 eA e L 0.125 0.200 Q 0.015 0.070 S1 0.005 — S2 0.005 — 28 (400 mil)
0.400 BSC
0.100 TYP
SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol Min Max A 0.070 0.093 A1 0.054 0.066 B1 0.025 0.031 D 0.442 0.458 D3 — 0.458 E 0.742 0.758 e h j L 0.045 0.055 L1 0.045 0.055 ND NE L13
0.300 BSC
0.150 BSC
0.200 BSC
0.050 TYP
0.090 REF
RECTANGULAR LEADLESS CHIP CARRIER
Page 10 of 10Document # SRAM127 REV E REVISIONS DOCUMENT NUMBER: SRAM127 DOCUMENT TITLE: P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE OR Oct-05 JDB New Data Sheet A Aug-06 JDB Updated SOJ package information B Oct-06 JDB Added Ceramic DIP, LCC packages and military processing C Dec-06 JDB Added L13 package, removed L12 package D Mar-07 JDB Minor typographic corrections E Apr-07 JDB Corrected LCC pin configuration