P4C1041L

P4C1041L PYRAMID | Alldatasheet

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Technical content

Document # SRAM142 REV OR Revised March 2011 P4C1041L LOW POWER 256K x 16 (4 MEG) STATIC CMOS RAM

FEATURES

Single 5V±10% Power Supply 2.0V Data Retention Easy Memory Expansion Using CE and OE Inputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down when deselected Packages – 44-Pin 400 mil TSOP II FUnCTIOnAL BLOCk DIAgRAM PIn COnFIgURATIOn TSOP II

DESCRIPTIOn

The P4C1041L is a 262,144 words by 16 bits high-speed CMOS static RAM. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. In- puts are fully TTL-compatible. The RAM operates from a single 5.0V ± 10% tolerance power supply. Access times of 55 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P4C1041L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A17. Reading is accom- plished by device selection (CE) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. The P4C1041L comes in a 44-Pin 400 mil TSOP II pack- age.

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 2Document # SRAM142 REV OR DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Value Unit VCC Power Supply Pin with Respect to GND -0.5 to +7.0 V VTERM Terminal Voltage with Respect to GND -0.5 to VCC + 0.5 V TA Operating Temperature -40 to +85 °C TBIAS Temperature Under Bias -40 to +85 °C TSTG Storage Temperature -65 to +150 °C IOUT DC Output Current 20 mA MAxIMUM RATIngS(1) RECOMMEnDED OPERATIng COnDITIOnS grade(2) Ambient Temp gnD VCC Commercial 0°C to 70°C 0V 5.0V ± 10% Industrial -40°C to +85°C 0V 5.0V ± 10% CAPACITAnCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Sym Parameter Conditions Typ Unit CIN Input Capacitance VIN=0V 6 pF COUT Output Capacitance VOUT=0V 8 pF Sym Parameter Test Conditions Min Max Unit VIH Input High Voltage 2.4 VCC + 0.3 V VIL Input Low Voltage -0.2 0.6 V VOL Output Low Voltage (TTL Load) IOL = +2 mA, VCC = Min 0.4 V VOH Output High Voltage (TTL Load) IOH = -1 mA, VCC = Min 2.4 V ILI Input Leakage Current VCC = Max, VIN = GND to VCC -1 +1 µA ILO Output Leakage Current VCC = Max, CE = VIH, VOUT = GND to VCC -1 +1 µA ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VCC - 0.2V, VCC = Max, f = 0, Outputs Open, VIN ≥ VCC - 0.2V or VIN ≤ 0.2V — 50 µA ICC Dynamic Operating Current Cycle Time = Min, CE = VIL, II/O = 0 mA, Other pins at VIH or VIL 60 mA ICC1 Dynamic Operating Current (CMOS) Cycle Time = 1 µs, CE ≤ 0.2V, II/O = 0 mA, Other pins at 0.2V or VCC - 0.2V 10 mA

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 3Document # SRAM142 REV OR Sym Parameter -55 Unit Min Max tRC Read Cycle Time 55 ns tAA Address Access Time 55 ns tAC Chip Enable Access Time 55 ns tOE Output Enable Access Time 30 ns tLZ Chip Enable to Output in Low-Z 10 ns tOLZ Output Enable to Output in Low-Z 5 ns tHZ Chip Disable to Output in High-Z 20 ns tOHZ Output Disable to Output in High-Z 20 ns tOH Output Hold from Address Change 10 ns tBE Byte Access Time 55 ns tHZBE Byte Disable to High-Z Output 25 ns tLZBE Byte Enable to Low-Z Output 10 ns AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2)

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 4Document # SRAM142 REV OR TIMIng WAVEFORM OF READ CYCLE nO. 1 TIMIng WAVEFORM OF READ CYCLE nO. 2 (OE COnTROLLED)(5,6) notes: 1. Stresses greater than those listed under MAxIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAxIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –2.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address.

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 5Document # SRAM142 REV OR AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -55 Unit Min Max tWC Write Cycle Time 55 ns tAW Address Valid to End of Write 50 ns tCW Chip Enable to End of Write 50 ns tAS Address Setup Time 0 ns tWP Write Pulse Width 45 ns tWR Write Recovery Time 0 ns tDW Data to Write Time Overlap 25 ns tDH Data Hold from End of Write Time 0 ns tOW Output Active from End of Write 5 ns tWZ Write to Output in High-Z 20 ns tBW Byte Enable to End of Write 45 ns TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (CE COnTROLLED)

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 6Document # SRAM142 REV OR TIMIng WAVEFORM OF WRITE CYCLE nO. 2 (BLE OR BHE COnTROLLED) TIMIng WAVEFORM OF WRITE CYCLE nO. 3 (WE COnTROLLED, OE LOW)

Figure 1. Output Load Figure 2. Thevenin Equivalent

• including scope and test fixture.

DOUT to match 639Ω (Thevenin Resistance).

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 8Document # SRAM142 REV OR DATA RETEnTIOn Sym Parameter Test Conditions Min Max Unit VDR VCC for Data Retention CE ≥ VCC - 0.2V, VIN ≥ VCC - 0.2V or VIN ≤ 0.2V 2.0 5.5 V ICCDR Data Retention Current VDR=2.0V 30 µA tCDR Chip Deselect to Data Retention Time See Retention Waveform 0 ns tR Operating Recovery Time tRC ns LOW VCC DATA RETEnTIOn WAVEFORM

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 9Document # SRAM142 REV OR

ORDERIng InFORMATIOn

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 10Document # SRAM142 REV OR TSOP II SMALL OUTLInE PACkAgE Pkg # T2 # Pins 44 Symbol Min Max A 0.039 0.047 A2 0.033 0.045 b 0.012 0.017 D 0.717 0.733 e 0.0315 BSC E 0.453 0.473 E1 0.392 0.408

P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM Page 11Document # SRAM142 REV OR REVISIOnS DOCUMEnT nUMBER SRAM 142 DOCUMEnT TITLE P4C1041L - LOW POWER 256K x 16 STATIC CMOS RAM REV ISSUE DATE ORIgInATOR DESCRIPTIOn OF CHAngE OR Mar-2011 JDB New Data Sheet