P1753-30CMB

PACE1753 PYRAMID | Alldatasheet

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Document # MICRO-4 REV D Revised November 2005 PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO

FEATURES

Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory (10,240 bits) for both the MMU and BPU functions are included on the chip. Designed to interface memory to the PACE1750A/AE 16-bit, 40 MHz processor. Systems can be designed where no WAIT states are required up to 40 MHz clock rates when using these PACE products. System performance and device count are optimized when used with the PACE1754 Processor Interface Circuit (PIC). Provides the following additional functions: — EDAC, Error Detection and Correction—or parity generation and detection — Correct data register—for diagnostics — First memory failing address register — Illegal address error detection— programmable — Multi-Master arbitration 8-bit extended address latches and drivers on chip Information bus and EDAC transceivers on chip 20, 30 and 40 MHz operation over the Military Temperature Range Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range (P D Outputs Open) < 0.20 watts at 20 MHz < 0.30 watts at 30 MHz < 0.40 watts at 40 MHz Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack (Leaded Chip Carrier) MEMORY MANAGEMENT UNIT AND BLOCK PROTECT UNIT “COMBO” — FUNCTIONAL DESCRIPTION The PACE1753 (COMBO) is a support chip for the PACE1750A/AE microprocessor family. It provides the following supporting functions to the system: 1. Memory management and access protection for up to 1M words.

2 Physical memory write protection for up to 1M words

memory in pages of 1K words each. Separate protection is provided for the CPU and for DMA in systems which include DMA. 3. Detection of illegal l/O accesses (as defined by MIL- STD-1750A) or access to an unimplemented block of memory. In each case an error flag is generated to the processor.

4 Detection of double errors on the data bus and

correction of single errors. An error signal is generated to the processor when a multiple error is detected. 5. RDYA generation. Up to three wait states can be inserted in the address phase of the bus by generating a not-ready, RDYA low signal. The number of wait states required can be programmed in an internal register in the COMBO. 6. Bus arbitration for up to 4 masters. Arbitration is done on a fixed priority basis (i.e. by interconnection of hardware). (In 68 pin package only).

Page 2 of 21Document # MICRO-4 REV D ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to V CC + 0.5V Storage Temperature Range –65°C to +150°C Input Current Range –30mA to +5mA Current applied to any output 3 150mA Maximum Power Dissipation2 1.5W Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance (θJC):4 Cases X and T 8°C/W Cases Y and U 5°C/W Case Z 6°C/W Notes 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., I OS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-89505 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array RECOMMENDED OPERATING CONDITIONS Supply Voltage Range 4.5V to +5.5V Case Operating –55°C to +125°C Temperature Range Operating Maximum Power Dissipation (Outputs Open) Device Type 20MHz 0.20W Device Type 30MHz 0.30W Device Type 40MHz 0.40W

Page 3 of 21Document # MICRO-4 REV D DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions 1 VIH Input HIGH Voltage 2.0 V CC + 0.5 V VIL Input LOW Voltage2 –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V V CC = 4.5V, IIN = –18mA 2.4 V V CC = 4.5V, I OH = –8.0mA VCC – 0.2 V V IN = 0.8V, 2.0V I OH = –300µA Output LOW Voltage, 0.5 V V CC = 4.5V, I OL = 8.0mA except EXT ADR0 – EXT ADR7 0.2 V V IN = 0.8V, 2.0V I OL = 300µA Output LOW Voltage, 0.5 V V CC = 4.5V, I OL = 20.0mA EXT ADR0 – EXT ADR7 0.2 V V IN = 0.8V, 2.0V I OL = 300µA Input HIGH Current, IIH except IB0 – IB15,1 0 µ A V IN = VCC, EDC0 – EDC5,V CC = 5.5V EXT ADR0 – EXT ADR7 Input HIGH Current, V IN = VCC, IIH IB0 – IB15, EDC0 – EDC5,5 0 µ A V CC = 5.5V EXT ADR0 – EXT ADR7 Input LOW Current, IIL except IB0 – IB15, –10 µA V IN = GND, EDC0 – EDC5,V CC = 5.5V EXT ADR0 – EXT ADR7 Input LOW Current, V IN = GND, IIL IB0 – IB15, EDC0 – EDC5, –50 µA V CC = 5.5V EXT ADR0 – EXT ADR7 IOZH Output Three-State Current 50 µA V OUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA V OUT = 0.5V, VCC = 5.5V Quiescent Power Supply V IN < 0.2V or < VCC – 0.2V ICCQC Current (CMOS Input 60 mA f = 0MHz, Outputs Open, Levels, Active) V CC = 5.5V Quiescent Power Supply V IN = 3.4V, f = 0MHz, ICCQT Current (TTL Input 110 mA All Inputs, Outputs Open, Levels, Active) V CC = 5.5V Dynamic Power Supply 40 mA F = 20MHz ICCD Current 50 mA F = 30MHz 60 mA F = 40MHz IOS Output Short Circuit Current3 –25 mA V OUT = GND, VCC = 5.5V CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional 15 pF Outputs Only Capacitance (Including I/O Buffers) Notes 2. V IL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. VOH Output HIGH Voltage VOL VOL VCC = 0V to VCC, tr = tf = 2.5 ns, Outputs Open, V CC = 5.5V

Page 4 of 21Document # MICRO-4 REV D AC ELECTRICAL CHARACTERISTICS (VCC = 4.5V)

20 MHz 30MHz 40 MHz

Symbol Parameter Min Max Min Max Min Max Unit TD/I (EXT ADR)V MMU Cache Hit 25 23 23 ns TSTRBD (EXT ADR ERR )L External Address Error 25 20 16 ns TC (IBD CORR) Error Correction Read Cycle 25 20 19 ns IBDV (SING ERR)H Error Correction Read Cycle 35 30 25 ns TC (SING ERR)L Error Correction Read Cycle 25 20 12 ns TIBDV (EDC GEN)V EDAC or Parity Write Cycle 30 25 23 ns TSTRBD (EX RDY)L MMU Cache Miss 25 20 12 ns TC (EX RDY)H MMU Cache Miss 25 20 12 ns TC (WR PROT)L MMU Cache Miss 25 22 18 ns TSTRBDH (WR PROT)H MMU Cache Miss 25 20 16 ns TC (GNT1)H Arbiter LOW to HIGH Priority 35 25 18 ns TC (GNT0)L Arbiter LOW to HIGH Priority 35 25 18 ns TC (GNT0)H Arbiter HIGH to LOW Priority 35 25 18 ns TC (GNT1)L Arbiter HIGH to LOW Priority 35 25 18 ns TC (RDYA) Address Ready 30 25 17 ns TFC (IB OUT) V Clock to IB Out Valid (I/O Read) 30 28 25 ns TIBDIN (MEM PAR ERR ) Parity Mode 34 30 25 ns TC (MEM PRT ERR ) Memory Protect Error 50 45 40 ns TSTRBD (WR PROT) Write Protect Cache Hit 25 20 16 ns TC (WR PROT)L Write Protect Cache Miss 25 22 18 ns TSTRBDH (WR PROT)H Write Protect Cache Miss 25 22 18 ns TD/I (PROT FLAG) Cache Hit (BPU Protection Error) 50 45 40 ns TD/I (PROT FLAG) Cache Hit (MMU Key-Lock Error) 40 35 30 ns TC (PROT FLAG) Cache Miss (BPU Protection Error) 45 35 30 ns TC (PROT FLAG) Cache Hit (MMU Key-Lock Error) 25 20 20 ns TC (EXT ADR) Clock to EXT ADR Valid (Miss) 32 30 23 ns Notes: 2. V IL = –3.0V for pulse widths less than or equal to 20ns. 3. Duration of the short should not exceed one second; only one output may be shorted at a time. 4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width.

Page 5 of 21Document # MICRO-4 REV D TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol

1 GND 23 IB 13 44 AS 1

2 EDC 0 24 IB 14 45 AS 0

3 EDC 1 25 IB 15 46 GND

4 EDC 2 26 MEM PRT ER 47 AK 3

5 RESET 27 MEM PAR ER 48 AK 2

6 EDC 3 28 EXT ADR ER 49 AK 1

7 EDC 4 29 RAM DIS 50 AK 0

8 EDC 5 30 SING ERR 51 CLK

9I B 0 31 DMA ACK 52 STRBA

10 IB 1 32 GND 53 STRBD

11 IB 2 33 EXT ADR 0 54 GND

12 IB 3 34 EXT ADR 1 55 EX RDY

13 IB 4 35 EXT ADR 2 56 WR PROT/PROT FLAG

14 IB 5 36 EXT ADR 3 57 R/ W

15 IB 6 37 EXT ADR 4 58 D/ I

16 IB 7 38 EXT ADR 5 59 M/ IO

17 IB 8 39 EXT ADR 6 60 RDYA

18 IB 9 40 EXT ADR 7 61 NC

19 V CC 41 V CC 62 NC

20 IB 10 42 AS 3 63 NC

21 IB 11 43 AS 2 64 V CC

22 IB 12

Page 6 of 21Document # MICRO-4 REV D Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with Gull- Wing Leads (Case Y) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol

1 GND 24 IB 12 47 AS 1

2 EDC 0 25 IB 13 48 AS 0

3 EDC 1 26 IB 14 49 BUS REQ 2

4 EDC 2 27 IB 15 50 AK 3

5 RESET 28 MEM PRT ERR 51 AK 2

6 EDC 3 29 MEM PAR ERR 52 BUS GNT 1

7 EDC 4 30 EXT ADR ERR 53 AK 1

8 EDC 5 31 RAM DIS 54 AK 0

9 BUS GNT 2 32 SING ERR 55 CLK

10 IB 0 33 DMA ACK 56 STRBA

11 IB 1 34 GND 57 STRBD

12 IB 2 35 V CC 58 BUS REQ 0

13 IB 3 36 EXT ADR 0 59 EX RDY

14 IB 4 37 EXT ADR 1 60 WR PROT/PROT FLAG

15 IB 5 38 EXT ADR 2 61 R/ W

16 IB 6 39 EXT ADR 3 62 D/ I

17 IB 7 40 EXT ADR 4 63 M/ IO

18 BUS REQ 3 41 EXT ADR 5 64 RDYA

19 IB 8 42 EXT ADR 6 65 BUS GNT 0

20 IB 9 43 EXT ADR 7 66 BUS LOCK

21 BUS GNT 3 44 GND 67 BUS REQ 1

22 IB 10 45 AS 3 68 V CC

23 IB 11 46 AS 2

Page 7 of 21Document # MICRO-4 REV D Case Outline: Pin Grid Array (Case Z) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol B1 IB 14 L5 EDC 1 D11 AS 0 B2 IB 13 K5 EDC 0 D10 AS 1 C1 IB 12 L6 GND C11 AS 2 C2 IB 11 K6 V CC C10 AS 3 D1 IB 10 L7 BUS REQ 1 B11 V CC D2 BUS GNT 3 K7 BUS LOCK A10 GND E1 IB 9 L8 BUS GNT 0 B10 EXT ADR 7 E2 IB 8 K8 RDYA A9 EXT ADR 6 F1 BUS REQ 3 L9 M/ IO B9 EXT ADR 5 F2 IB 7 K9 D/ I A8 EXT ADR 4 G1 IB 6 L10 R/ W B8 EXT ADR 3 G2 IB 5 K11 WR PROT/PROT FLAG A7 EXT ADR 2 H1 IB 4 K10 EX RDY B7 EXT ADR 1 H2 IB 3 J11 BUS REQ 0 A6 EXT ADR 0 J1 IB 2 J10 STRBD B6 GND J2 IB 1 H11 STRBA A5 DMA ACK K1 IB 0 H10 CLK B5 SING ERR L2 BUS GNT 2 G11 AK 0 A4 RAM DIS K2 EDC 5 G10 AK 1 B4 EXT ADR ERR L3 EDC 4 F11 BUS GNT 1 A3 MEM PAR ERR K3 EDC 3 F10 AK 2 B3 MEM PRT ERR L4 RESET E11 AK 3 A2 IB 15 K4 EDC 2 E10 BUS REQ 2 TERMINAL CONNECTIONS

Page 8 of 21Document # MICRO-4 REV D Note: All time measurements on active signals relate to 1.5V levels. External Address Error MMU Cache Hit

Page 9 of 21Document # MICRO-4 REV D Note: All time measurements on active signals relate to 1.5V levels. Error Correction (Read Cycle) Ready Address Memory Parity Error Error Correction (Write Cycle) Memory Protect Error

Page 10 of 21Document # MICRO-4 REV D Note: All time measurements on active signals relate to 1.5V levels. * The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT FLAG. (See BPU Description), T = 1 Clock Period. MMU Cache Miss Cycle (WA > 0) MMU Cache Miss Cycle (WA = 0)

Page 11 of 21Document # MICRO-4 REV D Note: All time measurements on active signals relate to 1.5V levels. Bus Arbitrator High Priority to Low Priority Transition Low Priority to High Priority Transition CLK B0 B1 B2 B3 B0 B0 B1 TC (GNT1)H TC (GNT0)L REQ1 GNT1 REQ0 LOCK GNT0

Page 12 of 21Document # MICRO-4 REV D SWITCHING WAVEFORMS AND TEST CIRCUIT (Continued) Standard Output (Non Three-State) Note: All time measurements on active signals relate to 1.5V levels. Parameter V O VMEA TPLZ ≥ 3V 0.5V TPHZ 0V V CC – 0.5V TPXL V CC/2 1.5V TPXH V CC/2 1.5V Three-State IB Bus Output (0:15)

Page 13 of 21Document # MICRO-4 REV D PIN FUNCTIONS Symbol Name Description BUS REQ0 - Bus Request 1 Active LOW inputs that indicate a requirement for the bus from 4 BUS REQ3 masters on the bus. The master assigned to pin BUS-REQ0 has highest priority; the master assigned to pin BUS-REQ3 has lowest priority. BUS LOCK Bus Lock1 An active LOW input that indicates that the one master assigned the bus is using the bus. A new master will receive a bus grant only after this signal becomes inactive. BUS GNT0 - Bus Grant 1 Active LOW outputs indicating which master was granted the BUS GNT3 bus. It remains active during BUS LOCK unless a higher master request occurs, which resets it. However, the higher master will be granted the bus only after the present master’s BUS LOCK releases the bus. M/IO Memory or I/O An input signal that indicates whether the current bus cycle is a memory (HIGH) or l/O (LOW) cycle. D/I Data or Instruction An input signal that indicates whether the current bus cycle access is for data (HIGH) or instruction (LOW). R/W Read or Write An input signal that indicates the direction of data flow on the bus. A HIGH indicates a memory read or input operation into the master and a LOW indicates a memory write or output operation from the master. STRBA Address Strobe An active HIGH input used to latch the address at the HIGH-to- LOW transition of the strobe. STRBD Data Strobe An active LOW input used to strobe data in memory and I/O cycles. CPU-CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) RESET Reset An active LOW input t hat initializes the device. AK 0 - AK3 Access Key Active HIGH inputs used to match the access lock in the MMU page for memory accesses. A mismatch will cause the MEM PRT ERR signal to become active. AS0 - AS3 Address State Active HIGH inputs that select the page register group in the MMU. In the DMA physical demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant bits of the physical address for use in the BPU function. EXT ADR 0 - Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an EXT ADR7 output bus which is used to select one of 256 pages, 4K words each, expanding the direct addressing space to 1M word. In DMA cycles, indicated by DMA-ACK being active, it is also an output bus except when programmed for the physical demultiplexed DMA mode. In this case it becomes an input to receive the 8 most significant bits of the DMA physical address for use in the BPU function. IB 0 - IB15 Information Bus An active HIGH bi-directional time multiplexed address/data bus. IB0 is the most significant bit. EDC0 - EDC5 Detection/Correction An active HIGH bi-directional bus used for detection of errors on Bus the data bus (IB 0 - IB15) and correction of single errors. When working in parity mode EDC0 is the parity bit. EDC0 - EDC5 are undefined in this case.

Page 14 of 21Document # MICRO-4 REV D PIN FUNCTIONS (Continued) Symbol Name Description MEM PRT ERR Memory Protect Error An active LOW output generated by the MMU or BPU blocks to signal to the CPU a protected memory violation. The error is generated in one of the following conditions: a mismatch in the access keys in the MMU page, an access to an execution protected page during instruction cycles, an access to a write-protected page during data cycles, or an access to a page write-protected by the BPU. MEM PAR ERR Memory Parity Error An active LOW output which signals to the CPU an error on the data bus during a memory cycle. Two detection modes can be selected by programming the control register: EDAC mode (6 Hamming code parity bits) or single bit parity mode (even or odd parity). The signal is inactive when none of the above modes are selected (default after Reset). EXT ADR ERR External Address Error An active LOW output which signals to the CPU an unimplemented memory or illegal I/O access. SING ERR Single Error An active HIGH output to signal detection of a single error on the data bus in memory cycles. It is high impedance when the EDAC function is disabled by the program (default state after Reset). RAM DIS RAM-Disable An active HIGH input from the P1754 device which enables the corrected data on the data bus when the EDAC function is enabled. An internal one clock delay is generated before the data is output on the bus to allow external memory to disconnect itself from the bus. EX RDY Data Ready An active HIGH output that indicates that no wait states are requested. It becomes inactive for one clock (inserting one wait state) whenever a memory page different than the current one is accessed (causing a miss). RDYA Address Ready An active HIGH output that indicates that no wait states are requested when STRBA is active. Wait states are inserted when this signal becomes inactive during STRBA. Up to three wait states can be inserted by programming an internal register. Three wait states are inserted after Reset (default). WR PROT/ Write Protected/ Either an active LOW output (following STRBD timing) during legal PROT FLAG Protection Flag memory write cycles, when no protection error occurs, or an active HIGH level indicating a protection error in a write cycle. Each mode can be selected by programming the control register. Default mode after Reset is write-protected. DMA ACK DMA Acknowledge An active HIGH input from the DMA controller which indicates a DMA cycle. Used to select the DMA table in the BPU memory for protection. For example, this could allow the DMA channel to update the program which could be write-protected from the processor. In the physical DMA mode, it will cause the Extended Address Lines (EXT ADR 0-7) to become inputs, providing BPU protection of the DMA transfers. Note: 1. Used for Bus Arbitration; only available on 68-lead devices.

Page 15 of 21Document # MICRO-4 REV D Standardized Military Vendor Vendor similar Drawing PIN CAGE Number PIN 5962-8950501UX 3DTT2 P1753-20QLMB 5962-8950501YX 3DTT2 P1753-20QGMB 5962-8950501ZX 3DTT2 P1753-20PGMB 5962-8950502UX 3DTT2 P1753-30QLMB 5962-8950502YX 3DTT2 P1753-30QGMB 5962-8950502ZX 3DTT2 P1753-30PGMB 5962-8950503UX 3DTT2 P1753-40QLMB 5962-8950503YX 3DTT2 P1753-40QGMB 5962-8950503ZX 3DTT2 P1753-40PGMB 5962-8950504TX 3DTT2 P1753-20GMB 5962-8950504XX 3DTT2 P1753-20CMB 5962-8950505TX 3DTT2 P1753-30GMB 5962-8950505XX 3DTT2 P1753-30CMB 5962-8950506TX 3DTT2 P1753-40GMB 5962-8950506XX 3DTT2 P1753-40CMB

ORDERING INFORMATION

Page 16 of 21Document # MICRO-4 REV D CASE OUTLINE X:

64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C)

NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. Inches mm .002 0.05 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.40 .018 0.45 .025 0.63 .040 1.01 .050 1.27 .185 4.70 .265 6.73 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .645 16.38 1.550 39.37 1.563 39.70

Page 17 of 21Document # MICRO-4 REV D CASE OUTLINE T:

64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G)

NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Inches mm .001 0.03 .003 0.08 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.41 .022 0.55 .030 0.76 .040 1.01 .050 1.27 .150 3.81 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .868 22.04 1.663 42.24

Page 18 of 21Document # MICRO-4 REV D CASE OUTLINE U:

68 Lead Quad Pack with Straight Leads (Ordering Code QL)

NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched may be either notched or square. Inches mm .002 0.05 .004 0.10 .006 0.15 .010 0.25 .012 0.30 .020 0.51 .050 1.27 .100 2.54 .116 2.95 .250 6.40 .560 14.22 .570 14.48 .800 20.32 .955 24.25 1.090 27.69

Page 19 of 21Document # MICRO-4 REV D CASE OUTLINE Y:

68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)

NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. 5) Corners indicated as notched my be either notched or square (with radius). 6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Inches mm .004 0.10 .005 0.12 .008 0.20 .010 0.25 .012 0.30 .015 0.38 .016 0.41 .020 0.50 .024 0.60 .040 1.02 .050 1.27 .100 2.54 .115 2.92 .570 14.48 .800 20.32 .955 24.25 1.010 25.65 1.090 27.68

Page 20 of 21Document # MICRO-4 REV D CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Inches mm .016 0.41 .020 0.50 .040 1.01 .050 1.27 .059 1.49 .060 1.52 .098 2.49 .100 2.54 .120 3.04 .150 3.81 .170 4.32 1.010 25.65 1.089 27.66 1.160 29.46

Page 21 of 21Document # MICRO-4 REV D REVISIONS DOCUMENT NUMBER: MICRO-4 DOCUMENT TITLE : PACE1753 CMOS MMU/COMBO REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version C Oct-05 JDB Altered case outline drawing for case X and case T D 11/15/05 JDB Removed Commercial Temp