PACE1754 PYRAMID | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Document # MICRO-5 REV C Revised November 2005 PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC)
FEATURES
The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations. Provides a significant savings in part-count and power dissipation enhancing reliability and overall system speed performance. Provides an optimal interface when used with the PACE1753 MMU/COMBO in a full 1750A implementation. Provides the following additional important system functions: — Programmable READY for memory and I/O — Automatic READY during self-test and internal I/O instructions — 100KHz timer clock output provided — Programmable system watchdog—ranges from 1 µs to 1 minute — Programmable Bus time-out function — Memory Parity generation/detection — Error detection of unimplemented memory and/or I/O space addressing — First failing memory address register for diagnostics — High drive three-state address latches — Built-in system test program—automatically tests the PACE1750A/AE CPU, PACE1753 MMU/COMBO, PACE1754 PIC and system address lines as well as memory and I/O strobes — System configuration decoding and buffering — Interrupt acknowledge decoder and strobe — Start up ROM support per MIL-STD-1750A — Memory or I/O READ/WRITE three-state strobes with external three-state control for DMA applications 20, 30 and 40 MHz operation over full Military Temperature Range Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range < 0.25 watts at 20 MHz < 0.30 watts at 30 MHz < 0.35 watts at 40 MHz Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack PACE1754 PROCESSOR INTERFACE CIRCUIT DESCRIPTION The PACE1754 Processor Interface Circuit (PIC) is a single chip implementation of many special system functions that are often required when using the PACE1750A/AE, single chip, 40MHz CMOS Microprocessor. The PIC allows a system designer to design a higher performance, more effecient microprocessor system which uses less power and takes up less board space than was previously possible. In addition to providing significant savings in part count and power dissipation the PIC uses only a 5V ±10%, single supply and operates at 20, 30 and 40 MHz over the fully Military Temperature Range. The PIC provides many important system functions. These functions are governed by respective bit positions in a programmable Control Register which is incorporated in the PIC. The individual bits of the control register are set to select the various features and are set to a specified default value upon Reset.
Page 2 of 20Document # MICRO-5 REV C ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to V CC + 0.5V Storage Temperature Range –65°C to +150°C Input Current Range –30mA to +5mA Current applied to any output 3 150mA Maximum Power Dissipation2 1.5W Lead Temperature Range (soldering 10 seconds) 300°C Thermal resistance (θJC):4 Cases X and T 8°C/W Cases Y and U 5°C/W Case Z 6°C/W Notes: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., I OS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-88642 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array RECOMMENDED OPERATING CONDITIONS Case Temperature GND V CC –55°C to +125°C 0 4.5V to +5.5V
Page 3 of 20Document # MICRO-5 REV C DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions 1 VIH Input HIGH Voltage 2.0 V CC + 0.5 V VIL Input LOW Voltage –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V V CC = 4.5V, IIN = –18mA 2.4 V V CC = 4.5V, I OH = –8.0mA VCC – 0.2 V V IN = 0.8V, 2.0V I OH = –300µA Output LOW Voltage, 0.5 V V CC = 4.5V, I OL = 8.0mA except A0 – A15 0.2 V V IN = 0.8V, 2.0V I OL = 300µA Output LOW Voltage, 0.5 V V CC = 4.5V, I OL = 20.0mA A0 – A15 0.2 V V IN = 0.8V, 2.0V I OL = 300µA Input HIGH Current, IIH except IB0 – IB15, parity/IB16,1 0 µ A V IN = VCC, SING ERR, A0/EXT AD0,V CC = 5.5V A1/EXT AD1, STRBA Input HIGH Current, V IN = VCC, IIH IB0 – IB15, parity/IB16,5 0 µ A V CC = 5.5V A0/EXT AD0, A1/EXT AD1 Input HIGH Current, V IN = VCC, STRBA, SING ERR V CC = 5.5V Input LOW Current, IIL except IB0 – IB15, parity/IB16, –10 µA V IN = GND, SING ERR, A0/EXT AD0,V CC = 5.5V A1/EXT AD1, STRBD, TEST ON Input LOW Current, V IN = GND, IIL IB0 – IB15, parity/IB16, SING ERR, –50 µA V CC = 5.5V A0/EXT AD0, A1/EXT AD1 Input LOW Current, V IN = GND, STRBD, TEST ON VCC = 5.5V IOZH Output Three-State Current 50 µA V OUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA V OUT = 0.5V, VCC = 5.5V Quiescent Power V IN < 0.2V or > VCC – 0.2V ICCQC Supply Current 10 mA f = 0MHz, Outputs Open, (CMOS Input Levels) V CC = 5.5V Quiescent Power V IN = 3.4V, f = 0MHz, ICCQT Supply Current 50 mA All Inputs, Outputs Open, (TTL Input Levels) V CC = 5.5V Dynamic Power f = 20MHz 40 mA V IN = 0V to VCC, ICCD Supply Current f = 30MHz 50 mA tr = tf = 2.5 ns typ., f = 40MHz 60 mA Outputs Open, V CC = 5.5V IOS Output Short Circuit Current2 –25 mA V OUT = GND, VCC = 5.5V CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional 15 pF Outputs Only Capacitance (Including I/O Buffers) Notes: 2. Duration of the short should not exceed one second; only one output may be shorted at a time. VOH Output HIGH Voltage VOL VOL IIL –500 µA IIH 500 µA
Page 4 of 20Document # MICRO-5 REV C AC ELECTRICAL CHARACTERISTICS1, 2 (VCC = 5V ± 10% Over Recommended Operating Conditions)
20 MHz 30MHz 40 MHz
Symbol Parameter Min Max Min Max Min Max Unit tEX RDY (RDYD)V Time from External Ready to 16 14 12 ns Ready Data Valid tC (RDYD)V Time from Clock Read to 28 22 16 ns Ready Data Valid tSTRBAH (A)V Time from Strobe Address HIGH to 29 21 19 ns Address Bus Valid tIBAV (A)V Time from Information Bus Address to 31 22 20 ns Address Bus Valid tFC (R)L Time from Falling Clock to 24 18 12 ns Read LOW tSTRBDH (R)H Time from Strobe Data HIGH to 24 18 12 ns Read HIGH tSTRBDL (W)L Time from Strobe Data LOW to 26 20 15 ns Write LOW tSTRBDH (W)H Time from Strobe Data HIGH to 26 20 15 ns Write HIGH tIBDIN (ME PA ER)L Time from Information Bus Data into 22 17 12 ns Memory Parity Error LOW tIBAIN (EX AD ER) Time from Information Bus Address into 30 25 20 ns External Address Error tSTRBDL – Time from Strobe Data LOW to 26 20 15 ns (STRT ROM)V Start-up ROM Valid tFC (IB OUT)V Time from Falling Clock to 30 25 25 ns Information Bus Valid tC (TIMER CLK) Time from Rising Edge of Clock to 30 25 20 ns Timer Clock tIB INV (IB16) Time from Information Bus Data to 25 20 18 ns Parity Valid tEXT AD (CLKB3) Extended Address 10 10 10 ns Setup Time tEX RDY1 (RDYD)V Time from External Ready Data to 28 24 21 ns Ready Data Valid tFC (SCR EN) Time from Falling Clock to SCR Enable; 30 24 24 ns Case Types T and X only tSTRBDH (SCR EN) Time from STRBD HIGH to SCR Enable; 30 24 24 ns Case Types T and X only Notes: 2. All measurements of delay times on active signals are related to the 1.5V levels.
Page 5 of 20Document # MICRO-5 REV C Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol
1 GND 23 IB 13 45 A 3
2 SCR EN 24 IB 14 46 GND
3 TEST ON 25 IB 15 47 A 2
4V CC 26 IB 16 48 A 1/EXT AD1
5 RESET 27 ME PA ER/RAM DIS 49 A 0/EXT AD0
6 TEST END 28 EX AD ER/SING ERR 50 TC
7 TIMER CLK 29 INTA 51 CPU CLK
8 EX RDY 1 30 STRT ROM 52 STRBA
10 IB 1 32 GND 54 STRB EN
11 IB 2 33 A 15 55 EX RDY
12 IB 3 34 A 14 56 RDYD
13 IB 4 35 A 13 57 R/ W
14 IB 5 36 A 12 58 GND
15 IB 6 37 A 11 59 M/ IO
16 IB 7 38 A 10 60 MEMW
17 IB 8 39 A 9 61 MEMR
18 IB 9 40 A 8 62 IOW
19 GND 41 A 7 63 IOR
20 IB 10 42 A 6 64 V CC
21 IB 11 43 A 5
22 IB 12 44 A 4
Page 6 of 20Document # MICRO-5 REV C Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with Gull- Wing Leads (Case Y) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol
1 GND 24 IB 12 47 A 3
3 SC1 26 IB 14 49 A 2
4 TEST ON 27 IB 15 50 A 1/EXT AD1
5 RESET 28 PARITY/IB 16 51 A 0/EXT AD0
6 TEST END 29 ME PA ER/RAM DIS 52 SC 4
7 TIMER CLK 30 EX AD ER/SING ERR 53 SC 3
9V CC 32 STRT ROM 55 CPU CLK
10 IB 0 33 V CC 56 STRBA
11 IB 1 34 GND 57 STRBD
12 IB 2 35 A 15 58 STRB EN
13 IB 3 36 A 14 59 EX RDY
14 IB 4 37 A 13 60 RDYD
15 IB 5 38 A 12 61 R/ W
16 IB 6 39 A 11 62 GND
17 IB 7 40 A 10 63 M/ IO
18 EX RDY 1 41 A 9 64 MEMW
19 IB 8 42 A 8 65 MEMR
20 IB 9 43 A 7 66 IOW
21 GND 44 A 6 67 IOR
22 IB 10 45 A 5 68 V CC
23 IB 11 46 A 4
Page 7 of 20Document # MICRO-5 REV C Case Outline: Pin Grid Array (Case Z) Terminal Terminal Terminal Terminal Terminal Terminal Number Symbol Number Symbol Number Symbol B1 V CC L5 SC 1 D11 A 3 B2 IB 14 K5 SC 0 D10 A 4 C1 IB 13 L6 V CC C11 A 5 C2 IB 12 K6 IOR C10 A 6 D1 IB 11 L7 IOW B11 A 7 D2 IB 10 K7 MEMR A10 GND E1 IB 9 L8 MEMW B10 A 8 E2 IB 8 K8 M/ IO A9 A 9 F1 EX RDY 1 L9 GND B9 A 10 F2 IB 7 K9 R/ W A8 A 11 G1 IB 6 L10 RDYD B8 A 12 G2 IB 5 K11 EX RDY A7 A 13 H1 IB 4 K10 STRB EN B7 A 14 H2 IB 3 J11 STRBD A6 A 15 J1 IB 2 J10 STRBA B6 GND J2 IB 1 H11 CPU CLK A5 V CC K1 IB 0 H10 TC B5 STRT ROM L2 GND G11 SC 3 A4 INTA K2 SC 2 G10 SC 4 B4 EX AD ER L3 TIMER CLK F11 A 0/EXT AD0 A3 ME PA ER K3 TEST END F10 A 1/EXT AD1 B3 PARITY/IB 16 L4 RESET E11 A 2 A2 IB 15 K4 TEST ON E10 GND TERMINAL CONNECTIONS
Page 8 of 20Document # MICRO-5 REV C STRT ROM Timer Clk IB Bus Output (0:15) EX AD ER Note: All time measurements on active signals relate to 1.5V levels. Extended Addresses (0:1)
Page 9 of 20Document # MICRO-5 REV C RDYD Timing TEST END Timing1 Notes: 1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two fetch cycles from the "old PC" (from addresses XXXX & XXXX+1). The data will be taken from system memory (because TEST END is asserted) but both the address and data are irrelevent. Following that, IC will start filling the pipe from address 0000 hex a nd 0001 hex, now from the system memory to start user's program execution. 2. All time measurements on active signals relate to 1.5V levels.
Page 10 of 20Document # MICRO-5 REV C Note: All time measurements on active signals relate to 1.5V levels. Address Bus and Strobes
Page 11 of 20Document # MICRO-5 REV C Note: All time measurements on active signals relate to 1.5V levels. Parameter V O VMEA TPLZ ≥ 3V 0.5V TPHZ 0V V CC – 0.5V TPXL V CC/2 1.5V TPXH V CC/2 1.5V TEST CIRCUITS Standard Output (Non Three-State) Three-State
Page 12 of 20Document # MICRO-5 REV C PIN FUNCTIONS Symbol Name Description CPU CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) STRBA Strobe Address An active HIGH input which latches the contents of IB(0:15) into the address latches. STRBD Strobe Data An active LOW input which is used for writing or reading data to or from the device and also to produce the external memory and I/O strobes. TIMER CLK Timer Clock A 100KHz output (fixed frequency) based on the programmed operating frequency of the CPU clock. MEMW Memory Write Strobe An active LOW output produced in memory write cycles. MEMR Memory Read Strobe An active LOW output produced in memory read cycles. IOW I/O Write Strobe An active LOW output produced in output write cycles. IOR I/O Read Strobe An active LOW output produced in input read cycles. INTA Interrupt Acknowledge An active LOW output produced after any interrupt, corresponding to Strobe an output write to address 1000 (hex). SCR EN System Configuration An active LOW output (in 64 pin only) produced any time an input read from address 8410 (hex), read system configuration is executed. STRB EN Strobe Enable An active LOW input, enabling the active state of the address outputs and the MEMR, MEMQ, IOR, and IOW outputs. When at a logic "1" (if enabled by bits EST, EAD of the control register) it will correspondingly enable the three-state state of the above signals. IB 0 - IB15 Information Bus (0:15) A bi-directional time multiplexed bus. It is an input during the address phase of any bus cycle and also during the data phase when writing. It is an output during the data phase when reading from the device. IB 16 Information Bus (16) A bi-directional line. It is an output during write cycles and an input during read cycles. It is used to implement the parity function at the system level. A(0:1)/ Address Bus (0:15) An active HIGH output bus. Contains the address of the current bus EX AD(0:1), cycle as latched by the end of STRBA. In system configurations A(2:15) including the MMU function, the only active lines during memory are A(4:15). In this case, A(2:3) are high impedance (don't care) and A(0:1) turn into inputs called Extended Addresses, EXT ADR (0:1). In this case, these two lines supplied by the MMU, will be used to operate the programmable ready generation during bus cycles. M/IO Memory I/O An input qualifier indicating the nature of the current bus cycle.
Page 13 of 20Document # MICRO-5 REV C PIN FUNCTIONS (Continued) Symbol Name Description R/W Read or Write An input qualifier indicating the nature of the current bus cycle, either Read (1) or Write (0). RESET External Reset An active LOW input used to initialize the device's hardware. TEST ON System Test Enable An active LOW input used to enable the execution of the System Test built into the device, immediately after completion of the P1754 initialization and before fetching any instruction from the user program. TEST END System Test End An active HIGH output indicating whether the system test in the device has been completed. Whenever the system test is disabled by the TEST ON signal, the TEST END output will be at a logical "1" immediately after RESET is removed. STRT ROM Start Up ROM An output following the execution of the ESUR and DSUR, I/O commands as defined in MIL-STD-1750A. It will be at the logical "1" level after executing ESUR and at the logical "0" level after executing DSUR. Initially, it defaults to a logical "1". RDYD Ready Data An active HIGH output to be connected to the P1750A/AE CPU input to control the bus cycle termination. EX RDY External Ready Data An active HIGH input which at logical "0" overrides the internal RDYD generation and forces it to a logical "0". EX RDY1 External Ready Data An active LOW input which at logical "1" overrides the internal RDYD generation and forces it to a logical "0". ME PA ER/ Memory Parity Error An active LOW output indicating a parity error when reading from RAM DIS memory. It becomes an active HIGH output called RAM DISABLE for handshaking with the P1753 MMU when the device is programmed to support EDAC. EX AD ER/ Illegal Address Error An active LOW output indicating an illegal address error when SING ERR referencing memory or I/O. It becomes an active HIGH output called SINGLE ERROR for handshaking with the P1753 MMU when the device is programmed to support EDAC. TC Terminal Count An active HIGH output indicating a Bus time out or a watchdog trigger. SC 0–SC4 System Configuration Inputs (for case outlines U, Y, and Z only) which are buffered onto IB0–IB4 when executing an I/O read from I/O address 8410 (hex), system configuration. GND Ground 0 volts system ground. VCC Power Supply 5 volts ± 10% power supply. Case U: Leaded Chip Carrier with Unformed Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case Z: Pin Grid Array
Page 14 of 20Document # MICRO-5 REV C Standardized Military Vendor Vendor similar Drawing PIN CAGE Number PIN 5962-8864201UX 3DTT2 P1754-20QLMB 5962-8864201YX 3DTT2 P1754-20QGMB 5962-8864201ZX 3DTT2 P1754-20PGMB 5962-8864202UX 3DTT2 P1754-30QLMB 5962-8864202YX 3DTT2 P1754-30QGMB 5962-8864202ZX 3DTT2 P1754-30PGMB 5962-8864203UX 3DTT2 P1754-40QLMB 5962-8864203YX 3DTT2 P1754-40QGMB 5962-8864203ZX 3DTT2 P1754-40PGMB 5962-8864204TX 3DTT2 P1754-20GMB 5962-8864204XX 3DTT2 P1754-20CMB 5962-8864205TX 3DTT2 P1754-30GMB 5962-8864205XX 3DTT2 P1754-30CMB 5962-8864206TX 3DTT2 P1754-40GMB 5962-8864206XX 3DTT2 P1754-40CMB
ORDERING INFORMATION
Page 15 of 20Document # MICRO-5 REV C CASE OUTLINE X:
64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C)
NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. Inches mm .002 0.05 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.40 .018 0.45 .025 0.63 .040 1.01 .050 1.27 .185 4.70 .265 6.73 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .645 16.38 1.550 39.37 1.563 39.70
Page 16 of 20Document # MICRO-5 REV C CASE OUTLINE T:
64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G)
NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Inches mm .001 0.03 .003 0.08 .005 0.12 .008 0.20 .010 0.25 .015 0.38 .016 0.41 .022 0.55 .030 0.76 .040 1.01 .050 1.27 .150 3.81 .470 11.93 .530 13.46 .590 14.98 .620 15.74 .868 22.04 1.663 42.24
Page 17 of 20Document # MICRO-5 REV C CASE OUTLINE U:
68 Lead Quad Pack with Straight Leads (Ordering Code QL)
NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) Corners indicated as notched may be either notched or square. Inches mm .002 0.05 .004 0.10 .006 0.15 .010 0.25 .012 0.30 .020 0.51 .050 1.27 .100 2.54 .116 2.95 .250 6.40 .560 14.22 .570 14.48 .800 20.32 .955 24.25 1.090 27.69
Page 18 of 20Document # MICRO-5 REV C CASE OUTLINE Y:
68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)
NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner . 5) Corners indicated as notched my be either notched or square (with radius). 6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Inches mm .004 0.10 .005 0.12 .008 0.20 .010 0.25 .012 0.30 .015 0.38 .016 0.41 .020 0.50 .024 0.60 .040 1.02 .050 1.27 .100 2.54 .115 2.92 .570 14.48 .800 20.32 .955 24.25 1.010 25.65 1.090 27.68
Page 19 of 20Document # MICRO-5 REV C CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Inches mm .016 0.41 .020 0.50 .040 1.01 .050 1.27 .059 1.49 .060 1.52 .098 2.49 .100 2.54 .120 3.04 .150 3.81 .170 4.32 1.010 25.65 1.089 27.66 1.160 29.46
Page 20 of 20Document # MICRO-5 REV C REVISIONS DOCUMENT NUMBER: MICRO-5 DOCUMENT TITLE: PACE1754 PIC BULK CMOS REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-cr eated electronic version C 11/15/05 JDB Removed Commercial Temperature Range