P4C1023-70CMB

P4C1023 PYRAMID | Alldatasheet

Document overview

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Technical content

Document # SRAM126 REV OR Revised October 2005 P4C1023/P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM locations are specified on address pins A0 to A16. Read- ing is accomplished by device selection ( CE low) and output enabling (OE) while write enable ( WE) remains HIGH. By presenting the address under these condi- tions, the data in the addressed memory location is pre- sented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE is HIGH or WE is LOW. The P4C1023L is packaged in a 32-pin 400 or 600 mil ceramic DIP and in a 32-pin ceramic SOJ. The P4C1023L is a 1 Megabit low power CMOS static RAM organized as 128K x 8. The CMOS memory re- quires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1023L device provides asynchronous opera- tion with matching access and cycle times. Memory Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 400 or 600 mil Ceramic DIP —32-Pin Ceramic SOJ V CC Current — Operating: 35mA — CMOS Standby: 100µA Access Times —55/70 ns Single 5 Volts ±10% Power Supply Easy Memory Expansion Using CECECECECE and OEOEOEOEOE Inputs

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (C10, C11), CERAMIC SOJ (CJ1) TOP VIEW

Page 2 of 11Document # SRAM126 REV OR GND ≤ VIN ≤ VCC Comm. Industrial Military I LO RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the opera- tional sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Temperature Range (Ambient) Supply Voltage 4.5V ≤ VCC ≤ 5.5V Industrial (-40°C to 85°C) 4.5V ≤ VCC ≤ 5.5V Commercial (0°C to 70°C) Symbol Parameter Min Max Unit VCC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current >200 mA Storage Temperature Symbol Parameter VOH VOL VIH VIL ILI ISB ISB1 Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage VCC Current CMOS Standby Current (CMOS Input Levels) V CC Current TTL Standby Current (TTL Input Levels) Output Leakage Current Input Leakage Current IOH = –1mA, VCC = 4.5V IOL = 2.1mA VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL GND ≤ VOUT ≤ VCC Comm. CE1 ≥ VIH or CE2 ≤ VIL Industrial Military Test Conditions Min Max Unit 2.4 2.2 -0.3 -10 -10 V V V V µA µA mA µA 0.4 V CC + 0.3 0.8 +10 +10 100 Military (-55°C to 125°C) 4.5V ≤ VCC ≤ 5.5V

Page 3 of 11Document # SRAM126 REV OR Note 1 - Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) POWER DISSIPATION CHARACTERISTICS VS. SPEED AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter Test Conditions Max Unit CIN COUT Input Capacitance Output Capacitance VIN = 0V VOUT = 0V pF pF Symbol Parameter Unit Dynamic Operating Current Commercial Industrial Military mA -55 -70 Temperature Range Symbol Parameter -55 Min Max -70 Min Max Unit tRC 55 ns tAA Address Access Time 55 70 ns tAC Chip Enable Access Time 55 70 ns tOH Output Hold from Address Change 55 ns tLZ Chip Enable to Output in Low Z 10 10 ns tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 30 35 ns tOLZ Output Enable Low to Low Z 55 ns tOHZ Output Enable High to High Z 20 25 ns tPU Chip Enable to Power Up Time 00 ns tPD Chip Disable to Power Down Time 55 70 ns Read Cycle Time 70 Note 1 ICC

Page 4 of 11Document # SRAM126 REV OR Notes: 1. WE is HIGH for READ cycle. 2. CE and OE are LOW for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE transition LOW. READ CYCLE NO. 1 (OEOEOEOEOE CONTROLLED)(1) READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CECECECECE CONTROLLED) 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address.

Page 5 of 11Document # SRAM126 REV OR -55 Notes: 6. CE and WE are LOW for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. Write Cycle Time is measured from the last valid address to the first transitioning address. AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) WRITE CYCLE NO. 1 (WEWEWEWEWE CONTROLLED)(6) Symbol Parameter Max -70 Max UnitMin Min tWC tCW tAS tWP tAH tDH tWZ tOW Write Cycle Time 55 70 ns Chip Enable Time to End of Write 50 60 ns Address Valid to End of Write 50 60 ns Address Set-up Time 00 n s Write Pulse Width 40 50 ns Address Hold Time 00 n s Data Valid to End of Write 25 30 ns Data Hold Time 00 n s Write Enable to Output in High Z 25 30 ns Output Active from End of Write 55 n s tAW tDW

Page 6 of 11Document # SRAM126 REV OR Write ActiveRead TIMING WAVEFORM OF WRITE CYCLE NO.2 (CECECECECE CONTROLLED)(6) * including scope and test fixture. Note: Because of the high speed of the P4C1023L, care must be taken when testing this device; an inadequate setup can cause a normal function- ing part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50 Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589Ω resistor must be used in series with D OUT to match 639 Ω (Thevenin Resistance). AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2 Mode Standby DOUT Disabled Standby PowerI/OWEWEWEWEWEOEOEOEOEOECECECECECE High Z DOUT DIN X H H L X H L X H L L L Active Active High Z

Page 7 of 11Document # SRAM126 REV OR DATA RETENTION LOW VCC DATA RETENTION WAVEFORM Symbol Parameter Test Conditions Unit MaxMin VDR ICCDR VCC for Data Retention Data Retention Current CE ≥ VCC -0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V 2.0 5.5 V VDR = 2.0V VDR = 3.0V 50 µA 100 µA tR Operating Recovery Time Chip Deselect to Data Retention Time See Retention Waveform tRC ns nstCDR

Page 8 of 11Document # SRAM126 REV OR SELECTION GUIDE The P4C1023L is available in the following temperature, speed and package options.

ORDERING INFORMATION

Side Brazed DIP (400 mil) -55CC -70CC Side Brazed DIP (600 mil) -55CWC -70CWC Ceramic SOJ -55CJC -70CJC Side Brazed DIP (400 mil) -55CI -70CI Side Brazed DIP (600 mil) -55CWI -70CWI Ceramic SOJ -55CJI -70CJI Side Brazed DIP (400 mil) -55CM -70CM Side Brazed DIP (600 mil) -55CWM -70CWM Ceramic SOJ -55CJM -70CJM Side Brazed DIP (400 mil) -55CMB -70CMB Side Brazed DIP (600 mil) -55CWMB -70CWMB Ceramic SOJ -55CJMB -70CJMB Speed (ns )Temperature Range Package Military Processed* Military Temperature Industrial Commercial

Page 9 of 11Document # SRAM126 REV OR Pkg # # Pins Symbol Min Max A- 0 . 2 2 5 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D- 1 . 6 8 0 E 0.510 0.620 eA e L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 -

0.600 BSC

0.100 BSC

32 (600 mil) SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol Min Max A- 0 . 2 3 2 b 0.014 0.023 b2 0.038 0.065 C 0.008 0.018 D- 1 . 7 0 0 E 0.350 0.410 eA e L 0.125 0.200 Q 0.015 0.060 S1 0.005 - S2 0.005 - C11 32 (400 mil)

0.400 BSC

SIDEBRAZED DUAL IN-LINE PACKAGE

Page 10 of 11Document # SRAM126 REV OR CERAMIC SOJ SMALL OUTLINE IC PACKAGEPkg # # Pins Symbol Min Max A 0.120 0.165 A1 0.088 0.120 A2 0.070 REF B0 . 0 1 0 R E F B1 0.030R TYP B2 0.020 REF B3 0.025 0.045 D 0.816 0.838 D1 0.750 REF E 0.419 0.431 E1 0.430 0.445 E2 0.360 0.380 e e1 0.038 TYP e2 0.005 j0 . 0 0 5 T Y P S 0.030 0.040 S1 0.020 TYP CJ1

0.050 BSC

Page 11 of 11Document # SRAM126 REV OR REVISIONS DOCUMENT NUMBER: SRAM126 DOCUMENT TITLE: P4C1023 / P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE OR Oct-05 JDB New Data Sheet