P3C1256L

P3C1256L PYRAMID | Alldatasheet

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Technical content

Document # SRAM143 REV A Revised October 2011 P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM

FEATURES

VCC Current (Commercial/Industrial) — Operating: 70mA/85mA — CMOS Standby: 100µA/100µA Access Times —55/70/85 Wide Range Power Supply: 2.7V to 3.6V Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages — 28-Pin 600 mil DIP — 28-Pin 330 mil SOP — 28-Pin TSOP FUnCTIOnAL BLOCk DIAgRAM PIn COnFIgURATIOnS DIP (P6), SOP (S11-3) TOP VIEW

DESCRIPTIOn

The P3C1256L is a 262,144-bit low power CMOS static RAM organized as 32Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates with a wide range power supply (2.7V to 3.6V). Access times of 55 ns and 70 ns are available. CMOS is utilized to reduce power consumption to a low level. The P3C1256L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading is accom- plished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW.

P3C1256L - 32K x 8 STATIC CMOS RAM Page 2Document # SRAM143 REV A DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) MAxIMUM RATIngS(1) RECOMMEnDED OPERATIng TEMPERATURE AnD SUPPLy VOLTAgE Sym Parameter Test Conditions Min Max Unit VOH Output High Voltage (I/O0 - I/O7) IOH = -1mA, VCC = 3.0V 2.4 V VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA 0.4 V VIH Input High Voltage 2.2 VCC + 0.3 V VIL Input Low Voltage -0.5(3) 0.8 V ILI Input Leakage Current GND ≤ VIN ≤ VCC Com -2 +2 µAInd -5 +5 Mil ILO Output Leakage Current GND ≤ VOUT ≤ VCC CE = VIH Com -2 +2 µAInd -5 +5 Mil ISB VCC Current TTL Standby Current (TTL Input Levels) VCC = 3.6V, IOUT = 0 mA CE = VIH 3 mA ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 3.6V, IOUT = 0 mA CE ≥ VCC - 0.2V 100 µA N/A = Not applicable Sym Parameter Min Max Unit VCC Supply Voltage with Respect to GND -0.5 7.0 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) -0.5 VCC + 0.5 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 25 mA ILAT Latch-up Current > 200 mA Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 2.7V ≤ VCC ≤ 3.6V Industrial (-40°C to 85°C) 2.7V ≤ VCC ≤ 3.6V Military (-55°C to 125°C) 2.7V ≤ VCC ≤ 3.6V

P3C1256L - 32K x 8 STATIC CMOS RAM Page 3Document # SRAM143 REV A CAPACITAnCES(4) (VCC = 3.3V, TA = 25°C, f = 1.0MHz) Symbol Parameter Test Conditions Max Unit CIN Input Capacitance VIN=0V 7 pF COUT Output Capacitance VOUT=0V 9 pF POWER DISSIPATIOn CHARACTERISTICS VS. SPEED Sym Parameter Temperature Range * ** Unit ICC Dynamic Operating Current* Commercial 70 70 70 15 15 15 mA Industrial 85 85 85 25 25 25 mA Military 100 100 100 35 35 35 mA * Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. ** As above but @ f=1 MHz and VIL/VIH = 0V/VCC. Sym Parameter -55 -70 -85 Unit Min Max Min Max Min Max tRC Read Cycle Time 55 70 85 ns tAA Address Access Time 55 70 85 ns tAC Chip Enable Access Time 55 70 85 ns tOH Output Hold from Address Change 5 5 5 ns tLZ Chip Enable to Output in Low Z 5 5 5 ns tHZ Chip Disable to Output in High Z 20 25 30 ns tOE Output Enable Low to Data Valid 30 35 40 ns tOLZ Output Enable Low to Low Z 5 5 5 ns tOHZ Output Enable High to High Z 20 25 30 ns tPU Chip Enable to Power Up Time 0 0 0 ns tPD Chip Disable to Power Down Time 55 70 85 ns AC ELECTRICAL CHARACTERISTICS—READ CyCLE (Over Recommended Operating Temperature & Supply Voltage)

P3C1256L - 32K x 8 STATIC CMOS RAM Page 4Document # SRAM143 REV A TIMIng WAVEFORM OF READ CyCLE nO. 1 (OE COnTROLLED)(5) TIMIng WAVEFORM OF READ CyCLE nO. 2 (ADDRESS COnTROLLED)(5,6) notes: 1. Stresses greater than those listed under MAxIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAxIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address. TIMIng WAVEFORM OF READ CyCLE nO. 3 (ADDRESS COnTROLLED)(5,7)

P3C1256L - 32K x 8 STATIC CMOS RAM Page 5Document # SRAM143 REV A AC CHARACTERISTICS—WRITE CyCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -55 -70 -85 Unit Min Max Min Max Min Max tWC Write Cycle Time 55 70 85 ns tCW Chip Enable Time to End of Write 50 60 75 ns tAW Address Valid to End of Write 50 60 75 ns tAS Address Setup Time 0 0 0 ns tWP Write Pulse Width 40 50 60 ns tAH Address Hold Time 0 0 0 ns tDW Data Valid to End of Write 25 30 35 ns tDH Data Hold Time 0 0 0 ns tWZ Write Enable to Output in High Z 25 30 35 ns tOW Output Active from End of Write 5 5 5 ns TIMIng WAVEFORM OF WRITE CyCLE nO. 1 (WE COnTROLLED)(10,11) Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first transitioning address.

Figure 1. Output Load Figure 2. Thevenin Equivalent

• including scope and test fixture.

DOUT to match 639Ω (Thevenin Resistance).

P3C1256L - 32K x 8 STATIC CMOS RAM Page 7Document # SRAM143 REV A DATA RETEnTIOn CHARACTERISTICS DATA RETEnTIOn WAVEFORM Sym Parameter Test Conditions Min Typ.* VCC = Max VCC = Unit 2.0V 3.0V 2.0V 3.0V VDR VCC for Data Retention 2.0 V ICCDR Data Retention Current CE ≥ VCC - 0.2V, VIN ≥ VCC - 0.2V or VIN ≤ 0.2V 10 15 80 120 µA tCDR Chip Deselect to Data Reten- tion Time 0 ns tR † Operation Recovery Time tRC § ns * TA = +25°C tRC § = Read Cycle Time † = This parameter is guaranteed but not tested.

P3C1256L - 32K x 8 STATIC CMOS RAM Page 8Document # SRAM143 REV A

ORDERIng InFORMATIOn

P3C1256L - 32K x 8 STATIC CMOS RAM Page 9Document # SRAM143 REV A Pkg # P6 # Pins 28 (600 mil) Symbol Min Max A 0.090 0.200 A1 0.000 0.070 b 0.014 0.020 b2 0.015 0.065 C 0.008 0.012 D 1.380 1.430 E 0.485 0.550 E1 0.600 0.625 e 0.100 BSC eB 0.600 TYP L 0.100 0.180 0° 15° PLASTIC DUAL In-LInE PACkAgE SOIC/SOP SMALL OUTLInE IC PACkAgE Pkg # S11-3 # Pins 28 (330 Mil) Symbol Min Max A 0.094 0.120 A1 0.002 0.014 B 0.014 0.020 C 0.008 0.012 D 0.702 0.728 e 0.050 BSC E 0.291 0.340 H 0.463 0.477 h 0.010 0.029 L 0.020 0.050 0° 8°

P3C1256L - 32K x 8 STATIC CMOS RAM Page 10Document # SRAM143 REV A Pkg # T1 # Pins 28 Symbol Min Max A 0.039 0.047 A2 0.036 0.040 b 0.007 0.011 D 0.461 0.469 E 0.311 0.319 e 0.022 BSC HD 0.520 0.535 TSOP THIn SMALL OUTLInE PACkAgE

P3C1256L - 32K x 8 STATIC CMOS RAM Page 11Document # SRAM143 REV A REVISIOnS DOCUMEnT nUMBER SRAM143 DOCUMEnT TITLE P3C1256L LOW POWER 32K x 8 STATIC CMOS RAM REV ISSUE DATE ORIgInATOR DESCRIPTIOn OF CHAngE OR Jul-2011 JDB New Data Sheet A Oct-2011 JDB Added wide range power supply