P3C1024L55TC

P3C1024L PYRAMID | Alldatasheet

Document overview

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Technical content

Document # SRAM132 REV OR Revised April 2006 P3C1024L ULTRA LOW POWER 128K x 8 CMOS STATIC RAM locations are specified on address pins A0 to A16. Read- ing is accomplished by device selection ( CE1 low and CE2 high) and output enabling ( OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory lo- cation is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE 1 or OE is HIGH or WE or CE2 is LOW. The P3C1024L is packaged in a 32-pin TSOP and 445 mil SOP. The P3C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory re- quires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V ± 0.3V tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P3C1024L device provides asynchronous opera- tion with matching access and cycle times. Memory Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 445 mil SOP —32-Pin TSOP V CC Current (Commercial/Industrial) — Operating: 10mA/12mA — CMOS Standby: 10µA/10µA Access Times —55/70 (Commercial or Industrial) Single 3.3 Volts ± 0.3V Power Supply Easy Memory Expansion Using CECECECECE1, CE2 and OEOEOEOEOE Inputs

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SOP (S12) TOP VIEW See end of datasheet for TSOP pin configuration.

Page 2 of 9Document # SRAM132 REV OR GND ≤ VIN ≤ VCC Ind'l. Com'l. ILO RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Temperature Range (Ambient) Supply Voltage 3.0V ≤ VCC ≤ 3.6V Industrial (-40°C to 85°C) 3.0V ≤ VCC ≤ 3.6V Commercial (0°C to 70°C) Symbol Parameter Min Max Unit VCC Supply Voltage with Respect to GND -0.3 3.9 V VTERM Terminal Voltage with Respect to GND -0.3 VCC + 0.3 V TA Operating Ambient Temperature -55 125 °C STG -65 150 °C IOUT Output Current into Low Outputs 20 mA ILAT Latch-up Current >200 mA Storage Temperature Symbol Parameter VOH VOL VIH VIL ILI ISB ISB1 Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage V CC Current CMOS Standby Current (CMOS Input Levels) V CC Current TTL Standby Current (TTL Input Levels) Output Leakage Current Input Leakage Current IOH = –1mA, VCC = 3.3V IOL = 2.1mA VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V VCC = 3.6V, IOUT = 0 mA CE1 = VIH or CE2 = VIL GND ≤ VOUT ≤ VCC Ind'l. CE1 ≥ VIH or CE2 ≤ VIL Com'l. Test Conditions Min Max Unit 2.4 2.2 -0.3 V V V V µA µA mA µA 0.4 VCC + 0.3 0.8

Page 3 of 9Document # SRAM132 REV OR Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. CAPACITANCES(4) (VCC = 3.3V, TA = 25°C, f = 1.0 MHz) POWER DISSIPATION CHARACTERISTICS VS. SPEED AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter Test Conditions Max Unit CIN COUT Input Capacitance Output Capacitance VIN = 0V VOUT = 0V pF pF Symbol Parameter Unit ICC Dynamic Operating Current Commercial Industrial mA mA -55 -70Temperature Range Symbol Parameter -55 Min Max -70 Min Max Unit tRC 55 ns tAA Address Access Time 55 70 ns tAC Chip Enable Access Time 55 70 ns tOH Output Hold from Address Change 10 10 ns tLZ Chip Enable to Output in Low Z 10 10 ns tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 25 35 ns tOLZ Output Enable Low to Low Z 55 ns tOHZ Output Enable High to High Z 20 25 ns tPU Chip Enable to Power Up Time 00 ns tPD Chip Disable to Power Down Time 55 70 ns Read Cycle Time 70

Page 4 of 9Document # SRAM132 REV OR Notes: 1. WE is HIGH for READ cycle. 2. CE1 and OE is LOW, and CE2 is HIGH for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. READ CYCLE NO. 1 (OEOEOEOEOE CONTROLLED)(1) READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CECECECECE CONTROLLED) 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address.

Page 5 of 9Document # SRAM132 REV OR -55 Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) WRITE CYCLE NO. 1 (WEWEWEWEWE CONTROLLED)(6) Symbol Parameter Max -70 Max UnitMin Min tWC tCW tAS tWP tAH tDH tWZ tOW Write Cycle Time 55 70 ns Chip Enable Time to End of Write 40 60 ns Address Valid to End of Write 40 60 ns Address Set-up Time 00 n s Write Pulse Width 40 50 ns Address Hold Time 00 n s Data Valid to End of Write 25 30 ns Data Hold Time 00 n s Write Enable to Output in High Z 20 25 ns Output Active from End of Write 10 10 ns tAW tDW

• including scope and test fixture.

is also required between VCC and ground. Figure 1. Output Load Figure 2. Thevenin Equivalent

Page 7 of 9Document # SRAM132 REV OR DATA RETENTION 2. VCC ramp from VDR to VCC (min) > 100 µs for full device operation. LOW VCC DATA RETENTION WAVEFORM 1 (CECECECECE1 CONTROLLED) Symbol Parameter Test Conditions Unit MaxMin VDR ICCDR (1) VCC for Data Retention Data Retention Current CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V 2.0 V VDR = 2.0V 10 µA tR Operating Recovery Time(2) Chip Deselect to Data Retention Time See Retention Waveform 100 µs nstCDR LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)

Page 8 of 9Document # SRAM132 REV OR SELECTION GUIDE The P3C1024L is available in the following temperature, speed and package options.

ORDERING INFORMATION

-55 -70 Plastic SOP (445 mil) -55SC -70SC TSOP -55TC -70TC Plastic SOP (445 mil) -55SI -70SI TSOP -55TI -70TI SpeedTemperature Range Package Commercial Industrial

Page 9 of 9Document # SRAM132 REV OR SOIC/SOP SMALL OUTLINE IC PACKAGE Pkg # # Pins Symbol Min Max A - 0.118 A1 0.004 - b2 0.014 0.020 C 0.006 0.012 D 0.790 0.820 e E 0.435 0.455 H 0.546 0.566 h 0.010 0.029 L 0.023 0.039 0° 8° S12 32 (445 Mil)

0.050 BSC

α TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm)Pkg # # Pins Symbol Min Max A - 0.048 A2 0.037 0.042 b 0.006 0.011 D 0.720 0.729 E 0.307 0.323 e H D 0.779 0.796 0.50 mm BSC All dimensions in inches except as noted

Page 10 of 9Document # SRAM132 REV OR REVISIONS DOCUMENT NUMBER: SRAM132 DOCUMENT TITLE: P3C1024L LOW POWER 128K x 8 CMOS STATIC RAM REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE OR Apr-06 JDB New Data Sheet