P322DB10UI

AM29PDS322D AMD | Alldatasheet

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Publication Number 23569 Revision A Amendment 5 Issue Date December 4, 2006 The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29PDS322D Data Sheet

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 23569 Rev: A Amendment/5 Issue Date: December 4, 2006 Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations ■ Page Mode Operation — 4 word page allows fast asynchronous reads ■ Dual Bank architecture — One 4 Mbit bank and one 28 Mbit bank ■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Package options — 48-ball FBGA ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 40 ns (100 ns random access time) at 1.8 V to 2.2 V V CC — Random access time of 100 ns at 1.8 V to 2.2 V V CC will be required as customers migrate downward in voltage ■ Ultra low power consumption (typical values) — 2.5 mA active read current at 1 MHz for initial page read — 24 mA active read current at 10 MHz for initial page read — 0.5 mA active read current at 10 MHz for intra-page read — 1 mA active read current at 20 MHz for intra-page read — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing — ACC voltage is 8.5 V to 12.5 V ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system

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The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. This device is offered in a 48-ball FBGA pack- age. The device is designed to be programmed in sys- tem with standard system 1.8 V V CC supply. This device can also be reprogrammed in standard EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to

2.2 V V

CC), allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 4 words. The device requires only a single 1.8 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and si- multaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Am29PDS322D Features The SecSi (Secured Silicon) Sector is an extra 64 KByte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank 1 Sectors Bank 2 Sectors Quantity Size Quantity Size

84 K w o r d s

4 Mbits total 28 Mbits total

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Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Part Number Am29PDS322D Speed Options Standard Voltage Range: V CC = 1.8–2.2 V 10 12 Max Random Address Access Time (ns) 100 120 Max Page Address Access Time (ns) 40 45 CE# Access Time (ns) 100 120 OE# Access Time (ns) 35 40 VCC VSS Upper Bank AddressA0–A20 RESET# WE# CE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A20 A0–A20 A0–A20A0–A20 DQ0–DQ15 DQ0–DQ15 Mux Mux Mux

December 4, 2006 23569A5 Am29PDS322D 5 DATA SHEET CONNECTION DIAGRAMS Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15 VSSNCA16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Ball FBGA Top View, Balls Facing Down

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A0–A20 = 21 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect/ Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output V CC = 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ0–DQ15 A0–A20 CE# OE# WE# RY/BY#RESET# WP#/ACC

December 4, 2006 23569A5 Am29PDS322D 7 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29PDS322D B 10 WM I N OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE WM = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 12 mm package (FBD048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29PDS322D

32 Megabit (2 M x 16-Bit) CMOS Boot Sector Page Mode Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for FBGA Package Order Number Package Marking Am29PDS322DT10, Am29PDS322DB10 WMI P322DT10U, P322DB10U I Am29PDS322DT12, Am29PDS322DB12 WMI P322DT12U, P322DB12U I

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register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29PDS322D Device Bus Operations

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. mand is necessary in this mode to obtain array data. gate data to the output pins if the device is selected.

A1–A0 determine the specific word within that page. cessor supplying the specific word location. 16 for timing specifications. Table 2. Page Word Mode and Unlock Bypass command sequences. space that each sector occupies. tables and timing diagrams for write operations. gram and read-while-erase, respectively. state, independent of the OE# input. before it is ready to read data.

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If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Automatic sleep mode current is drawn when CE# = V SS ± 0.3 V and all inputs are held at V CC ± 0.3 V. If CE# and RESET# voltages are not held within these tolerances, the automatic sleep mode current will be greater. I CC5 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for th e duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.3 V, the device draws CMOS standby current (ICC3). If RESET# is held at VIL but not within V SS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 3. Am29PDS322DT Top Boot Sector Addresses

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Table 4. Am29PDS322DT Top Boot SecSi Sector Address Table 3. Am29PDS322DT Top Boot Sector Addresses (Continued) Table 5. Am29PDS322DB Bottom Boot Sector Addresses

Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

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Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 7. In addition, when verifying sector protection, highest order address bits (see Tables 3 through 6). the corresponding identifier code on DQ15–DQ0. mand Sequence section for more information. Table 7. Autoselect Codes (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

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Table 8. Top Boot Sector/Sector Block Addresses Table 9. Bottom Boot Sector/Sector Block

equipment requires V ID on address pin A9 and OE#. representative for further details. The device is shipped with all sectors unprotected. AMD representative for details. a top-boot-configured device. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

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1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

Figure 2. Temporary Sector Group Unprotect

Figure 3. In-System Sector Group Protect/Unprotect Algorithms

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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize that sector in any manner they choose. The customer-lock- able version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indi- cator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the ad- dresses normally occupied by the first sector (SA0). This mode of operation continues until the system is- sues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors instead of the SecSi sector Factory Locked: SecSi Sector Programmed and Protected at the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable mem- ory area at addresses 000000h–000007h. In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at ad- dresses 1F8000h–1F8007h. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the permanently locked. Contact an AMD representative for details on using AMD’s Express- Flash service. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 3, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection” sec- tion. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent

December 4, 2006 23569A5 Am29PDS322D 21 DATA SHEET writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 10 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Co mmand, for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 15 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an aut oselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode,

22 Am29PDS322D 23569A5 December 4, 2006

and the system may read any number of autoselect codes without reinitiating the command sequence. Table 10 shows the address and data requirements for the command sequence. To determine sector protec- tion information, the system must write to the appropri- ate sector group address (SGA). Tables 3 and 5 show the address range associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 16-byte random Electronic Serial Num- ber (ESN). The system can access the SecSi Sector region by issuing the thr ee-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Mem- ory Region” for further information. Note that a hard- ware reset (RESET#=V IL ) will reset the device to reading array data. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the program command se- quence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refe r to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to reading array data. See Figure 4 for the unlock bypass algorithm. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock

24 Am29PDS322D 23569A5 December 4, 2006

When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characterist ics section for parameters, and Figure 20 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re- write the command sequence and any additional ad- dresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section for infor- mation on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Note that un- lock bypass programming is not allowed when the device is erase-suspended. Reading at any address within erase-suspended sec- tors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read

just as in the standard word program operation. can be written after the chip has resumed erasing.

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

Figure 6. Erase Operation

26 Am29PDS322D 23569A5 December 4, 2006

Table 10. Am29PDS322D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. or erased. Address bits A20–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth and fifth cycle of the

autoselect command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A12 are don’t cares in
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The device ID must be read across the fourth, fifth and sixth
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector group and 01h for a
4. The Unlock Bypass command is required prior to the Unlock
5. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

28 Am29PDS322D 23569A5 December 4, 2006

Table 11 shows the outputs for RY/BY#. complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. Table 11 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 8. Toggle Bit Algorithm

30 Am29PDS322D 23569A5 December 4, 2006

Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

32 Am29PDS322D 23569A5 December 4, 2006

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. 5. Embedded algorithm (program or erase) is in progress (at 8 MHz). Parameter Symbol Parameter Description Te st Conditions Min Typ Max Unit I LI Input Load Current V IN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9, OE#, RESET# = 11 V 35 µA ILO Output Leakage Current V OUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Inter-Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, 1 MHz 2.5 3 mA

10 MHz 24 28

ICC2 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) WP#/ACC = VCC ± 0.3 V, RESET# = VSS ± 0.3 V 0.1 5 µA ICC5 VCC Automatic Sleep Mode Current (Notes 2, 4) CE# = VSS ± 0.3 V; RESET# = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH 30 55 mA ICC7 VCC Active Read-While-Erase Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH 30 55 mA ICC8 VCC Active Program-While-Erase-Suspended Current (Note 2) CE# = VIL, OE# = VIH 17 35 mA ICC9 VCC Active Intra-Page Read Current CE# = V IL, OE# = VIH 10 MHz 0.5 1 mA

20 MHz 1 2

WP#/ACC Accelerated Program Current VCC = VCCMax, WP#/ACC = VACCMax 12 20 mA VIL Input Low Voltage –0.5 V CC x 0.2 V VIH Input High Voltage 0.8 x V CC VCC + 0.3 V VACC Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 1.8–2.2 V 8.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 1.8–2.2 V 9 11 V VOL Output Low Voltage I OL = 100 µA, VCC = VCC min 0.1 V VOH Output High Voltage I OH = –100 µA V CC – 0.1 V VLKO Low VCC Lock-Out Voltage 1.2 1.5 V

34 Am29PDS322D 23569A5 December 4, 2006

Table 12. Test Specifications Figure 13. Test Setup Figure 14. Input Waveforms and Measurement Levels

1. See Figure 13 and Table 12 for test specifications.
2. Measurements performed by placing a 50 Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the

data bus driven to VCC/2 is taken as tDF.

0 VRY/BY#

Figure 15. Conventional Read Operation Timings

36 Am29PDS322D 23569A5 December 4, 2006

Figure 16. Page Mode Read Timings

Figure 17. Reset Timings

38 Am29PDS322D 23569A5 December 4, 2006

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Option JEDEC Std Description 10 12 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 60 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 60 ns tWHDX tDH Data Hold Time Min 0 ns tCEPH Chip Enable High during toggle bit polling Min 20 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 60 ns tWHDL tWPH Write Pulse Width High Min 60 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

40 Am29PDS322D 23569A5 December 4, 2006

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 20. Chip/Sector Erase Operation Timings

42 Am29PDS322D 23569A5 December 4, 2006

Figure 23. Toggle Bit Timings (During Embedded Algorithms) Figure 24. DQ2 vs. DQ6

Figure 25. Temporary Sector Group Unprotect Timing Diagram

44 Am29PDS322D 23569A5 December 4, 2006

• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector Group Protect and Unprotect Timing Diagram

December 4, 2006 23569A5 Am29PDS322D 45 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Option JEDEC Std Description 10 12 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 60 ns tDVEH tDS Data Setup Time Min 60 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 60 ns tEHEL tCPH CE# Pulse Width High Min 60 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 16 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 2) Typ 5 5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

46 Am29PDS322D 23569A5 December 4, 2006

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

December 4, 2006 23569A5 Am29PDS322D 47 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1 10 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 93 sec Word Program Time 16 360 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 5 µs Chip Program Time (Note 3) 20 100 sec Description Min Max Input voltage with respect to V SS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

48 Am29PDS322D 23569A5 December 4, 2006

FBD048—48-Ball Fine-Pitch Ball Gr id Array (FBGA) 6 x 12 mm package * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AF; 1/2000 xFBD 048 6.00 mm x 12.00 mm PACKAGE 1.20 0.20 0.84 0.94

12.00 BSC

6.00 BSC

5.60 BSC

4.00 BSC

0.25 0.30 0.35

0.80 BSC

0.40 BSC

December 4, 2006 23569A5 Am29PDS322D 49 DATA SHEET REVISION SUMMARY Revision A (December 4, 2000) Initial release. Revision A+1 (February 16, 2001) Added “U” designator to package marking. Deleted burn-in option. Revision A+2 (August 31, 2001) Autoselect Command Sequence Modified section to point to appropriate tables for au- toselect functions. Revision A+3 (February 18, 2002) Global Removed “Advance Information” designation from data sheet. Erase Suspend/Erase Resume Commands Noted in the third paragraph that unlock bypass pro- gramming is not allowed when the device is erase sus- pended. Revision A+4 (August 7, 2002) Distinctive Characteristics Removed “Supports Common Flash Memory Interface (CFI)) ment (inadvertently restored in Revision A+4). thorization by the respective government entity will be required for export of those products. for identification purposes only and may be trademarks of their respective companies. trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.