P320DB60RI

AM29PL320D AMD | Alldatasheet

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Publication Number 24075 Revision C Amendment +3 Issue Date June 13, 2005 Am29PL320D Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this docu- ment is retained for reference and historical purposes only. June 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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Publication# 24075 Rev: C Amendment/+3 Issue Date: June 13, 2005 Refer to AMD’s Website (www.amd.com/flash) for the latest information. Am29PL320D

32 Megabit (2 M x 16-Bit/1 M x 32-Bit)

CMOS 3.0 Volt-only High Performance Page Mode Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ 32 Mbit Page Mode device — Word (16-bit) or double word (32-bit) mode selectable via WORD# input — Page size of 8 words/4 double words: Fast page read access from random locations within the page ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors ■ Flexible sector architecture — Sector sizes (x16 configuration): One 16 Kword, two 8 Kword, one 96 Kword and fifteen 128 Kword sectors — Supports full chip erase ■ SecSi ™ (Secured Silicon) Sector region — Current version of device has 512 words (256 double words); future versions will have 128 words (64 double words) ■ Top or bottom boot block configuration ■ Manufactured on 0.23 µm process technology ■ 20-year data retention at 125 ■ Minimum 1 million erase cycles guarantee per sector PERFORMANCE CHARACTERISTICS ■ High performance read access times — Page access times as fast as 20 ns — Random access times as fast as 60 ns ■ Power consumption (typical values) — Initial page read current: 4 mA (1 MHz), 40 mA (10 MHz) — Intra-page read current: 15 mA (10 MHz), 50 mA (33 MHz) — Program/erase current: 25 mA — Standby mode current: 2 µA SOFTWARE FEATURES ■ Software command-set compatible with JEDEC standard — Backward compatible with Am29F and Am29LV families ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation HARDWARE FEATURES ■ Sector Protection — A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked via programming equipment — Temporary Sector Unprotect command sequence allows code changes in previously locked sectors ■ ACC (Acceleration) input provides faster programming times ■ WP# (Write Protect) input —A t V IL, protects the first or last 32 Kword sector, regardless of sector protect/unprotect status —A t V IH, allows removal of sector protection — An internal pull up to V CC is provided ■ Package Options — 84-ball FBGA This product has been retired and is not recommended for designs. For new and current designs, S29GL032M supersedes Am29PL320D and is the factory-recommended migration path. Please refer to the S29GL032M datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29PL320D is a 32 Mbit, 3.0 Volt-only page mode Flash memory device organized as 2,097,152 words or 1,048,576 double words. The device is of- fered in an 84-ball FBGA package. The word-wide data (x16) appears on DQ15–DQ0; the double word- wide (x32) data appears on DQ31–DQ0. The device is available in both top and bottom boot versions. This device can be programmed in-system or with in stan- dard EPROM programmers. A 12.0 V V PP or 5.0 V CC are not required for write or erase operations. The device offers fast page access times of 20, 25, and 35 ns, with corresponding random access times of 60, 70, 90 ns, respectively, allowing high speed micro- processors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#), and output enable (OE#) controls. Page Mode Features The device is AC timing, input, output, and package compatible with 16 Mbit x 16 page mode Mask ROM. The page size is 8 words or 4 double words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. Standard Flash Memory Features The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cy- cles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The SecSi ™ Sector (Secured Silicon) is an extra sec- tor capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is perma- nently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lock- able parts can never be used to replace a factory locked part. Current version of device has 512 words (256 double words); future versions will have only 128 words (64 double words). This should be considered during system design. Fac- tory locked parts can store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may be programmed after being shipped from AMD. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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June 13, 2005 Am29PL320D 5 PRODUCT SELECTOR GUIDE Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29PL320D Speed Option Regulated Voltage Range: VCC =3.0–3.6 V 60R 70R Full Voltage Range: VCC = 2.7–3.6 V 70 90 Max access time, ns (tACC)6 0 7 0 9 0 Max CE# access time, ns (tCE)6 0 7 0 9 0 Max page access time, ns (tPACC)2 0 2 5 3 0 Max OE# access time, ns (tOE)2 0 2 5 3 0 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WORD# ACC WP# CE# OE# STB STB DQ31–DQ0 Data Latch Y-Gating Cell Matrix Address LatchA19–A0 A1, A0, A-1

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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. C1 D1 E1 F1 G1 H1 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ8 A15NCNCDQ31/A-1NCNCWE# NC NCNCNCNCWP#ACCNC A12 A11NCDQ2A0A3A2A1 DQ21 A8DQ5DQ18DQ16DQ0A5A4 DQ6 DQ7DQ4DQ19VSSDQ1VCC VSS VCCDQ20 J2 K2 J3 K3 J4 K4 J5 K5 J6 K6 A14 A13 NC NC A9 A10 A7 B7 C7 D7 E7 F7 G7 H7 A8 B8 C8 D8 E8 F8 G8 H8 VSS DQ24DQ11DQ28DQ29DQ15VSSCE# DQ25 A18DQ10VSSDQ14OE#WORD#NC J7 K7 J8 K8 VCC A19 A17 A16 B9 C9 D9 E9 F9 G9 H9 DQ26 VCCDQ27DQ12DQ13VCCDQ30 DQ9 A6 A7 DQ23 V SS DQ22DQ3VCCDQ17 84-Ball FBGA Top View, Balls Facing Down

June 13, 2005 Am29PL320D 7 INPUT CONFIGURATION A19–A0 = 20 address inputs DQ30–DQ0 = 31 data inputs/outputs DQ31/A-1 = In double word mode, functions as DQ31. In word mode, functions as A-1 (LSB address input) WORD# = Word enable input When low, enables word mode When high, enables double word mode WP# = Hardware Write Protect input ACC = Acceleration input CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device ground NC = input not connected internally LOGIC SYMBOL 16 or 32 DQ31–DQ0 (A-1) A19–A0 CE# OE# WE# WORD# WP# ACC

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29PL320D B 60R WP I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE WP = 84-Ball Fine Pitch Ball Grid Array (FBGA) 0.8 mm pitch (FBF084) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Boot Sector B = Bottom Boot Sector DEVICE NUMBER/DESCRIPTION Am29PL320D CMOS 3.0 Volt-only High Performance Page Mode Flash Memory Valid Combinations Package Marking Voltage Range AM29PL320DT60R, AM29PL320DB60R WPI P320DT60RI, P320DB60RI VCC = 3.0–3.6 V AM29PL320DT70R, AM29PL320DB70R P320DT70RI, P320DB70RI AM29PL320DT70, AM29PL320DB70 P320DT70VI, P320DB70VI VCC = 2.7–3.6 V AM29PL320DT90, AM29PL320DB90 P320DT90VI, P320DB90VI

each of these operations in further detail. Table 1. Am29PL320D Device Bus Operations

1. Addresses are A19–A0 in double word mode (WORD# = V IH), A19–A-1 in word mode (WORD# = V IL).
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. active and controlled by CE# and OE#. used as an input for the LSB (A-1) address function. the device outputs array data in words or bytes. until the command register contents are altered. rent specification for reading array data. gate data to the output inputs if the device is selected.

0.3 V X X X X High-Z High-Z High-Z

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to select the specific word, within that page. Table 2. Double Word Mode Table 3. Word Mode

June 13, 2005 Am29PL320D 11 Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the WORD# input determines whether the device accepts program data in double words or words. Refer to “Word/Double Word Configu- ration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or double word, instead of four. The “Word/Double Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 4 indicates the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has de- tails on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH (11.5 to 12.5 V) on this in- put, the device automatically enters the aforemen- tioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program opera- tions. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at V HH for operations other than acceler- ated programming, or device damage may result. In addition, the ACC pin must not be left floating or un- connected; inconsistent behavior of the device may re- sult. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris- tics” for timing diagrams. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# input is both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# is held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during Automatic Sleep mode, OE# must be at V IH before the device reduces cur- rent to the stated sleep mode specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output inputs are placed in the high im- pedance state.

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Table 4. Sector Address Table, Top Boot (Am29PL320DT) Table 5. SecSi ™ Sector Addresses for Top Boot Devices

Table 6. Sector Address Table, Bottom Boot (Am29PL320DB) Table 7. SecSi ™ Sector Addresses for

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system through the command register. details on using the autoselect mode. Table 8. Am29PL320D Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 13. program and erase operations in any sector. The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. re-protected using the sector protect algorithm. Command Sequence” for more information.

interfaces for long-term compatibility. mode), any time the device is ready to read array data. the system must write the reset command. vice to the autoselect mode. Table 9. CFI Query Identification String

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Table 10. System Interface String Table 11. Device Geometry Definition

SecSi Sector is locked when shipped from the factory. Table 12. Primary Vendor-Specific Extended Query D7–D4: volt; D3–D0: 100 millivolt. D7–D4: volt; D3–D0: 100 millivolt.

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tected when the device is shipped from the factory. through the ExpressFlash service. factory with the SecSi Sector permanently locked. ■ Write 60h to any address (protect command). ■ Read from address 02h. The data should be 01h. ■ Write the reset command (F0h to any address). quence to return to reading from the array. Sector, follow the algorithm shown in Figure 1. Figure 1. SecSi Sector Protect Verify

June 13, 2005 Am29PL320D 19 tected using the method described in “Sector Protec- tion/Unprotection”. If the system asserts V IH on the WP# input, the device reverts to whether Sector 0 or 18 was last set to be protected or unprotected. That is, sector protection or unprotection for that sector depends on whether they were last protected or unprotected using the method described in “Sector Protection/Unprotection”. Note that the WP# input must not be left floating or un- connected; inconsistent behavior of the device may re- sult. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 13 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must pro- vide the proper signals to the control inputs to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 13 defines the valid register com- mand sequences. Note that writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. A reset command is required to return the device to nor- mal operation. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys- tem can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor- mation on this mode. The system must issue the reset command to re-en- able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.

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The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 13 shows the address and data requirements. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read any number of autoselect codes without reinitiating the command sequence. Tables 13 and 14 show the address and data require- ments for the command sequence. To determine sec- tor protection information, the system must write to the appropriate sector address (SA). Tables 4 and 6 show the address range associated with each sector. The system must write the reset command to exit the autoselect mode and return to reading array data. Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight-word (or four double word) electronic serial number (ESN). The system can ac- cess the SecSi Sector region by issuing the three- cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sec- tor command sequence. The Exit SecSi Sector com- mand sequence returns the device to normal operation. Table 13 shows the address and data re- quirements for both command sequences. See also “SecSi ™ (Secured Silicon) Sector Flash Memory Region” for further information. Word/Double Word Program Command Sequence The system may program the device by word or double word, depending on the state of the WORD# input. Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically gener- ates the program pulses and verifies the programmed cell margin. Table 13 shows the address and data re- quirements for the program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for informa- tion on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. The Program command sequence should be reinitiated once the de- vice has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. The unlock by- pass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The de- vice then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the pro- gram address and data. Additional data is programmed in the same manner. This mode dis- penses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 13 shows the re- quirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 2 illustrates the algorithm for the program oper- ation. See the Program/Erase Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams.

Figure 2. Program Operation

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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 13 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embed- ded Erase algorithm are ignored. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase op- eration by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase opera- tion. See the Program/Erase Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 13 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The in- terrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Sus- pend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector ad- dresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the sta- tus of the erase operation by using DQ7, DQ6, or DQ2. (Refer to “Write Operation Status” for information on these status bits.) Figure 3 illustrates the algorithm for the erase opera- tion. Refer to the Program/Erase Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo- rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Ad- dresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maxi- mum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is writ- ten during the sector erase time-out, the device immediately terminates the time-out period and sus- pends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase

if a sector is actively erasing or is erase-suspended. pend mode and continue the sector erase operation. Further writes of the Resume command are ignored. the device has resumed erasing.

1. See Table 13 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

24 Am29PL320D June 13, 2005

1. All protected sectors are unprotected. If WP# = V IL, the

first or last 64 KByte sector will remain protected.

1. All previously protected sectors are protected once again.

Figure 4. Temporary Sector Unprotect Algorithm

Table 13. Command Definitions (Double Word Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. on the falling edge of the WE# or CE# pulse, whichever happens later. edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ31–DQ8 are don’t cares for unlock and command
2. Address bits A19–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array data.
2. The Reset command is required to return to reading array data when

device is providing status data).

1. The fourth cycle of the autoselect command sequence is a read
2. DQ31–DQ16 output 2222h for device ID reads. The device ID must
3. The data is 80h for factory locked and 00h for not factory locked.
4. The data is 00h for an unprotected sector and 01h for a protected

sector. See “Autoselect Command Sequence” for more information.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

1. The Unlock Bypass command is required prior to the Unlock Bypass
2. The Unlock Bypass Reset command is required to return to reading

array data when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or enter

Suspend command is valid only during a sector erase operation.

1. The Erase Resume command is valid only during the Erase Suspend

26 Am29PL320D June 13, 2005

Table 14. Command Definitions (Word Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. on the falling edge of the WE# or CE# pulse, whichever happens later. edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ31–DQ8 are don’t cares for unlock and command
2. Address bits A19–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array data.
2. The Reset command is required to return to reading array data when

device is providing status data).

1. The fourth cycle of the autoselect command sequence is a read
2. The device ID must be read across the fourth, fifth, and sixth cycles.
3. The data is 80h for factory locked and 00h for not factory locked.
4. The data is 00h for an unprotected sector and 01h for a protected

sector. See “Autoselect Command Sequence” for more information.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

1. The Unlock Bypass command is required prior to the Unlock Bypass
2. The Unlock Bypass Reset command is required to return to reading

array data when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or enter

Suspend command is valid only during a sector erase operation.

1. The Erase Resume command is valid only during the Erase Suspend

28 Am29PL320D June 13, 2005

DQ6: Toggle Bit Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog- gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 15 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 20 in the “AC Character- istics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit”. DQ2: Toggle Bit The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit subsection. Figure 20 shows the toggle bit timing dia- gram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure

was not successfully completed. μs. See also the “Write Operation Status” section. accepted. Table 15 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ 5

Figure 6. Toggle Bit Algorithm

30 Am29PL320D June 13, 2005

Table 15. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

32 Am29PL320D June 13, 2005

Notes: 1. The I CC current listed is typically less than 4 mA/MHz, with OE# at V IH. T ypical VCC is 3.0 V. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. The Automatic Sleep Mode current is dependent on the state of OE#. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. 6. Not 100% tested. Parameter Symbol Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Inter-Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH

1 MHz 4 50 mA

10 MHz 40 80 mA

(Notes 2, 4) CE# = VIL, OE# = VIH 25 80 mA ICC3 VCC Standby Current (Note 2) CE# = V CC±0.3 V 2 5 µA ICC4 Automatic Sleep Mode (Notes 2, 3, 6) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V OE# = VIH 15 µA OE# = VIL 22 0 ICC5 VCC Active Intra-Page Read Current (Note 2) CE# = VIL, OE# = VIH

10 MHz 15 50 mA

33 MHz 50 80 mA

VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 V CC + 0.3 V VHH Voltage for Accelerated Programming on ACC 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 ± 0.3 V 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 VLKO Low VCC Lock-Out Voltage (Note 6) 2.3 2.5 V

34 Am29PL320D June 13, 2005

Table 16. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

June 13, 2005 Am29PL320D 35 AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications. Parameter Description Test Setup Speed Options UnitJEDEC Std 60R 70R, 70 90 tAVAV tRC Read Cycle Time Min 60 70 90 ns tAVQV tACC Address Access Time CE#=VIL, OE#=VIL Max 60 70 90 ns tELQV tCE Chip Enable to Output Delay OE#=V IL Max 60 70 90 ns tPACC Page Access Time Max 20 25 35 ns tGLQV tOE Output Enable to Output Valid Max 20 25 35 ns tEHQZ tDF Chip Enable to Output High Z Max 16 ns tGHQZ tDF Output Enable to Output High Z Max 16 ns tOEH Output Enable Hold Time (Note 1) Read 0 ns Toggle and Data# Polling 10 ns tAXQX tOH Output Hold Time From Addresses, OE# or CE#, Whichever Occurs First (Note 1) Min 0 ns

36 Am29PL320D June 13, 2005

Figure 13. Conventional Read Operations Timings Note: Double Word Configuration: Toggle A2, A1, A0. Word Configuration: Toggle A2, A1, A0, A-1. Figure 14. Page Read Timings

38 Am29PL320D June 13, 2005

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter

Description

JEDEC Std 60R 70R, 70 90 tAVAV tWC Write Cycle Time (Note 1) Min 60 70 90 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 35 45 45 ns tDVWH tDS Data Setup Time Min 30 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 35 ns tWHWL tWPH Write Pulse Width High Min 25 30 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 14.3 µs Double Word Typ 18.3 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 5 sec tVCS VCC Setup Time (Note 1) Min 50 µs

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

40 Am29PL320D June 13, 2005

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. AC Waveforms for Chip/Sector Erase Operations Figure 19. Data# Polling Timings (During Embedded Algorithms)

42 Am29PL320D June 13, 2005

Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter UnitJEDEC Std 60R 70R, 70 90 tAVAV tWC Write Cycle Time (Note 1) Min 60 70 90 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 35 45 45 ns tDVEH tDS Data Setup Time Min 30 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 25 30 35 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 14.3 µsDouble Word Ty p 18 .3 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 5 sec

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D OUT = data written to the
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.

Figure 22. Alternate CE# Controlled Write Operation Timings

44 Am29PL320D June 13, 2005

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 13 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all inputs except VCC. Test conditions: VCC = 3.0 V, one input at a time. DATA RETENTION * For reference only. BSC is an ANSI standard for Basic Space Centering. BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions TA = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time, 96 and 128 KByte sector 26 0 s Excludes 00h programming prior to erasure (Note 4)Sector Erase Time, 8 and 16 KByte sector 0.5 60 Chip Erase Time 33.5 s Word Programming Time 14.3 300 µs Excludes system level overhead (Note 5) Double Word Programming Time 18.3 360 µs Chip Programming Time (Note 3) Word Mode 28 84 s Double Word Mode 18 54 s Description Min Max Input voltage with respect to V SS on all inputs except I/O inputs (including A9 and OE#) –1.0 V 12.5 V Input voltage with respect to V SS on all I/O inputs –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 4.2 5.0 pF COUT Output Capacitance V OUT = 0 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 3.9 4.7 pF

June 13, 2005 Am29PL320D 45 PHYSICAL DIMENSIONS FBF084—84-Ball Fine Pitch Ball Grid Array (FBGA) 11 x 12 mm Dwg. Rev. AB-01; 7/00

46 Am29PL320D June 13, 2005

Revision A (March 7, 2001) Initial release. Revision B (June 12, 2001) Global Added 70R speed option. Changed data sheet status from Advance Information to Preliminary. Distinctive Characteristics SecSi Sector: Added note to future compatibility. Power Consumption: Replaced stated maximum val- ues with typical values. General Description Added section on SecSi Sector. SecSi™ (Secured Silicon) Sector Flash Memory Region Added note to indicate sector size and erase function- ality for future devices. DC Characteristics Added typical values for I CC1–ICC5 to table. Corrected VIN test condition specification to V CC. Figure 10, Typical ICC1 vs. Frequency Changed scale on Y -axis to 4 mA divisions. Revision B+1 (August 30, 2001) Autoselect Command Sequence Modified section to point to appropriate tables for au- toselect functions. Accelerated Program Operation Specified a voltage range for VHH. Table 13, Command Definitions Corrected the autoselect device ID command se- quence. The device ID is read in cycles 4, 5, and 6 of a single command sequence, not as three separate command sequences as previously shown. Separated the word and double word command sequences into two tables for easier reference. DC Characteristics Added V HH parameter to table. Revision C (October 22, 2002) Global Deleted preliminary status from data sheet. Distinctive Characteristics Clarified endurance specification from “write cycles” to “erase cycles.” SecSi™ (Secured Silicon) Sector Flash Memory Region Added text and figure on SecSi Sector Protect Verify function. Command Definitions Modified first paragraph to indicate device behavior when incorrect data or commands are written. DC Characteristics Changed V IL maximum specification. Changed V CC test condition for VID parameter. BGA Ball Capacitance Added table. Revision C+1 (July 21, 2003) Common Flash Interface (CFI) Changed URL for CFI publications. Command Definitions Added the phrase “in the improper sequence” to cau- tionary text in first paragraph. Erase and Programming Performance Changed typical sector erase time and typical chip erase time. Added typical and maximum sector erase times pertaining to 8 and 16 Kword sectors. Revision C+2 (October 2, 2003) Erase Suspend/Erase Resume Commands Modified text to “Note that unlock bypass programming is not allowed when the device is erase-suspended” in the third paragraph. AC Characteristics - Double Word/Word Configuration (WORD#) diagram Modified all instances of DQ14 to DQ30, DQ7 to DQ15, and DQ15 to DQ31. Revision C+3 (June 13, 2005) Cover Page / Title Page Added Spansion EOL cover page and added EOL disclaimer to title page.

June 13, 2005 Am29PL320D 47 Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .