PLL130-07 PLL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 5
Technical content
High Speed Translator Buffer to CMOS (Selectable Drive) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
FEATURES
- CMOS output
- Selectable Drive capability (15pF or 30pF output load).
- Single AC coupled input (min. 100mV swing).
- Input range from DC to 200 MHz.
- 2.5V to 3.3V operation.
- Available in 8-Pin SOIC and 3x3mm QFN.
DESCRIPTION
The PLL130-07 is a low cost, high performance, high speed, buffer that reproduces any input fre- quency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. Any input signal with at least 100mV swing can be used as reference signal. This chip is ideal for conversion from sine wave to CMOS. PIN CONFIGURATION (TOP VIEW) BLOCK DIAGRAM Input Amplifier REF_IN CLK_OUT PLL130-07 GND REF_IN GND VDD DRIV_SEL^ GND CLK_OUT VDD PLL130-07 CLK_OUT N/C GND VDD VDD VDD GND VDD GND DRIV_SEL^ GND OE^ GND GND REF_IN GND Note: ^ denotes internal pull up
High Speed Translator Buffer to CMOS (Selectable Drive) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2 PIN DESCRIPTION Name 8pin SOIC Pin number 3x3mm QFN Pin number Type 1,3,6 1,2,4,5, 9,14,15 P Ground. VDD 4,7 7,10,11,12 P Power supply. DRIV_SEL I Drive Select input: ‘1’ for standard drive, ‘0’ for hi-drive output. Internal pull-up (default is ‘1’). REF_IN I Reference input signal. The frequency of this signal will be reproduced at the output (after translation to CMOS level). CLK_OUT O CMOS clock output. OE N/A I Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage VDD 4.6 V Input Voltage, dc VI -0.5 VDD+0.5 V Output Voltage, dc VO -0.5 VDD+0.5 V Storage Temperature TS -65 150 Ambient Operating Temperature* TA -40 Junction Temperature TJ 125 Lead Temperature (soldering, 10s) 260 ESD Protection, Human Body Model kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con- ditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. AC Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Frequency 200 MHz Input signal swing REF_IN input 100 mV Output Frequency 200 MHz
High Speed Translator Buffer to CMOS (Selectable Drive) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3 3. CMOS Output Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output High Voltage VOH IOH = -12mA 2.4 V Output Low Voltage VOL ILO = 12mA 0.4 V Output High Voltage at CMOS level VOHC IOH = -4mA VDD– 0.4 V At TTL level (High drive*) mA Output drive current At TTL level (Standard drive) mA * Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN). 4. CMOS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 0.8V ~ 2.0V with 10 pF load 1.15 Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 3.7 0.8V ~ 2.0V with 10 pF load 0.5 Output Clock Rise/Fall Time (High Drive*) 0.3V ~ 3.0V with 15 pF load 1.5 ns * Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN).
High Speed Translator Buffer to CMOS (Selectable Drive) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4
PACKAGE INFORMATION
C L A
8 PIN ( dimensions in mm )
Min. Max. A 1.47 1.73 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e
1.27 BSC
E H D A e B
High Speed Translator Buffer to CMOS (Selectable Drive) 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL130-07 x C Order Number Marking Package Option PLL130-07QC-R P130-07QC QFN - Tape and Reel PLL130-07QC P130-07QC QFN - Tube PLL130-07SC-R P130-07SC SOIC -Tape and Reel PLL130-07SC P130-07SC SOIC - Tube PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC; Q=QFN