PLL103-02 PLL | Alldatasheet

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Technical content

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1

FEATURES

  • Generates 24 output buffers from one input.
  • Supports up to four DDR DIMMS.
  • Supports 266MHz DDR SDRAM.
  • One additional output for feedback.
  • Less than 5ns delay.
  • Skew between any outputs is less than 100 ps.
  • 2.5V Supply range.
  • Enhanced DDR Output Drive selected by I2C.
  • Available in 48 pin SSOP. BLOCK DIAGRAM PIN CONFIGURATION Note: #: Active Low

DESCRIPTION

The PLL103-02 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR DIMMS. The PLL103-02 can be used in conjunction with a clock synthesizer for the VIA Pro 266 chipset. The PLL103-02 also has an I2C interface, which can enable or disable each output clock. When powered up, all output clocks are enabled (have internal pull ups). PLL103-02 DDR5C DDR4C DDR4T GND VDD2.5 DDR3C DDR3T GND VDD2.5 DDR2C GND VDD2.5 DDR1C DDR0C DDR0T GND VDD2.5 FBOUT SDATA VDD2.5 DDR5T DDR2T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 N/C VDD2.5 GND DDR11T DDR11C DDR10T GND DDR6T DDR7T DDR7C GND SCLK BUF_IN DDR1T DDR6C BUF_IN SDATA SCLK I2C Control PD# DDR0T DDR0C DDR1T DDR1C DDR2T DDR2C DDR3T DDR3C DDR4T DDR4C DDR5T DDR5C DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T DDR10C DDR11T DDR11C

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2 PIN DESCRIPTIONS Name Number Type Description FBOUT 1 O Feedback clock for chipset. BUF_IN 13 I Reference input from chipset. PD 36 I Power Down Control input. When low, it will tri-state all outputs. N/C 48 Not connected. DDR[0:11]T 4,6,10,15,19, 21,28,30,34, 39,43,45 O These outputs provide Tr ue copies of BUF_IN. DDR[0:11]C 5,7,11,16,20, 22,27,29,33, 38,42,44 O These outputs provide complementary copies of BUF_IN. 32,37,41,47 P 2.5V power supply. GND 3,9,14,18,26, 31,35,40,46 P Ground.

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3 I2C BUS CONFIGURA TION SETTING Address Assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 _ Slave Receiver/Transmitter Provides both slave write and readback functionality Data Transfer Rate Standard mode at 100kbits/s Data Protocol This serial protocol is design ed to allow both blocks write and read from the controller. The bytes must be accessed in sequenti al order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD 2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte . Byte Count Byte default at power-up is = (0x09). I2C CONTROL REGISTERS 1. BYTE 6: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 48 1 Reserved Bit 6 - 0 Reserved Bit 5 - 0 Enhanced DDR Dr ive. 1 = Enhanced 25% Bit 4 - 0 Reserved Bit 3 45, 44 1 DDR11T, DDR11C Bit 2 43, 42 1 DDR10T, DDR10C Bit 1 39, 38 1 DDR9T, DDR9C Bit 0 34, 33 1 DDR8T, DDR8C 2. BYTE 7: Outputs Register (1=Enable, 0=Disable) Bit Pin# Default Description Bit 7 30, 29 1 DDR7T, DDR7C Bit 6 28, 27 1 DDR6T, DDR6C Bit 5 21, 22 1 DDR5T, DDR5C Bit 4 19, 20 1 DDR4T, DDR4C Bit 3 15, 16 1 DDR3T, DDR3C Bit 2 10, 11 1 DDR2T, DDR2C Bit 1 6, 7 1 DDR1T, DDR1C Bit 0 4, 5 1 DDR0T, DDR0C

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 4 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V DD 4.6 V Input Voltage, dc V I V SS -0.5 V DD +0.5 V Output Voltage, dc V O V SS -0.5 V DD +0.5 V Storage Temperature T S -65 150 °C Ambient Operating Temperature* T A -40 85 °C Junction Temperature T J 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specif ied by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. Thes e conditions represent a stress rating on ly, and functional operations of the devic e at these or any other conditions above the operational limits noted in this spec ification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only . 2. Operating Conditions PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V DD2.5 2.375 2.625 V Input Capacitance C IN 5 pF Output Capacitance C OUT 6 pF 3. Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Input High Voltage V IH All Inputs except I2C 2.0 V DD +0.3 V Input Low Voltage V IL All inputs except I2C V SS -0.3 0.8 V Input High Current I IH V IN = V DD TBM uA Input Low Current I IL V IN = 0 TBM uA Output High Voltage VOH IOL = -12mA, VDD = 2.375V 1.7 V Output Low Voltage VOL IOL = 12mA, VDD = 2.375V 0.6 V Output High Current IOH VDD = 2.375V, VOUT=1V -18 -32 mA Output Low Current IOL VDD = 2.375V, VOUT=1.2V 26 35 mA Note: TBM: To be measured

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 5 3. Electrical Specifications (Continued) PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current I DDS PD = 0 TBM mA Output Crossing Voltage VOC (VDD/2) -0.1 VDD/2 (VDD/2)+ 0.1 V Output Voltage Swing VOUT 1.1 VDD-0.4 V Duty Cycle D T Measured @ 1.5V 45 50 55 % Max. Operating Frequency 66 170 MHz Clock Skew ( pin to pin ) TSKEW All outputs equally loaded 100 ps Stabilization Time T ST 0.1 ms Note: TBM: To be measured

DDR SDRAM Buffer for Des ktop PCs with 4 DDR DIMMS 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 6

PACKAGE INFORMATION

ORDERING INFORMATION

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or bo th at any time without notice . The information furnished by PhaseLink is believed to be accurate and reliable . However, PhaseLink makes no guarantee or warranty concerning t he accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL103-02 X C Order Number Marking Package Option PLL103-02XC-R P103-02XC SSOP - Tape and Reel PLL103-02XC P103- 02XC SSOP - Tube 0.008 - 0.016 (0.20 - 0.41) 0.620 - 0.630 45 0 0.010 - 0.016 0.050 (1.346) MIN 30-60 0.015 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) 0.025 0.835 0.400 - 0.410 10.160 - 10.414 0.292 - 0.299 7.417 - 7.959 0.008 - 0.0135 0.203 - 0.343 48PIN SSOP PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE X=SSOP